JPS62288949A - Serializing instruction control system - Google Patents

Abstract

PURPOSE:To speed up serializing processing by adding an identifier indicating the serializing request source to a serializing request flag signal to perform the serializing processing overlapping between processors. CONSTITUTION:When the serializing request signal from a CPU 0 is accepted by a serializing control circuit 22 corresponding to the CPU 0, a serializing request flag and the identifier indicating the request source are supplied to a local pipeline 24 through a priority level circuit 23. The serializing request flag signal and the identifier transmitted to a tag memory 21 provided correspondingly to each CPU are fed back to the circuit 22. Since the identifier is encoded, it is decoded by the circuit 22 and a corresponding latch is reset. Thus, the following serializing instruction is started even during the processing of the preceding serializing instruction to overlap the serializing processing, and serializing instructions are processed at a high speed.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] At least a main storage unit (MSU), a plurality of central processing units (CPUs) each having a cache memory, and a system control unit (QICU) In a multiprocessor system that has a tag memory (TAG2) that temporarily holds a buffer invalidation address, when starting serialization processing and propagating it to another central processing unit, the serialization request source is specified in the serialization request flag signal. By providing means for adding an identifier (RQTRID) indicating the serialization request, subsequent serialization processing from another processing device can be continuously started while the preceding serialization request is being processed.

[Industrial application field]

The present invention provides at least a main storage device (MStl) and a plurality of central processing units (CPUs) each having a cache memory.
) and a serialization instruction control method in a multiprocessor system having a tag memory (TAG2) for temporarily holding a buffer invalidation address in a system control unit (MCI).

Conventionally, in a multiprocessor system equipped with a cache memory, the contents of the cache memory of each central processing unit (CPI) and the main memory (MSI)
In order to ensure consistency with the contents of I), a serialization instruction is provided.

The serialize instruction is an instruction for serializing store access in each central processing unit (CPU), and there are two types: pre-serialization and post-serialization.

The post-serialize instruction performs store access of the central processing unit (CPII) before the instruction is issued, and the post-serialize instruction performs the store access of the central processing unit (CPII) before the instruction is issued, including the store access started at the same time as the instruction is issued. CPU
) has a function of interrupting store access of CPUs in other central processing units (CPUs) in the system and terminating cache memory invalidation processing in other central processing units (CPUs) in the system.

On the other hand, the central processing unit (CPU) has a built-in cache memory consisting of a tag (TAGI) section and a data section for the purpose of speeding up processing.
When a processing device other than U) rewrites the contents of the master to device (MSU), it checks whether old data before being rewritten exists in the cache memory and checks if it exists. For example, the corresponding portion on the cache memory is invalidated.

This is called BT validation (BT) processing, and the address is called the Bl address, but usually the Bl
The address is temporarily held in Bl stack memory,
It is not processed immediately.

The above serialize instruction propagates this 81 address to all other processing units in the system, causing the processing unit that received it to temporarily suspend other processing, and instead It functions to perform Bl processing on unprocessed Bl addresses within the process, and to match the contents of the cache memory of the processing device with the contents of the main storage unit (MSU).

Central processing unit (CpH) that issued the serialization command
After confirming that the instruction has been transmitted to all other processing devices in the system, subsequent processing (store access) is resumed.

In such a serialization control method, as mentioned above, serialization processing (8
1 process) When the request is propagated to other processing units, the subsequent store access is resumed, so in a multiprocessor system, overload is required for serialization requests from multiple central processing units (CPII). An efficient serialization instruction control method that allows wrapping is needed.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram showing an example of the configuration of a conventional multiprocessor system, and FIG. 4 is a diagram showing an example of the configuration of an improved multiprocessor system. It is a diagram.

First, in the multiprocessor system shown in Figure 3,
Each central processing unit (hereinafter referred to as CPt1) 3 itself is aware of the address for the main storage unit (hereinafter referred to as MSU) and selects the system control unit (hereinafter referred to as MCU) to which the MSU 1 that it wants to access is connected. 2), the method is to issue the access.

In this method, the address of a store access issued by a certain CPU 3 is the address of the MCU0 that received the store access.
, or MCUI (2), all other CPUs 3 are notified. Each CPU 3 holds this store address in a Bl stack (not shown) provided in the memory, and sequentially executes Bl processing.

In a multiprocessor system having such a configuration, there is a problem in that (1) the number of interface lines between the MCUO or MCUI (2) and all the CPUs in the system increases. Particularly when the length of data to be processed is long, there is a problem in that the increased amount of hardware cannot be ignored.

■Also, for one CPII 3 (for example, CPLIO), multiple CPUs 3 (for example, CPU1, 2.3
-) Bl address may be sent from c
There was a problem in that the BT processing in puo (3) sometimes became congested, reducing the processing capacity of each CPU 3.

Therefore, the system shown in FIG. 4 was devised as a multiprocessor system to improve these problems.

In the improved multiprocessor system, M
MCUO that accepted the SU access request or MC old (2
) connects the corresponding MS[0,
1, 2, --(1) issues an access request.

For this reason, each MCU0, 1 (2) is the access source CPU 3
Corresponding to the
Remember the fetch address from the other CPU
When there is a store access from 3, it is compared with the access address, and if a match is detected, the matching address is used as the BI address and the CPU that is in charge of
Propagate to 3.

Each CPII 3 holds these 81 addresses in its own Bl stack, sequentially executes Bl processing, and invalidates the corresponding entry in the cache memory.

Normally, the TAG2 has multi-stage registers and a queue for temporarily holding addresses in order to speed up processing, but since they are not directly related to the present invention, the details are omitted here. do.

In this improved multiprocessor system,
One store address is propagated throughout the system as a Bl address (i.e., to each CPU via TAG2).
It takes some time until it is registered in the Bl stack of 3).

Therefore, when each CPU 3 issues a serialization instruction, it takes time to complete one serialization instruction as described above. Therefore, processing the serialization instructions without overlapping each other reduces the performance of the entire system. There was a problem that lowered the

On the other hand, when the serialization and rise instructions from each CPU 3 are processed by overlapping each other, multiple store access addresses are temporarily held in TAG2, so the completion of each serialization instruction cannot be guaranteed. There was a problem. Specifically, there was a problem in that the serial rice commands issued by each CPU 3 could no longer correspond to the B1 address.

In view of the above conventional drawbacks, the present invention adds an identifier (R (ITR10)) indicating the issuer of the serialization instruction when starting and propagating the serialization instruction to each central processing unit (C
By enabling over-ramp processing of serialization requests from PUs (PUs), even if one processing device is processing a preceding serialization request, subsequent serialization requests from other processing devices can be continuously activated and processed. , the purpose is to provide a method for preventing a decrease in processing speed.

[Means for solving problems]

FIG. 1 is a principle block diagram of the serialization command control system of the present invention.

In the present invention, at least a plurality of main storage devices and a plurality of central processing units (C
PUO, L2. --) 3 and the system control unit (MCU)
o, 1) 2, and a tag memory (
TAG2) In a multiprocessor system having 21, the plurality of central processing units (CPIIo, 1, 2.-)
In order to process three types of serialization requests, an identifier (RQTI 210) indicating the serialization request source is added to the serialization request flag signal to another central processing unit 3 when the serialization activation 1 is propagated. , each T
5ERI from AG2 to the central processing unit 3 in charge of it.
At the time when the serialization request flag is sent by the ALIZE OUT signal, each central processing unit (CPUO
,l,2,3. --) The serialization control circuit 22 provided for each central processing unit 3 is provided with a means for returning the serialization request flag signal and the identifier (RQTRID). 1' from another central processing unit 3
! In addition to continuously activating successive serialization requests, each serialization control circuit 22 recognizes the end of propagation of serialization requests issued by each central processing unit (CPU0, 1, 2, --) 3. Configure it to accept new serialization requests.

[Effect]

That is, according to the present invention, at least the main storage device (MS
LI), multiple central processing units (CPl, l) with cache memory, and system control unit (MCI)
When the serialization request flag signal is propagated to the multiprocessor system processing unit having a tag memory (TAG2) that temporarily holds the serialization request flag signal,
Identifier indicating the source of the serialization request (RQTR 10)
By providing a means to add , the subsequent serialization process from another processing device is started continuously while the preceding serialization request is being processed. This has the effect of enabling serialization processing and allowing serialization instructions to be processed at high speed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the serialization control circuit of the present invention, and shows an identifier (RQTR 10) input to TAG2 configured by the pipeline shown in FIG.

and a feedback circuit for the identifier (RQTR ID) in FIG. 2 are necessary means to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, while referring to the configuration of the improved multiprocessor system shown in FIG. 4, the structure shown in FIG. The serialization command control method of the present invention will be explained with reference to FIG.

In the system shown in Figure 4, each anus υ0,1(2)
Figure 1. There is a serialization control circuit 22 shown in FIG.

Here, CFl? -ENA-CPUI etc. are cr+uo, 1 to each MCIJO or MCtll (2)
,2,=(3) is energized when not connected and functions to forcibly reset the corresponding latch O-■ and inhibit access to the launch.

First, for example, when a serialization request signal from CPUO (3) is accepted by the serialization control circuit 22 corresponding to CPUO (3), the launches of ■ and O-■ are sent, and ■no latch (CPUO- SERIAL
IZE) via the priority circuit 23 to the local pipeline 24, a serialization request flag indicating that the serialization request has been activated, and the issuer of the serialization request generated by encoding the serialization request flag signal, for example. An identifier (1 unit TR 10) indicating this is input.

Of course, the above identifier (RQTR ID) is CPUO (
It goes without saying that the serialization request signal may be included in the serialization request signal from the beginning at the time when 3) issues the serialization command. In this case, the above encoding mechanism becomes unnecessary.

◎Lunch (INH-STOPE-BY-SERT8)
, the activation of store access from CrtlO (3), which is the source of the serialization request, is suppressed in the priority circuit 23 during the serialization period, and the store access of cpUo (3) is not activated until the end of this instruction. Not done.

An interface signal from the MCU 2 of another system is input to the remote pipeline 25, and the MCU 2 of the other system
The serialization request flag signal and the identifier (R
QTR ID).

The TAG2 21 provided corresponding to each CPU 3 receives necessary control signals, addresses, etc. from both the local and remote pipelines 24.25, and sends them to each CPU 3. Propagate the processing request as the old address.

The serialization request flag signal and the identifier (RQTRID) transmitted to the TAG221 are input into a queue (not shown) in the TAG221, and under the control of the TAG221, the serialization request flag signal (SERIALIZE-0
11T) The signals are sent to the corresponding CPUs 0, 1, 2 . -(3)
At the same time, the serialization control circuit 22, whose details are shown in FIG.
ID).

For example, since the identifier (RQTRID) is encoded as described above, it is decoded in the serialization control circuit 22 and operates to reset the corresponding launch among O-.

For example, the serialization instruction from CPU0 (3) is
For example, CPI other than CPIIOTAG2 (21)
II TAG2 (21) and CPUI TA
From G2 (21), the above serialization signal (CPUI
-TAG2-5ERIALIZE-011T) signal,
Identifier (RQIRID) (CPUI-TAG2-RQT
When R-ID-CP[IO] returns to the serialization control circuit 22 corresponding to cpllo (3),
O's launch is reset by the illustrated condition of PI'.

When all the launches up to G-① are reset in this way, the 0 latch is then reset, and the serialization instruction is completed.

The serialization signal (SERIALIZE-011T) signal sent by a certain TAG2 (21) and the identifier (
RQTRID) is fed back to all serialization control circuits 22 in the system, but since the identifier (RQTRID) added according to the present invention is code information indicating the issuer of the serialization instruction, the identifier (RQTRIn)
Only the corresponding launch existing in the serialization control circuit 22 corresponding to the access source CPU 3 indicated by is reset.

In this way, even if the preceding serialization instruction is being processed, the subsequent serialization instruction can be started and overlapped, and the serialization instruction can be processed at high speed.

As described above, the present invention provides a serialization control circuit and a TAG2 in the MCI corresponding to each CP[I in a multiprocessor system, so that a serialization request from a certain CPU is handled by a serialization control circuit corresponding to the CPU. When the circuit accepts the acceptance, it is propagated to other CPUs via all TAG2s other than the TAG2 corresponding to itself, causing each CPU to perform BT processing, and transmitting the serialization signal (SERIALIZE signal) from the other TAG2s.
-OUT) and the identifier (RQTRID),
When feedback signals from all the other TAG2s are received, it is recognized that the serialization process has ended, and the next serialization command is accepted, thereby overlapping the serialization process in multiple CPUs. The place has its own characteristics.

〔Effect of the invention〕

As described above in detail, the serialization instruction control method of the present invention uses at least a main storage unit (MSU) and a plurality of central processing units (CPUs) each having a cache memory.
PU) and a tag memory (TAG2) that temporarily holds the hasher invalidation address in the system control unit (MCI).
By providing means for adding an identifier (RQTR[0) indicating the serialization request source to the serialization request flag signal at the time of starting the serialization processing and propagating it to other processing devices, While the preceding serialization request is being processed, subsequent serialization processing from other processing devices is started continuously, so serialization processing can be performed in a consistent manner between each processing device, and serialization commands can be executed at high speed. There are effects that can be processed.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the serialization command control method of the present invention. FIG. 2 is a diagram showing an embodiment of the serial rice control circuit of the present invention. FIG. 3 is a diagram showing an example of the configuration of a conventional multiprocessor system. FIG. 4 is a diagram showing an example of the configuration of an improved multiprocessor system. It is. In the drawings, 1 is a main storage unit (MSUO, L2.-). 2 is a system control unit (MCIIO, 1). 3 is a central processing unit (CPU0.1.2.-), etc. 21 is a tag memory (TAG2). 22 is a serialization control circuit. 23 is a priority circuit. 24 is the local pipeline. 25 is a remote pipeline. ■~ is lunch. P1~ is the recess/throttle condition for latch O~.

Claims (1)

[Claims] Consisting of at least a plurality of main storage devices (1), a plurality of central processing units (3) equipped with cache memory, and a system control device (2) that performs main memory access control,
In a multiprocessor system having a tag memory (TAG2) that temporarily holds a buffer invalidation address in the system control unit (2), a serialization request flag signal from the plurality of central processing units (3) is processed. However, starting the serialization,
When propagating the serialization request to another central processing unit (3), an identifier (RQTR I) indicating the source of the serialization request is sent to the serialization request flag signal.
D) is provided, and by this means, even during serialization processing from a certain central processing unit (3),
A serialization command control method characterized in that a subsequent serialization request flag signal from another central processing unit (3) is controlled to be activated continuously.