JPH06332871A - Parallel processing system - Google Patents

Abstract

PURPOSE:To improve processing efficiency by unnecessitating interruption processing for synchronism after transfer by reporting transfer end to a processor at the transfer destination by a transfer end notice means together with the transfer of data. CONSTITUTION:It is decided whether the processor is in charge of a pivot line or not (S1). Processing 1 is executed by the processor decided as in charge of the pivot in the S1 (S2). The line data and transfer end flag of a k-th line are transferred from a processor in charge of the k-th line to the other processor (S3). The on/off of the transfer end flag is checked by the processor at the transfer destination (S4). When the flag is turned on, the processing is advanced to S5 but when the flag is turned off, the check is repeated. Concerning lines from a (K+1)-th line to an n-th line, processing 2 is respectively executed by processors in charge of respective lines (S5). The pivot is turned to ak+1 and ak+1 and processingis returned to the S1. The pivot line is changed from the 1st line up to the n-th line, this loop is repeated, and an upper trigonometric matrix is generated (S6). The solution of a simultaneous linear equation is calculated by backward substitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing system, and more particularly to a parallel processing system for processing matrix operations incorporated in a semiconductor design device by a parallel computer composed of a plurality of parallel processors.

[0002]

2. Description of the Related Art When simulating a physical phenomenon on a computer, a space to be divided is finely divided, and a linear differential approximation is performed on a grid point in order to analyze a partial differential equation representing the physical phenomenon. The coefficient matrix is created, and this coefficient matrix is calculated by an appropriate matrix solving method to obtain the physical quantity for each lattice point. Usually, the coefficient matrix is a large-scale matrix, and a lot of time is consumed in matrix calculation. One method for performing the matrix calculation at high speed is to perform parallel processing using a parallel computer.

A Gaussian elimination method is one of matrix solving methods. IPSJ, Information Processing Handbook No. 150-
As described on page 151, Ohmsha, 1989, the processing of the Gaussian elimination method consists of forward elimination and backward substitution, of which forward elimination consumes most of the computation time. Figure 4
To explain the Gaussian elimination with reference to the elements of the row i and column j a _ij, the current pivot or pivot to a _kk.
First, in order to set the pivot to 1, the element a _kj in the k-th row is set to a _kj
Replace with / a _kk (Process 1). Next, from the (k + 1) th row to the nth row
Process up to line. For example, if the element is a _ij , then a _{ij
-Replace with} a _ik * a _kj (Process 2). That is, this process 2
Is the target part of parallel processing.

When the above Gaussian elimination method is calculated using a parallel computer, the process 1 is performed between the process 1 and the process 2.
In order to ensure that the output data of (1) is transferred to all the processors that execute the process 2, synchronization among the above-mentioned processors constituting this parallel computer is required.

Referring to FIG. 5 which shows a flowchart of a conventional parallel processing system in which each row of an nth-order coefficient matrix is calculated by a parallel computer composed of m processors, first, at step P1, this processor makes this pivot row It is determined whether the person is in charge. In step P2, by the processor determined to be in charge of the pivot row in step P1,
Process 1 is executed. In Step P3, the row data of the kth row is transferred from the processor in charge of the kth row to all the other processors. Here, all the processors forming the parallel computer are synchronized with each other, and the processing is temporarily suspended until the data transfer between all the processors is completed. In Step P5, the processor in charge of each of the k + 1-th to n-th rows executes the process 2. In step P6, the pivot is set to a _{k + 1, k + 1} , and the process returns to step P1. The loop process is repeated by changing the pivot row from the first row to the n-th row to generate the upper triangular matrix. In step 7, the solution of the simultaneous linear equations is obtained by backward substitution.

The above Gaussian elimination method is applied to four processor PEs.
Referring to FIG. 6, which shows a time chart when processing is performed by a parallel computer including 0 to PE3 in a conventional parallel processing method, all processors PE0 to PE3 are synchronized after row data transfer of a pivot row after execution of processing 1. There is synchronous processing, and these processors PE0 to PE0 until all transfers are completed.
PE3 interrupts the process.

[0007]

In the conventional parallel processing method described above, all the parallel processors are synchronized until the transfer is completed because of the synchronous processing of all the parallel processors after the row data transfer of the pivot row after the execution of processing 1. Since the processor interrupts the processing, there is a drawback that the transfer time increases as the number of the processors increases, and the processing efficiency significantly decreases due to the increase of the interrupt time of each processor.

[0008]

A parallel processing system of the present invention is a parallel processing system of a large-scale matrix operation composed of coefficient matrices of simultaneous linear equations executed by a parallel computer composed of a plurality of processors. Each of the processors is provided with transfer end notifying means for indicating the end of the transfer of the row data of a predetermined processing target row to another processor when the row data is transferred by the first processor of the transfer source. At the same time, the transfer end notifying means notifies the transfer destination second processor of the transfer end, and the second processor confirms the transfer end by the notification and starts the next process. Each of the processors is controlled asynchronously.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, which is a flowchart showing one embodiment of the parallel processing system of the present invention, first, in step S1, it is determined whether or not this processor is in charge of this pivot row. In step S2, processing 1 is performed by the processor determined to be in charge of the pivot row in step S1.
To execute. In step S3, the row data of the kth row and the transfer end flag are transferred from the processor in charge of the kth row to another processor. In step S4, the transfer destination processor checks whether the transfer end flag is on or off. If the flag is on, the process goes to step S5, and if it is off, the check is repeated. In step S5, the processor in charge of each of the k + 1-th to n-th rows executes the process 2. In step S6, the pivot is set to a _{k + 1, k + 1} , and the process returns to step S1. The loop process is repeated by changing the pivot row from the first row to the n-th row to generate the upper triangular matrix. In step 6, the solution of the simultaneous linear equations is obtained by backward substitution.

Similar to the conventional example, referring to FIG. 2 which shows a time chart when the above-described Gaussian elimination method is processed by the conventional parallel processing method by the parallel computer having the four processors PE0 to PE3, the processing 1 is completed. The data PE and the transfer end flag are simultaneously transferred from the post-transfer source processor PE0 to each of the transfer destination processors PE1 to PE3. Each of the processors PE1 to PE3 immediately executes the process 2 when the check result transfer of the flag is completed.

Referring to FIG. 3, which shows a block diagram of a configuration example in which the present embodiment is applied to a semiconductor design apparatus, the semiconductor design apparatus includes an input device 1, an analysis mesh generation device 21, and a parallel processing system of the present embodiment. An arithmetic unit 2 including a matrix arithmetic unit 22 composed of a plurality of processors, a storage unit 3 such as a magnetic disk, a printer 41 and a CRT display 42.
And an output device 4 including.

In operation, the input device 1 inputs the structure and physical parameters of the semiconductor device to be designed. The analysis mesh generation device 21 finely divides the inside of the semiconductor device, linearly approximates a partial differential equation representing a physical phenomenon to be analyzed in the vicinity of each grid point, creates a simultaneous linear equation, and generates a coefficient matrix thereof. To do. Matrix operation device 22
Solves the simultaneous linear equations and finds the physical quantity on each grid point. The analysis result is supplied to the storage device 3, and further CR
The analysis result is output to the T display 42 and the printer 41.

[0014]

As described above, in the parallel processing method of the present invention, the transfer end notifying means notifies the transfer destination processor of the transfer end as well as the transfer of the data, so that the processing interruption for the synchronization after the transfer is prevented. There is an effect that it becomes unnecessary and the processing efficiency is improved.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a parallel processing system of the present invention.

FIG. 2 is a time chart showing an example of an operation in the parallel processing system of this embodiment.

FIG. 3 is a block diagram of a semiconductor design device to which the parallel processing method of this embodiment is applied.

FIG. 4 is an explanatory diagram of a Gaussian elimination method.

FIG. 5 is a flowchart showing an example of a conventional parallel processing method.

FIG. 6 is a time chart showing an example of operation in a conventional parallel processing method.

[Explanation of symbols]

 1 Input Device 2 Arithmetic Device 3 Storage Device 4 Output Device 21 Analysis Mesh Generation Device 22 Matrix Arithmetic Device 41 Printer 42 CRT Display

Claims (2)

[Claims] 1. A parallel processing method of large-scale matrix operation comprising a coefficient matrix of simultaneous linear equations executed by a parallel computer composed of a plurality of processors, wherein each of the plurality of processors has a row of a predetermined processing target row. When the data is transferred to another processor, there is provided transfer end notification means for indicating the end of transfer of this row data, and the first source processor is the transfer destination notification means by the transfer end notification means simultaneously with the transfer of the row data. 2, the second processor notifies the end of the transfer, the second processor confirms the end of the transfer by the notification, and starts the next process, whereby each of the plurality of processors is asynchronously controlled. And parallel processing method. 2. The transfer end notification means is a flag which is set when the transfer is completed, wherein the first processor of the transfer source sets the flag simultaneously with the row data to the second processor of the transfer destination. 2. The parallel processing method according to claim 1, wherein the second processor starts the next processing when the flag is in the set state.