JPS6293742A - Inter-processor interface system - Google Patents

Abstract

PURPOSE:To constitute the titled system so that an operation for delivering a parameter from a master processor to a slave processor can be executed in parallel and simultaneously in each processor, by separating a local bus and a system bus by using a bus buffer, and also coupling the local bus and system bus by an FIFO buffer. CONSTITUTION:Among instructions which a master processor has fetched from a memory device 1 and has decoded, as for that which is executed by a slave processor 4, its parameter is written in an FIFO buffer 10 of the object slave processor 4. On the other hand, the slave processor 4 always monitors the FIFO buffer 10, therefore, even in a state that the slave processor 4 does not have the right of using of a system bus 2, then fetching a parameter which is sent from the master processor 3 from the FIFO buffer 10, and taking into a register of the inside of the slave processor is made possible. After the delivery of all parameters has been completed, the master processor 3 gives the right of using of the system but to its slave processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface system between processors. In particular, it relates to an interface between a master processor that executes and decodes instructions and a slave processor that executes special instructions.

〔overview〕

In an inter-processor interface system between a master processor and a slave processor, the present invention separates a system bus from a local bus belonging to each processor using a bidirectional bus buffer, and uses a FIFO buffer between the system bus and the local bus. By connecting the slave processor and allowing the slave processor to independently retrieve the parameters sent from the master processor via this FIFO, the slave processor can transfer the parameters from the master processor to the slave processor even if the slave processor does not have the right to use the system bus. This allows the operation of passing parameters to each processor to be performed in parallel and at the same time.

[Conventional technology]

Conventionally, this type of interface method is a method in which parameters are directly transferred from a master processor to a slave processor, or a method in which parameters are transferred within a memory device.
There are methods such as setting up an area for the master processor and interrupting the slave processor after the master processor writes the parameters to memory.

[Problems to be Solved by the Invention] However, such conventional inter-processor interface systems have the following problems.

The method of directly transferring parameters from the master processor to the slave processor 7 has the disadvantage that the master processor and slave processor must be synchronized each time one parameter is transferred. For this reason, there was a problem in that it took time to pass parameters, making it impossible to execute instructions at high speed.

In addition, by setting an area for parameter passing in the memory device, the master processor's parameter writing operation and the slave processor's parameter retrieving operation are completely serialized, which makes parameter passing easier than direct parameter passing between processors. The disadvantage is that it takes time.

Further, using a memory device for passing parameters means using a part of the memory device for interfacing between hardware, and the memory area for instructions and data is compressed.

The present invention solves these conventional problems,
It is an object of the present invention to provide an inter-processor interface method in which the operation of passing parameters from a master processor to a slave processor can be performed in parallel and simultaneously in each processor.

[Means for solving problems]

The present invention includes a memory device for storing instructions and data;
A system bus that connects one master processor that retrieves and decodes and executes instructions, one or more slave processors that executes instructions, the memory device and each processor, and is used by one processor that has usage rights. an inter-processor interface system comprising: a local bus provided inside each of the processors; a bidirectional bus buffer that separates the local bus from the system bus; and a bidirectional bus buffer that transmits information from the system bus to the local bus. The master processor includes FIFOs C and F, and among the instructions read out and decoded from the memory device, the slave processor executes the following:
The parameter is set to FFO of the target slave processor.
The present invention is characterized in that the slave processor includes means for giving the right to use the system bus to the slave processor after writing to the data processor, and the slave processor frequently includes means for monitoring the presence or absence of data in its own FIFO buffer.

[For production]

Among the instructions retrieved and decoded from the memory device by the master processor, those to be executed by the slave processor are transferred to the FIF of the target slave processor.
Write to O buffer. On the other hand, the slave processor is FI
By constantly monitoring the FO buffer, even if the slave processor does not have the right to use the system bus, it is possible to retrieve parameters sent from the master processor from the FIFO buffer and store them in the slave processor's internal registers. . Mask Broce Nosa is
After all parameters have been passed, use of the system bus is granted to the slave processor.

Furthermore, since a FIFO buffer is used, overload due to differences in processing speed between the master processor and slave processors can be minimized.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, a memory device 1 is connected to a system 2
The master processor 3 and slave processor 4 are connected to each local bus 5.6, and the system bus 2 and each local bus 5.6 are connected to a bidirectional bus buffer 7.8 and a local bus 5.6 from the system bus 2 side. bus 5
．． FIFO hasher sofa that stores parameters to the 6th side 9.
10.

Memory device 1 stores instructions and data, and is accessed by master processor 3 or slave processor 4 via system bus 2 . The master processor 3 is normally active and fetches, decodes and executes instructions. That is, the system bus 2 is exclusively used by the master processor 3. At this point, the local bus 5 and system bus 2 on the master processor 3 side
A bus buffer 7 located between the two serves as a data path from the system bus 2 to the local bus 5 or from the local bus 5 to the system bus 2, depending on the bus operation of the master processor 3.

On the other hand, the slave processor 4 is normally inactive and starts operating in response to a command from the master processor 3. Therefore, the bus buffer 8 on the slave processor 4 side
is disabled. However, the FIFO connected to the local bus 6 on the slave processor 4 side
The buffer 10 is accessible from the slave processor 4.

Next, the operation of the system of the present invention will be explained by taking up instructions using the slave processor 4.

FIG. 2 is a diagram showing an example of an instruction format using a slave processor. The instruction code (OP) 1) indicates the type of instruction, such as transfer of a character data string. The data descriptor 1 (DDI) 12 has information such as the method of calculating the address where the first operand exists, the length of the data, and the type of data. Additional word 1 of data descriptor ■
3 is the displacement information necessary for calculating the address of the operand. data descriptor II
(DDII) 14 and additional word 15 of data descriptor ■
The content is the same as the additional word 13 of data descriptor 1) 2 and data descriptor I, but it includes information regarding the second operand.

The master processor 3 transfers the instruction code 1) to the memory device 1.
When the instruction is retrieved from and decoded, it is recognized that this instruction is executed by the slave processor 4.

Master processor 3 writes instruction code 1) into FIFO buffer 10 of slave processor 4 using an input/output instruction. slave processor 4
is always in the FIFO buffer 10 in the idle state.
Since the master processor 3 writes instruction code 1), it immediately imports this instruction into the slave processor 4.
Start deciphering the command. The master processor 3 then retrieves the data descriptor 1) 2 from the memory device 1, sends it to the FIFO buffer 10 of the slave processor 4, decodes the addressing, calculates the effective address of the operand, and also outputs the value as I'lFO. Write to buffer 10.

When all parameters have been transferred, the master processor 3 transfers the right to use the system bus 2 to the slave processor 4. After this, the slave processor 4 executes the instruction using the passed parameters. After completing the instruction execution, the slave processor 4 transfers the FIF of the master processor 3.
The completion status is written to the O buffer 9 and control of the system lotus 2 is returned to the master processor 3.

〔Effect of the invention〕

As explained above, the present invention separates the local bus and system bus using a hash buffer, and also connects the local bus and system bus with a 'c F I F O buffer. The operation of passing parameters to can be performed in each processor in parallel and simultaneously using FIFO buffers.

Therefore, parameters are quickly passed from the master processor to the slave processor, and there is an advantage that high-speed execution of instructions is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of an instruction format using a slave processor. 1...Memory device, 2...System bus, 3...
Master processor, 4... slave processor, 5.
6...Local bus, 7.8...Bus buffer, 9
．． 10... FIFO fin, 1)... Instruction code, 12... Data descriptor I, 13... Additional word of data descriptor ■, 14... Data descriptor ■, 15...
...Additional word of data descriptor H.

Claims (1)

[Claims] (1) A memory device that stores instructions and data, one master processor that retrieves, decodes, and executes instructions, and one or more slave processors that executes instructions. The memory device and each of the processors are connected. , in an inter-processor interface system including a system bus used by one processor having usage rights, a local bus provided inside each of the processors, and a bidirectional bus buffer that separates this local bus from the system bus. , and a FIFO buffer for transmitting information from the system bus to the local bus, and the master processor transfers the parameters of the instructions retrieved and decoded from the memory device and executed by the slave processor to the target slave processor. A processor characterized in that the slave processor includes means for granting the right to use the system bus to a slave processor after writing to a FIFO buffer of the processor, and the slave processor includes means for frequently monitoring the presence or absence of data in its own FIFO buffer. interface method.