JP2663893B2 - Architecture simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to an architecture simulator for analyzing the architecture and performance of a computer system.

[0002]

2. Description of the Related Art With the recent development of semiconductor technology, various computer systems have been devised and put into practical use.

[0003] Early computer systems were relatively simple in construction, so their processing capacity was limited to a central processing unit (CPU).
, But to further improve processing capacity,
Hierarchical memory structure, multiple buses, write buffer (wr
ite Buffer) and its architecture is becoming more complex. As a result, the performance of the computer system is
It has become strongly dependent not only on the processing capability of the (CPU) itself, but also on the architecture of the entire computer, such as the memory, bus, and I / O. Therefore, in order to develop a computer or to operate a program at a high speed on a specific computer, it is necessary to optimize the program according to the architecture or optimize the hardware according to the program.

[0004] Under the above-mentioned background, an architecture simulation technique is attracting attention as a simulation means for obtaining the operation of hardware in advance by simulation and optimizing the operation.

A conventional architecture simulator is:
For example, the technical report “Tango: A Multiprosessor Simulation and Tracing Sy
stem (YML-TR-90-439) ", which is a trace-driven system that collects the instruction sequence at the time of program execution using a tracer such as a logic analyzer and analyzes it with another program. Is shown in FIG. 4 and the operation will be described.

A conventional architecture simulator is:
Stores a PE / memory function model 41 that defines the functions and operations of the processor elements and the memory system constituting the computer, a PE timing model 42 that defines the timing information on the operation of the processor elements, and stores partial timing information of the memory. A memory timing model 43 storing detailed memory timing information, a memory timing model 45 storing detailed memory timing information, and a memory timing simulator 46 for simulating a memory operation based on the memory timing model 45. Is done.

When simulating the architecture of a computer composed of a plurality of processor elements, the execution instruction sequence includes a
Output the execution instruction of each processor element as trace data 402 while referring to the memory function model 41 and the PE timing model 42. If arbitration between processors is necessary, such as access to a shared memory, the access order is determined with reference to the partial memory timing model 43. After collecting the trace data,
The timing simulator 46 executes each trace file 402
The operation of each processor element is determined with reference to the memory timing model 45.

[0008]

The above-mentioned conventional architecture simulator has an advantage that a simulation method is relatively simple and a simulation of a single processor element can secure sufficient accuracy. In the processing, the processing speed is slow because the processing is performed while sequentially translating the instruction sequence, and the detailed operation analysis of the multiprocessor system is difficult because a partial memory timing model is used. However, there is a disadvantage that a huge amount of storage device is required for creating the data.

[0009]

An architecture simulator according to the present invention detects a system call part from a system call function model defining functions and operations of a system call part of a computer system, and an instruction of an execution program. A system call analysis module for referring to a system call function model to determine the operation of the computer; a PE / memory function model defining functions and operations of a processor element and a memory system constituting the computer; PE timing model defining the timing information of the above, operation information of the computer determined by the system call analysis module, the PE / memory function model and the PE
An address generator that determines a memory address to be referred to by the computer from the function / timing information defined by the timing model and generates reference memory address information; and a memory that stores timing information on the operation of the memory system of the computer. A memory timing simulator configured to determine an operation of the memory system based on the timing model, the reference memory address information determined by the address generator, and the memory timing model.

[0010]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the architecture simulator of the present invention. 11 is a system call function model, 12 is a system call analysis module, 13 is a PE timing model, 14 is a PE / memory function model, 15 is an address generator, 16 is a memory timing model, and 17 is a memory timing simulator.

The system call function model 11 stores an operation model of a system call section which is a function of the operating system (OS). The operation model is represented by an execution instruction sequence when executing each system call. When a system call has an argument, an operation model is described using the argument as a variable. The system call analysis module 12 detects a system call part from the instruction sequence executed by the execution application 101, expands the system call into the execution instruction sequence with reference to the system call function model 11, and adds the extended instruction sequence 103 to the execution instruction sequence. Output. In the extended instruction sequence, the system call part is also expanded into the execution instruction sequence, and the reference relation of the instruction to be executed is completely resolved. The PE timing model 13 stores timing information such as bus access and memory access of the PE (processor element), and obtains timing information of various operations generated by the PE during operation by referring to the timing information. PE / memory function model
14, stored functional model of PE and memory,
The functional operation of the PE and the memory is determined from the reference address information. The address generator 15 inputs the extended instruction sequence 103, extracts memory and I / O access information from the instruction sequence, accesses the PE / memory function model 14, and determines the operation of the PE and the memory. Further, based on the determined operation, the PE timing model 13 is accessed 105 to resolve the timing of the PE operation such as the bus access time and the memory access time. Based on this timing, the memory timing simulator 17 is accessed 106 to solve the memory access timing problem. In the case of a shared memory type multiprocessor, the operation may greatly differ due to contention for access to a shared variable. However, since the address generator 15 strictly manages the operation time of each PE, accurate simulation can be performed. In this manner, the simulation of the architecture is executed, and the trace information 108 for each processor is obtained.
Is output. The memory timing model 16 stores an operation timing model of a memory such as an access time.
The memory timing simulator 17 refers to the memory timing model 16 to resolve timing at the time of memory access.

FIG. 2 shows a detailed configuration example of the memory timing simulator 17. 21 is a cache model, 22 is a bus model, 23 is a memory model, and 24 is an I / O model.
Since this configuration depends on the hardware architecture to be simulated, it is necessary to prepare a model according to the configuration of the hardware to be simulated.
The memory access information 106 is input to the cache model 21, and a cache hit / miss hit is determined. In the case of a mishit, the memory access information 106 is a bus model
Entered in 22. In the bus model 22, the bus time is added to the access time based on the bus delay, and the memory model 23 and the I / O model 24 are referred to by the reference address. In the memory model 23, the access time of the memory is added, and the end time of the memory access information 106 is determined. In the I / O model 24, the access times of various I / Os are added to determine the end time of the memory access information 106.

FIG. 3 shows an operation example of the architecture simulator of the present invention. The application to be simulated is compiled by a general procedure and converted into assembler code (step 1). In the assembler code, a system call part is extracted by the system call analysis module, and a system call execution instruction is extended (step 2). The extended instructions are converted into binary by an assembler (step 3), and are linked to a PE timing model, a PE / memory function model, an address generator, and a memory / timing simulator to become an execution module (step 4). When the program is executed, the application code is directly executed as in the prior art, and at the time of memory access, the architecture simulator of the present invention is called as a subroutine to evaluate the architecture.

[0015]

As described above, the architecture simulator of the present invention links the architecture simulator to the application to be simulated and directly executes the architecture simulator. Therefore, there is almost no reduction in processing speed, and the timing is strictly controlled by the memory timing model. Since information is managed, it is possible to accurately evaluate the operation of the shared memory of the multiprocessor, and since there is no need to create a trace file during simulation, there is no need for a storage device for storing trace data. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a memory timing simulator in the figure.

FIG. 3 is a diagram showing an operation example of the architecture simulator of the present invention.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 11 System call function model 12 System call analysis module 13 PE timing model 14 PE memory function model 15 Address generator 16 Memory timing model 17 Memory timing simulator 21 Cache model 22 Bus model 23 Memory model 24 I / O model

Continuation of the front page (56) References JP 1-2229328 (JP, A) JP 6-95891 (JP, A) IEICE Technical Report SS D85-79 Ryuichi Takahashi "Hardware Architecture Simulator" ： PALS IM ”Information Processing Society of Japan Research Report ARC102-5 Masato Takahashi et al.“ Performance evaluation of shared bus coupled MP with multi-stage cache using trace driven architecture simulator ”

Claims (2)

(57) [Claims] A system call function model that defines functions and operations of a system call section of a computer system;
A system call analysis module that detects the system call unit from an instruction of an execution program, refers to the system call function model, and determines an operation of the computer;
A PE / memory function model defining functions and operations of a processor element and a memory system constituting the computer; a PE timing model defining timing information on operation of the processor element; and the computer determined by the system call analysis module. An address generator that determines a memory address to be referred to by the computer and generates reference memory address information based on the operation information and the function / timing information defined by the PE / memory function model and the PE timing model; The operation of the memory system is performed according to a memory timing model storing timing information on the operation of the memory system, the reference memory address information determined by the address generator, and the memory timing model. Architecture simulator, characterized in that it comprises a memory timing simulator constant. 2. In the memory timing simulator, memory access information is input to a cache model, a cache hit / mishit is determined, and in the case of a mishit, memory access information is input to a bus model. Then, based on the bus delay, a bus delay is added to the access time, and the memory model and the I / O model are referred to by the reference address. In the memory model, the access time of the memory is added and the end time of the memory access information is determined. 2. The architecture simulator according to claim 1, wherein in the I / O model 24, access times of various I / Os are added to determine an end time of the memory access information.