JP5440083B2 - Simulation apparatus, method and program - Google Patents

Description

  The present invention relates to a simulation apparatus, method, and program for a system including a processor.

  A processor such as a CPU or DSP has a complicated internal configuration. Processors and systems equipped with processors are required to evaluate the performance of the entire system and confirm the performance by operating software close to the actual application before the detailed design of the hardware. Yes. Therefore, a simulation that faithfully reproduces the hardware is performed at the stage where the actual hardware at the pre-design stage does not exist.

  FIG. 1 is a diagram showing a basic configuration of a system including a processor (processor core), where (A) shows the configuration of the system and (B) shows the internal configuration of the processor core.

  As shown in FIG. 1A, the system includes a processor core 1, a bus 2, a high speed memory 3, a low speed memory 4, a DMAC 5, an accelerator 6, an external I / F 7, an external HW (hardware). Wear) pseudo 8. The processor core 1, the high speed memory 3, the low speed memory 4, the DMAC 5, and the accelerator 6 are connected to each other via the bus 2. The external HW pseudo 8 is connected to other elements via the external I / F and the bus 2. The example shown in FIG. 1A is a basic configuration of the system, and it goes without saying that there can be various modifications such as including a plurality of processor cores.

  As shown in FIG. 1B, the processor core 1 includes an instruction cache 11, an instruction fetch unit 12, an instruction decoding unit 13, an instruction execution unit 14, and a data cache 15. The instruction cache 11 stores instructions input from the bus 2. The data cache 15 stores data input from the bus 2 and stores data output to the bus 2. The instruction fetch unit 12 reads instructions from the instruction cache 11 in the order of execution and outputs them to the instruction decoding unit 13. The instruction decoding unit 13 decodes the instruction and outputs it to the instruction execution unit 14. The instruction execution unit 14 executes the decoded instruction. The instruction execution unit 14 reads data necessary for executing the instruction from the data cache 15 and stores data obtained as a result of executing the instruction in the data cache 15. When an instruction stored in the instruction cache 11 is executed using data stored in the data cache 15, the instruction can be executed in a predetermined cycle. On the other hand, when executing an instruction not stored in the instruction cache 11, it is necessary to read the instruction into the instruction cache 11 via the bus 2. In this case, the time required to input an instruction to the instruction cache 11 is not constant depending on the situation due to the right to use the bus. Further, when data necessary for executing an instruction is not stored in the data cache 15, it is necessary to read the data into the data cache 15 via the bus 2. Also in this case, the time required to input an instruction to the data cache 15 is not constant depending on the situation due to the right to use the bus. The time (number of cycles) from fetching an instruction to starting execution is called latency. Accordingly, when executing an instruction not stored in the instruction cache 11 and when data required for executing the instruction is not stored in the data cache 15, the latency is not constant. A case where an instruction to be executed is not stored in the instruction cache 11 and a case where data necessary for executing the instruction is not stored in the data cache 15 are referred to as a cache miss. When a cache miss occurs, an instruction or data is loaded into the instruction cache 11 or the data cache 15 by the cache hardware. Since the above configuration is widely known, further description is omitted. Note that the example shown in FIG. 1B is a basic configuration of the processor core, and it goes without saying that various modifications can be made.

  The simulation apparatus is realized by software in a computer. FIG. 2 is a diagram showing a hardware configuration of a widely known computer. As shown in FIG. 2, the computer includes a CPU 81, a memory 82, a storage device 83, a display device 84, an input device 85, a drive device 86 that drives a disk device 87 that is an external memory, and a bus 88. . A description of the computer is omitted.

  As a simulation apparatus that performs performance evaluation, there are an instruction level simulation apparatus that performs simulation while paying attention to the operation of each processor in units of instructions, and a logic level simulation apparatus that performs simulation while paying attention to the operation of each cycle of processors. Widely used.

  FIG. 3 is a diagram for explaining the simulation by the instruction level simulation apparatus. As shown in FIG. 3, in the instruction level simulation, interpretation and execution are performed for each instruction, and the time required for executing the instruction is accumulated, so that the processor in the case where the instruction sequence is executed in the system that is a performance evaluation target. Calculate the processing time. In the example shown in FIG. 3, since normal instructions are processed one instruction per cycle in a pipeline operation, the time for one cycle per instruction is accumulated as the processor processing time. In the case of a load instruction in which a cache miss or the like occurs, a time obtained by adding a main memory access time assumed to be a predetermined value to the internal latency is accumulated in the processing time of the processor.

  Since the instruction level simulation shown in FIG. 3 simulates the operation of the processor in units of instructions, the simulation can be performed at high speed. However, since the hardware configuration inside the processor is not faithfully reproduced, the internal state of the operating processor cannot be reproduced. Therefore, when the processor that is the target of performance evaluation has complicated mechanisms such as a non-blocking cache and a branch predictor, the operation of these mechanisms cannot be expressed by the instruction level simulation. Therefore, the instruction level simulation cannot accurately evaluate the performance of the processor. In the example of FIG. 3, the time required for main memory access is not constant.

  On the other hand, a logic level simulation apparatus used for hardware verification can be used for performance evaluation.

  FIG. 4 is a diagram for explaining the simulation by the logic level simulation apparatus. As shown in FIG. 4, in the logic level simulation, the operation of the processor is simulated one cycle at a time, and when the execution of the instruction sequence of the performance evaluation target processor is completed, the processor simulation is performed based on the number of cycles of the simulation. Calculate the processing time. For example, as shown in FIG. 2, instruction 2 accompanies main memory access, but reproduces the actual main memory access and faithfully reproduces the time required for processing. When using the write data by accessing the main memory (external memory) where the instruction 2 is generated in the instruction 5, the process waits until the data writing by the main memory access is completed, and calculates the time (number of cycles) required for the wait. Is done.

  Since the logic level simulation faithfully reproduces the hardware inside the processor, the internal state of the processor can be accurately reproduced. For this reason, even if the performance evaluation target processor has a complicated mechanism, the performance of the processor can be accurately evaluated.

  However, in the logic level simulation, it is necessary to faithfully simulate the processing of each cycle of each instruction in the processor, and the amount of calculation required for the simulation is increased as compared with the instruction level simulation. Therefore, the logic level simulation is slower than the instruction level simulation, and the simulation time is longer.

  As explained above, there is a trade-off between accuracy and speed in simulations that perform performance evaluation. When performing performance evaluation with high accuracy, the simulation becomes slow, and the accuracy must be lowered to speed up the simulation. .

Japanese Patent Laid-Open No. 1-067645 JP-A-8-110919 JP 2001-273340 A

  Embodiments describe a simulation apparatus and method that achieves high speed while maintaining accuracy.

  A first aspect of an embodiment is a simulation apparatus of a system including a processor, and an instruction level simulation unit that executes simulation in units of instructions for an operation capable of calculating latency by simulation in units of instructions, and in units of instructions A logic level simulation unit that performs simulation in cycle units that reproduces system hardware for operations whose latency cannot be calculated by simulation, and a resource management table that stores time information when resources used in the simulation can be used And a resource management unit. The instruction level simulation unit requests the logic level simulation unit to execute the simulation in the cycle unit when the latency cannot be calculated by the instruction unit simulation. In response to this, the logic level simulation unit notifies the resource management unit of time information at which the resources used in the simulation can be used, based on the requested simulation results in cycle units. In response to this, the resource management unit stores time information at which resources used in the simulation can be used.

  A second aspect of the embodiment is a method for simulating a system including a processor, and performs an instruction-by-instruction simulation for an operation whose latency can be calculated by an instruction-by-instruction simulation. In the case of an operation where latency cannot be calculated, a simulation is performed for each cycle that reproduces the system hardware. Based on the result of the simulation for each cycle, the resources related to the latency of operations for which latency cannot be calculated are Stores available time information.

  According to the embodiment, a system including a processor can be simulated at high speed while maintaining accuracy.

FIG. 1 is a diagram illustrating a configuration of a system including a processor to be simulated and a configuration of the processor. FIG. 2 is a diagram illustrating a hardware configuration of a general computer in which the simulation apparatus is realized. FIG. 3 is a diagram for explaining a general instruction level simulation operation. FIG. 4 is a diagram for explaining the operation of a general logic level simulation. FIG. 5 is a diagram illustrating a configuration of the simulation apparatus according to the first embodiment. FIG. 6 is a diagram for explaining the operation of the instruction level simulation unit in the first embodiment. FIG. 7 is a diagram for explaining the operation of the logic level simulation unit in the first embodiment. FIG. 8 is a diagram illustrating a configuration of the resource management unit in the first embodiment. FIG. 9 is a block diagram showing a simulation operation in the first embodiment. FIG. 10 is a flowchart showing the operation in the first embodiment. FIG. 11 is a time chart of a simulation operation example in the first embodiment. FIG. 12 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 13 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 14 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 15 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 16 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 17 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 18 is a diagram illustrating changes in values in the resource management table of the resource management unit when the simulation operation in the first embodiment is performed. FIG. 19 is a block diagram showing a simulation operation in the second embodiment. FIG. 20 is a time chart of a simulation operation example in the second embodiment.

  The simulation apparatus (simulator) of the first embodiment is realized by software on a computer having a hardware configuration as shown in FIG. 2, and simulates a system having a processor as shown in FIG.

  FIG. 5 is a functional block diagram of the simulation apparatus (simulator) of the first embodiment. As shown in FIG. 5, the simulation apparatus includes an instruction level simulation unit 21, a logic level simulation unit 22, a resource management unit 23, and a control unit (scheduler) 24.

  The instruction level simulation unit 21 performs a simulation in units of instructions for an operation that can calculate latency by a simulation in units of instructions. The logic level simulation unit 22 executes a cycle unit simulation that reproduces the system hardware for an operation in which the latency cannot be calculated by the instruction unit simulation. The resource management unit 23 stores time information at which resources such as registers, arithmetic units, and ports in the processor used in the simulation can be used. Further, the resource management unit 23 stores information related to a series of instructions for performing a simulation. The scheduler 24 controls the start request to the instruction level simulation unit 21 and the logic level simulation unit 22 and release of waiting.

  The instruction level simulation unit 21 requests the logic level simulation unit 22 to execute a simulation in cycle units and can use resources used in the simulation when the operation cannot perform latency calculation by simulation in units of instructions. The resource management unit 23 is notified that the time to be unknown is unknown.

  The logic level simulation unit 22 executes the simulation in the requested cycle unit, and notifies the resource management unit 23 of time information at which the resources used in the simulation can be used based on the result. When the execution of the simulation in the requested cycle unit is completed, the logic level simulation unit 22 determines whether or not an unprocessed request remains, and if it remains, executes the simulation in the requested cycle unit. If it does not remain, the operation is stopped.

  The resource management unit 23 stores information related to instructions executed in the simulation, and stores time information at which resources used in the simulation can be used. Note that the instruction level simulation unit 21 continues the simulation for each instruction until it detects a subsequent instruction that requires the latency for the operation that cannot calculate the latency after the operation that cannot calculate the latency by the simulation for each instruction. To do. Then, the instruction level simulation unit 21 stops the simulation in units of instructions when a subsequent instruction that requires a latency of an operation that cannot calculate the latency is detected. When the resource management unit 23 updates the time information when the resource required by the subsequent instruction becomes available, the instruction level simulation unit 21 resumes the simulation in units of instructions and uses the updated time information to execute the instruction. Continue simulation in units.

  When the resource used by the instruction level simulation unit 21 is unavailable and waiting, the scheduler 24 is notified of the time when the resource becomes available from the logic level simulation unit 22. Release the wait for. Further, when the instruction level simulation unit 21 makes a simulation request to the logic level simulation unit 22, the scheduler 24 cancels the waiting of the logic level simulation unit 22 waiting for the request.

  FIG. 6 is a diagram for explaining the operation of the instruction level simulation unit 21 and shows an example of simulating the process A in which the resource B of the resource management unit 23 is used and the result is stored in the resource A at time a. Here, the resource management unit 23 includes an instruction storage unit 23A that stores instructions for processing to be executed in the simulation, and a resource information storage unit 23B that stores information about resources.

  In response to the simulation start request from the scheduler 24, the instruction level simulation unit 21 selects the process A at time a stored in the instruction storage unit 23A of the resource management unit 23. The instruction level simulation unit 21 determines whether the process A can be processed from the information of the resource B stored in the resource information storage unit 23B of the resource management unit 23. If it is determined that the processing is possible, the processing A is executed using the resource B, the latency is calculated from the type condition of the processing A, and the resulting latency is determined as the resource A in the resource information storage unit 23B of the resource management unit 23. To store. If logic level simulation is necessary according to the type of process to be executed, conditions, etc., the logic level simulation unit 22 is requested to perform logic level simulation. The instruction level simulation unit 21 can be realized by the general method described with reference to FIG.

  When the instructed process A does not exist in the instruction cache 11 or when the resource B to be used is not usable, the instruction level simulation unit 21 determines that the process is not possible and stops the simulation and waits.

  FIG. 7 is a diagram for explaining the operation of the logic level simulation unit 22. In response to a request (processing request) from the instruction level simulation unit 21, the logic level simulation unit 22 faithfully reproduces a state machine, a pipeline, a queue structure, and the like inside the processor hardware and performs a simulation. The logic level simulation unit 22 notifies the resource management unit 23 of the time required for processing. The resource management unit 23 adds the processing time calculated by the logic level simulation unit 22 to the processing latency to calculate the time when the resource can be used. The logic level simulation unit 22 can be realized by the general method described with reference to FIG.

  FIG. 8 is a diagram illustrating a configuration of the resource management unit 23. As shown in FIG. 8, the resource management unit 23 includes a resource management table and an instruction execution time calculation unit 33. The resource management table is divided into a first resource management table 31 and a second resource management table 32. The first resource management table 31 stores entry numbers, instruction types, used resources 1, used resources 2, used resources 3, and usable time (latency) in association with each other. The second resource management table 32 stores an available time for each resource of the first resource management table 31. The instruction execution time calculator 33 calculates and outputs the instruction execution time from the available time corresponding to the instruction in the first resource management table 31 and the available time of the resource used in the second resource management table 32. Here, the instruction execution time calculator 33 selects and outputs the maximum value of a plurality of related available times. The resource management unit 23 has a queue structure (FIFO) and realizes a pipeline register that processes entries in order.

  FIG. 9 is a block diagram for explaining the operation in the first embodiment. In FIG. 9, the instruction level simulation unit 21 is divided into an instruction execution simulation unit 21A that simulates an instruction execution operation and a cache simulation unit (instruction unit) 21B that simulates an access operation to the cache. Similarly, the logic level simulation unit 22 is divided into a cache simulation unit (cycle unit) 22A that simulates an access operation to a cache, and a bus / memory simulation unit 22B that simulates access to a bus and a memory. It is.

  The scheduler (transfer control) 24 outputs a simulation start request to the instruction execution simulation unit 21A in units of instructions. In response to this, the instruction execution simulation unit 21A obtains an executable instruction from the resource management unit 23 and starts an instruction level simulation operation. If internal simulation is possible, the instruction execution simulation unit 21A performs a simulation and outputs the result to the resource management unit 23. To store. Further, the instruction execution simulation unit 21A requests a cache access from the cache simulation unit (instruction unit) 21B if cache access is necessary for execution of an instruction. The cache simulation unit (instruction unit) 21B receives a cache access and performs a cache access simulation. If there is a cache hit (there is an instruction or data in the cache), the cache simulation unit (instruction unit) 21B notifies the resource management unit 23 of the simulation result. If there is a cache miss (there is no instruction or data in the cache), the cache simulation unit (instruction unit) 21B requests a cycle-by-cycle simulation process from the cache simulation unit (cycle unit) 22A. At the same time, the cache simulation unit (instruction unit) 21B notifies the resource management unit 23 that the available time of the resource is unknown as a result of the cache access.

  The cache simulation unit (cycle unit) 22A accepts a simulation request from the cache simulation unit (instruction unit) 21B, performs a cache replacement operation (data transfer from an external memory to the cache), and performs a bus / memory simulation unit 22B. An access request is issued.

  The bus / memory simulation unit 22B is connected to the cache simulation unit (cycle unit) 22A through an interface that reproduces a signal line, receives a memory access request from the cache simulation unit (cycle unit) 22A, and has an appropriate latency. And the result is returned to the cache simulation unit (cycle unit) 22A. The cache simulation unit (cycle unit) 22A notifies the resource management unit 23 of this result.

  The resource management unit 23 receives the results notified from the instruction execution simulation unit 21A, the cache simulation unit (instruction unit) 21B, and the cache simulation unit (cycle unit) 22A, and stores them in the internal resource management table.

  FIG. 10 is a flowchart showing the operation in the first embodiment. The left side shows the operation of the instruction level simulation unit 21, and the right side shows the operation of the logic level simulation unit 22.

  In the instruction level simulation 200, in step 201, the instruction level simulation unit 21 receives a simulation start request from the scheduler 24, and obtains an instruction to be processed from the resource management unit 23 accordingly.

  In step 202, the instruction level simulation unit 21 inquires the resource management unit 23 about the resource used by the obtained instruction, and waits until the resource becomes available. In the case of accurately simulating a processor having an out-of-order instruction issue mechanism, the instruction level simulation unit 21 receives instructions from the resource management unit 23 that resources can be used. If there is no instruction that can use the resource, the resource management unit 23 may wait and perform steps 201 and 202 simultaneously.

  In step 202, the instruction level simulation unit 21 waits if the resource used by the instruction to be simulated is not available at that time, but continues the process if the resource is available.

  In step 203, the instruction level simulation unit 21 interprets the instruction and simulates instruction execution including cache access.

  In step 204, the instruction level simulation unit 21 determines whether latency calculation is possible, for example, when the simulation target instruction is an operation instruction having a fixed value latency or a load instruction causing a cache hit. If possible, the control of the instruction level simulation unit 21 proceeds to Step 205. If the latency calculation is impossible, such as a load instruction that causes a cache miss, the control of the instruction level simulation unit 21 proceeds to step 206.

  In step 205, the instruction level simulation unit 21 calculates a time at which resources related to the result of the simulation target instruction can be used, and proceeds to step 208.

  In step 206, the instruction level simulation unit 21 requests the logic level simulation unit 22 to simulate an instruction whose latency cannot be calculated. At this time, the instruction level simulation unit 21 notifies information necessary for the simulation in the logic level simulation unit 22 together. The simulation request notification method includes a method of directly reporting to the logic level simulation unit 22, a method performed via the scheduler 24, and a method of using an entry of processor internal resources in the resource management table of the resource management unit 23. As a result, a part of the simulation is transferred to the logic level simulation 300, but the instruction level simulation is continued as it is, and the process proceeds to Step 207.

  In step 207, the instruction level simulation unit 21 sets the time when the resource related to the result of the simulation target instruction can be used as unknown, and proceeds to step 208.

  In step 208, the time at which the resource becomes usable is stored in the write destination entry (the result storage location of the command) of the resource management table of the resource management unit 23. Therefore, when the process proceeds from step 205 to step 208, the time when the resource becomes available is stored, and when the process proceeds from step 207 to step 208, the time when the resource becomes available is unknown.

  After step 208, the process returns to step 201 and the above steps are repeated.

  In the logic level simulation 300, in step 301, the logic level simulation unit 22 checks whether a simulation request from the instruction level simulation unit 21 remains. If there is a simulation request, the logic level simulation unit 22 waits for a simulation request from the instruction level simulation unit 21. If there is a simulation request, the control of the logic level simulation unit 22 proceeds to step 302.

  In step 302, the logic level simulation unit 22 performs cycle unit simulation for one cycle, and proceeds to step 303.

  In step 303, the logic level simulation unit 22 determines whether the requested simulation process is completed. If not completed, the process returns to step 301. If completed, the process proceeds to step 304. If not completed, step 302 is repeated through step 301, and the requested simulation process is completed.

  In step 304, the logic level simulation unit 22 sets the time at which the resource related to the result of the simulation target instruction obtained as a result of the simulation becomes usable, as the write destination entry (the instruction of the instruction) of the resource management unit 23. The result is stored in (result storage location), and the process proceeds to step 301. Thereafter, if the simulation request remains, steps 301 to 304 are repeated, and if not, the process waits at step 301.

  By writing the time in the resource management table, a part of the simulation is transferred from the logic level simulation 300 to the instruction level simulation 200 again. Thereby, when the control of the instruction level simulation unit 21 is waiting in step 202, the waiting is canceled and the control proceeds.

  In the above operation, when there is a resource request access from the instruction level simulation unit 21, the resource management unit 23 uses the resource at that time based on the available time of the resource requested by the instruction level simulation unit 21. Determine whether it is possible and return the result. When there is a result storage access from the instruction level simulation unit 21, the resource management unit 23 stores the notified result and updates the resource management table. Similarly, when there is a result storage access from the logic level simulation unit 22, the resource management unit 23 stores the notified result and updates the resource management table. If the resource management unit 23 has updated the resource management table, the resource management unit 23 notifies the scheduler 24 accordingly.

  The scheduler 24 cancels the waiting of the instruction level simulation unit 21 when the logic level simulation unit 22 is notified of the time when the resource that is waiting because the instruction level simulation unit 21 is unavailable cannot be used. To do. Furthermore, the scheduler 24 cancels the waiting of the logic level simulation unit 22 when the instruction level simulation unit 21 makes a simulation request to the logic level simulation unit 22.

  FIG. 11 is a time chart of a simulation operation example in the first embodiment. FIG. 11A illustrates a case where a general logic level simulation is performed for comparison, and FIG. 11B illustrates a simulation according to the first embodiment. The case is shown. In FIG. 11, IF is instruction fetch, ID is instruction decode, EX is instruction execution, DC is data cache access, WB is write back, mem is memory access, and wait is resource use. Waiting until it becomes possible (waiting for results) is shown.

  As shown in FIG. 11A, each instruction is pipeline processed. For example, for each instruction, IF, ID, EX, DC, and WB are continuously executed in five cycles. At cycle 0, the pipeline IF fetches instruction 1. In cycle 2, the pipeline IF fetches instruction 2 and the ID decodes instruction 1. In cycle 2, the pipeline IF fetches instruction 3, ID decodes instruction 2, and EX executes instruction 1. In cycle 3, pipeline IF fetches instruction 4, ID decodes instruction 3, EX executes instruction 2, and DC performs instruction 1 data cache access. In cycle 4, the pipeline IF fetches instruction 5, ID decodes instruction 4, EX executes instruction 3, DC performs data cache access of instruction 2, and WB writes instruction 1. Perform the return.

  Here, instruction 2 is a load instruction with memory access, and instruction 5 uses the result of instruction 2. Therefore, in cycle 5, the pipeline ID decodes instruction 5, EX executes instruction 4, and DC performs data cache access of instruction 3, but for instruction 2, memory access mem is performed. Further, in cycle 6, the pipeline DC performs data cache access of instruction 4, and WB writes back the result of instruction 3. However, for the instruction 2, the state of the memory access mem is continued, and the instruction 5 that requires the result of the instruction 2 cannot be executed, so that the instruction 2 enters a standby state. Further, in cycle 7, the pipeline WB writes back the result of the instruction 4, but the instruction 2 has a memory access mem state and the instruction 5 has a standby state. This state continues until cycle 34 when the memory access of instruction 2 is completed and data is obtained from the memory. Then, in cycle 35, the pipeline WB writes back the result of the memory access of the instruction 2, and the EX executes the instruction 5 using the result. Thereafter, in cycle 36, the pipeline DC performs data cache access of instruction 5, and in cycle 37, the pipeline WB writes back the result of instruction 5.

  Here, one cycle of operations such as IF, ID, mem, and wait is defined as one unit. As shown in FIG. 11A, when 30 cycles are required for main memory access, the processing time in FIG. In conventional general logic level simulations, since these unit operations are simulated, the amount of calculation is 107 units.

  Further, according to a general instruction level simulation, a predetermined latency is used for fetch, decode execution, and write-back, and an interlock other than memory access is considered, and a memory access time is assumed to be a predetermined value, for example, 30 cycles. To calculate the processing time. Since the memory access time varies depending on the situation, an accurate processing time cannot be calculated.

  Next, the simulation operation in the first embodiment will be described with reference to FIG. In cycle 0, the scheduler 24 requests the instruction execution simulation unit 21A to start simulation. When the instruction execution simulation unit 21A receives the request, the instruction execution simulation unit 21A executes the instruction 1 obtained through the resource management unit 23 in cycle 0, adds the latency of 4 cycles to the result, and stores the result in the resource management unit 23.

  In cycle 1, the instruction execution simulation unit 21 </ b> A executes instruction 2. In this case, since the instruction 2 is a load instruction, the instruction execution simulation unit 21A requests a cache access from the cache simulation unit (instruction unit) 21B. The cache simulation unit (instruction unit) 21B simulates the cache operation and detects a cache miss in this example. The cache simulation unit (instruction unit) 21B adds a latency of 3 cycles required for cache access, and requests a cache replacement operation from the cache simulation unit (cycle unit) 22A. Further, the cache simulation unit (instruction unit) 21B notifies the resource management unit 23 that the usable time of the write destination of the result of the instruction 2 is unknown.

  In cycle 2, the instruction execution simulation unit 21 </ b> A executes the instruction 3, adds a 4-cycle latency to the result, and stores the result in the resource management unit 23.

  Similarly, in cycle 3, the instruction execution simulation unit 21 </ b> A executes the instruction 4, adds the latency of 4 cycles to the result, and stores it in the resource management unit 23.

  In cycle 4, the instruction execution simulation unit 21 </ b> A executes the instruction 5. In this case, since the instruction 5 depends on the result of the instruction 2 in this example, the instruction execution simulation unit 21A waits for the result at the timing when the resource management unit 23 requests the resource.

  From cycle 5, the cache simulation unit (cycle unit) 22A starts processing the request received from the cache simulation unit (instruction unit) 21B, and performs simulation until cycle 34. Since the result of the instruction 2 is notified to the resource management unit 23 in the cycle 35, the scheduler 24 requests the instruction execution simulation unit 21A to resume the simulation, and the instruction 5 is executed.

  As described above, in the first embodiment, since the instruction whose latency can be calculated by the instruction level simulation is performed by the instruction level simulation, the calculation time can be shortened. In the first embodiment, since the instruction whose latency cannot be calculated by the instruction level simulation is performed by the logic level simulation, high accuracy is maintained. In the first embodiment, the calculation amount is 37 units, and the simulation time can be reduced to 35% compared to the case of FIG.

  Next, changes in values in the resource management table of the resource management unit 23 when the simulation operation in the first embodiment of FIG. 11B is performed will be described in detail with reference to FIGS. 12 to 18. To do. The first resource management table 31 of the resource management table stores instructions 1 to 5 to be executed.

  FIG. 12 to FIG. 17 show the pipeline simulation state and the state of the first resource management table 31 and the second resource management table 32 of the resource management table at time points 1 to 6.

  At time 0, the available times of each resource in the second resource management table 32 are all 0, and nothing is in the pipeline. At time 0, instruction 1 is fetched.

  As shown in FIG. 12, at time 0 to 1, the IF in the first stage of the pipeline is in a state where the instruction 1 is fetched. The instruction 1 is an addition instruction that adds the values of the register R0 and the register R1 and stores the result in the register R2. Since the time required to execute the instruction 1 is 1, the sum 2 with the time 1 becomes the usable time of the instruction 1. At time 1, the pipeline is in a state where the IF has fetched the instruction 1, and is not in the stage where the instruction is executed. Therefore, the usable time of each resource in the second resource management table 32 at this time is all 0. It is. At time 1, instruction 2 is fetched.

  As shown in FIG. 13, at time 1 to 2, the IF of the pipeline fetches the instruction 2. The instruction 2 is a load instruction that accesses the memory using the sum of the value of the register R2 and the value of the register R3 as an address, reads the data at the address from the memory, and stores it in the register R4. That is, instruction 2 is an instruction that requires memory access. Since the time required to execute the instruction 2 itself is 1, the sum 3 with the time 2 at that time becomes the usable time. In actual operation, at time 1-2, the second stage ID of the pipeline is in the state where instruction 1 is decoded and the first stage IF is fetching instruction 2, and the instruction is not executed. The usable time of each resource in the second resource management table 32 is 0. At time 2, instruction 3 is fetched.

  As shown in FIG. 14, at time 2 to 3, the IF of the pipeline fetches the instruction 3. The instruction 3 is an integer addition instruction for adding an integer to the value of the register R3 and storing it again in the register R3. Since the time required to execute the instruction 3 is 1, the sum 4 with the time 3 at that time becomes the usable time. In actual operation, at time 2 to 3, the EX of the pipeline executes the instruction 1, the ID decodes the instruction 2, and the IF fetches the instruction 3. As described above, since the value of the register R2 is changed by the instruction 1, the usable time of the register R2 in the second resource management table 32 is set to 3. At time 3, instruction 4 is fetched.

  As shown in FIG. 15, at time 3 to 4, the pipeline IF fetches the instruction 4. The instruction 4 is a subtraction instruction that subtracts the value of the register R5 from the value of the register R3 and stores the result in the register R0. Since the time required to execute the instruction 4 is 1, the sum 5 with the time 4 at that time becomes the usable time. In actual operation, at time 3-4, the pipeline DC accesses the data cache and a cache hit is found, so the register R2 becomes available and is set to zero. Further, the EX of the pipeline executes the instruction 2. As described above, instruction 2 changes the value of register R4. However, since instruction 2 involves a memory access operation, the time at which the value of register 4 becomes usable is unknown. Therefore, the usable time of the register R4 in the second resource management table 32 is set to unknown (?). At time 4, instruction 5 is fetched.

  As shown in FIG. 16, at time 4 to 5, the pipeline IF fetches the instruction 5. The instruction 5 is a multiplication instruction that multiplies the value of the register R4 by the value of the register R6 and stores the result in the register R7. Since the time required to execute the instruction 5 is 1, the sum 6 with the time 5 at that time becomes the usable time. In actual operation, instruction 3 is executed at times 4-5. As described above, since the instruction 3 changes the value of the register R3, the usable time of the register R3 in the second resource management table 32 is set to 5. An unknown state is maintained for the usable time of the register R4. At time 5, instruction 6 is fetched.

  As shown in FIG. 17, at time 5-6, although not shown, the IF of the sixth pipeline fetches the instruction 6. The instruction 6 is an addition instruction for adding the value of the register R7 to the value of the register R8 and storing the result in the register R8. Since the time required to execute the instruction 6 is 1, the sum 7 with the time 6 at that time becomes the usable time. At time 6, instruction 4 is executed. As described above, since the instruction 4 changes the value of the register R0, the usable time of the register R0 in the second resource management table 32 is set to 6. The register R3 is set to 0 by the cache hit of the instruction 3, and the usable time of the register R4 is kept in an unknown state.

  Here, EX of the fifth pipeline tries to execute the instruction 5, but as described above, the usable time of the register R4 necessary for executing the instruction 5 is unknown, and the instruction 5 cannot be executed. Therefore, the instruction level simulation unit 21 temporarily stops its operation at this time and enters a standby state.

  The instruction level simulation unit 21 requests the logic level simulation unit 22 to simulate the memory access operation of the instruction 2 because the cache miss is found in the instruction 2 when the pipeline DC performs the cache access. In response to this, the logic level simulation unit 22 executes a memory access operation simulation, calculates the memory access operation time, and notifies the resource management unit 23 of the calculation result. The resource management unit 23 adds the internal latency notified from the instruction level simulation unit 21 and the memory access operation time to calculate the usable time of the register R4, and the usable time of the register R4 in the second resource management table 32 To store.

  FIG. 18 shows a state in which the value of the register R4 of the second resource management table 32 has changed due to the simulation result of the logic level simulation unit 32. The time when the register R4 becomes usable after executing the memory access operation of the instruction 2 is 32, the time of the instruction execution time calculator 33 is set to 32, and the value of the register R4 of the second resource management table 32 is 32. Set to

  As described above, the simulation of the instruction stored in the resource management table 23 is executed, and the processing execution time is calculated.

  FIG. 19 is a diagram illustrating a configuration of the simulation apparatus according to the second embodiment. The processor core 1 that performs the simulation in the second embodiment includes the configuration illustrated in FIG. 1B and includes a plurality of pipelines corresponding to the components. The simulation apparatus according to the second embodiment performs a simulation corresponding to the configuration of the processor core 1 shown in FIG.

  As shown in FIG. 19, in the simulation apparatus of the second embodiment, the instruction level simulation unit 21 includes an instruction fetch simulation unit 21C, an instruction cache simulation unit (instruction unit) 21D, an instruction decode simulation unit 21E, and instruction execution. A simulation unit 21F and a data cache simulation unit (instruction unit) 21G are provided. The logic level simulation unit 22 includes an instruction cache simulation unit (cycle unit) 22C, a bus / memory simulation unit (cycle unit) 22B, and a data cache simulation unit (cycle unit) 22D. The bus / memory simulation unit (cycle unit) 22B simulates a memory image 25 assuming an external memory to be connected. The resource management unit 23 includes a first resource management unit 23A, a second resource management unit 23B, and a third resource management unit 23C.

  The instruction fetch simulation unit 21C simulates an instruction fetch operation. The instruction cache simulation unit (instruction unit) 21D simulates an instruction cache access operation. The instruction decode simulation unit 21E simulates an instruction decode operation. The instruction execution simulation unit 21F simulates an instruction execution operation. The data cache simulation unit (instruction unit) 21G simulates the data cache access operation.

  The instruction cache simulation unit (cycle unit) 22C performs a simulation of the instruction cache replacement operation. The data cache simulation unit (cycle unit) 22D performs a simulation of the data cache replacement operation. The bus / memory simulation unit (cycle unit) 22B performs a simulation of memory access requests from the instruction cache simulation unit (cycle unit) 22C and the data cache simulation unit (cycle unit) 22D.

  The first resource management unit 23A manages resources related to the instruction buffer related to processing between instruction fetch and instruction decode. The second resource management unit 23B manages resources related to pipeline registers related to processing between instruction decoding and instruction execution. The third resource management unit 23C manages resources related to registers, arithmetic units, ports, and the like.

  The scheduler (transfer control) 24 requests each part of FIG. 19 to start and restart the simulation.

  FIG. 20 is a time chart of a simulation operation example in the second embodiment. FIG. 20A shows a case in which a general logic level simulation is performed for comparison, and FIG. 20B shows a simulation in the second embodiment. The case is shown. In this operation example, the processing unit is different for each process. For example, fetching is performed in units of four instructions, decoding is performed in units of instructions that can be executed simultaneously, and execution is performed in units of instructions. Decoding is performed in two cycles, and the number of cycles varies depending on the instruction.

  As shown in FIG. 20A, in cycle 0, four instructions 1 to 4 are fetched in the first stage of the fetch pipeline. In cycle 1, 4 instructions 1 to 4 are shifted to the second stage of the fetch pipeline, and 4 instructions 5 to 8 are fetched to the first stage of the fetch pipeline. In cycle 2, 4 instructions 1-4 are shifted to the third stage of the fetch pipeline, and 4 instructions 5-8 are shifted to the second stage of the fetch pipeline.

  In cycle 3, instructions 1 to 3 are decoded simultaneously, and 4 instructions 5 to 8 are shifted to the third stage of the fetch pipeline. In cycle 4, instructions 1 to 3 are further decoded and instructions 4 to 6 are decoded. In cycle 5, instructions 1 to 3 are executed, instructions 4 to 6 are further decoded, and instruction 7 is also decoded. In cycle 6, the results of instructions 1 and 3 are written back, execution of instruction 2 continues, instructions 4-6 are executed, instruction 7 is further decoded, and instruction 8 is also decoded. Therefore, the processing of instructions 1 and 3 is finished.

  In cycle 7, execution of instruction 2 continues, the results of instructions 4 and 5 are written back, execution of instruction 6 continues, and instruction 8 is also decoded. Here, since the instruction 7 uses the result of the instruction 2, an interlock occurs.

  In cycle 8, the result of instruction 2 is written back and execution of instruction 7 resumes. Instruction 6 is an instruction with memory access, and instruction 8 uses the result of instruction 6. In a general logic level simulation, the memory access operation of the instruction 6 is simulated after the cycle 8 and the simulation is performed until a memory access result is obtained.

  In cycle 11, the result of instruction 7 is written back. At this time, the instruction 6 is simulating the memory access operation, and the instruction 8 waits for the result of the instruction 6.

  In cycle N, the memory access operation time of instruction 6 is obtained. In cycle N + 1, instruction 8 is executed and the result of instruction 6 is written back. Execution of instruction 8 continues until cycle N + 3, and the result of instruction 8 is written back at cycle N + 3. In the above simulation, the simulation unit amount is 107.

  Further, according to a general instruction level simulation, a predetermined latency is used for fetch, decode execution, and write-back, and an interlock other than memory access is considered, and a memory access time is assumed to be a predetermined value, for example, 30 cycles. To calculate the processing time. Since the memory access time varies depending on the situation, an accurate processing time cannot be calculated.

  On the other hand, in the second embodiment, as shown in FIG. 20B, for the operation whose latency can be calculated by the instruction level simulation, the instruction level simulation is performed. In FIG. 20B, an operation that can calculate the latency by the instruction level simulation is indicated by a solid line arrow. For the operation P such as memory access in which the latency cannot be calculated by the instruction level simulation, the logic level simulation calculates the operation time. The operation indicated by the white arrow in FIG. 20B performs an instruction level simulation, but requires the result of the logic level simulation. Calculate the exact processing time.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

21 Instruction level simulation unit 22 Logic level simulation unit 23 Resource management unit (resource management table)
24 Control unit (scheduler)

Claims (10)

A simulation apparatus for a system including a processor,
An instruction level simulation unit that performs simulation in units of instructions for operations that can calculate latency by simulation in units of instructions,
A logic level simulation unit that executes a simulation in a cycle unit that reproduces the hardware of the system for an operation in which a latency cannot be calculated by a simulation in an instruction unit,
A resource management unit comprising a resource management table for storing time information when resources used in the simulation are available,
The instruction level simulation unit requests the logic level simulation unit to execute a simulation in a cycle unit in the case of an operation in which a latency cannot be calculated by a simulation in an instruction unit.
The logic level simulation unit notifies the resource management unit of time information at which resources used in the simulation can be used, based on a simulation result in a requested cycle unit,
The said resource management part stores the time information when the resource used by simulation becomes usable, The simulation apparatus characterized by the above-mentioned.   The instruction level simulation unit notifies the resource management unit that the time at which a resource used in the simulation becomes available is unknown in an operation in which latency cannot be calculated by simulation in units of instructions. 1. The simulation apparatus according to 1. The instruction level simulation unit
The simulation in the instruction unit is continued until the subsequent instruction that requires the latency of the operation in which the latency cannot be calculated after the operation in which the latency cannot be calculated by the simulation in the instruction unit is detected.
The simulation in units of instructions is stopped when a subsequent instruction that requires the latency of the operation that cannot calculate the latency is detected,
The simulation according to claim 2, wherein when the resource management unit stores time information at which a resource required by the subsequent instruction becomes available, the simulation is resumed in units of instructions and the stored time information is used. apparatus. The simulation apparatus according to claim 3 , wherein when the execution of the simulation in the requested cycle unit ends, the logic level simulation unit stops the operation when there is no unprocessed request remaining. The simulation apparatus according to claim 4 , further comprising a scheduler that issues a process execution request only to the instruction level simulation unit and the logic level simulation unit in which a simulation processing request exists. The simulation apparatus includes a plurality of the instruction level simulation units, a plurality of the logic level simulation units, and a plurality of the resource management units,
The resource management unit managing resources required by the subsequent instruction is the instruction level other than the instruction level simulation unit waiting for the resource required by the subsequent instruction to be usable. When the time information at which the resource can be used is notified from the simulation unit or the plurality of logic level simulation units, the time information at which the resource can be used is stored,
The scheduler makes a process resumption request to the instruction level simulation unit waiting for the resource required by the succeeding instruction to become available, triggered by the update of time information when the resource becomes available. Item 6. The simulation device according to Item 5. A method for simulating a system comprising a processor,
For operations that can calculate latency by simulation in instruction unit, execute simulation in instruction unit,
In the case of an operation in which the latency cannot be calculated by simulation in units of instructions, a simulation in units of cycles that reproduces the hardware of the system is executed,
A simulation method comprising: storing time information at which a resource related to a latency of an operation incapable of calculating the latency can be used based on a simulation result in cycle units. After an operation in which latency cannot be calculated by simulation in units of instructions, simulation in units of instructions is continued until a subsequent instruction that requires the latency of operations in which the latency cannot be calculated is detected.
The simulation in units of instructions is stopped when a subsequent instruction that requires the latency of the operation that cannot calculate the latency is detected,
8. The simulation according to claim 7, wherein when the time information at which the resource related to the latency of the operation incapable of calculating the latency can be used is stored, simulation in units of instructions is resumed and the stored time information is used. Simulation method. A simulation program for causing a computer to execute a simulation of a system including a processor,
For operations that can calculate latency by simulation in instruction unit, execute simulation in instruction unit,
In the case of an operation in which the latency cannot be calculated by simulation in units of instructions, a simulation in units of cycles that reproduces the hardware of the system is executed,
A simulation program for controlling to store time information at which resources related to the latency of an operation whose latency cannot be calculated are stored based on a simulation result in cycle units. After an operation in which latency cannot be calculated by simulation in units of instructions, simulation in units of instructions is continued until a subsequent instruction that requires the latency of operations in which the latency cannot be calculated is detected.
The simulation in units of instructions is stopped when a subsequent instruction that requires the latency of the operation that cannot calculate the latency is detected,
The control is performed such that when the time information at which the resource related to the latency of the operation incapable of calculating the latency can be used is stored, the simulation in units of instructions is resumed and the stored time information is used. 9. The simulation program according to 9.

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