JP2000011022A - Method for verifying cooperation between hardware and software - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hardware/software cooperation verifying method capable of executing quick and accurate simulation in the simulation of the whole system in which a software program code and hardware can interact with each other. SOLUTION: The system is provided with plural processor simulation models 103 for simulating software instruction operation, a logical circuit simulation model 105 for simulating a logical circuit part, a model switching means 102 for dynamically switching plural processor simulation models 103, and a synchronizing means 104 for synchronizing the simulation of the processor simulation models 103 with that of the logical circuit simulation model 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor for processing a software program code and a software board for executing a software program code on a printed circuit board or a semiconductor integrated circuit including a logic circuit other than the processor controlled by the processor. The present invention relates to a hardware / software co-verification method for quickly and accurately simulating an interaction between a processor unit and a logic circuit unit other than the processor unit.

[0002]

2. Description of the Related Art Conventionally, as a method of verifying an operation in which a software section and a hardware program interact with a processor section and hardware controlled by the processor section, a method of verifying an operation on a printed circuit board after manufacturing an actual chip is known. This has been done by the created evaluation board.

[0003] As another verification method, a processor and a logic unit including a logic circuit are all verified using a simulation model in which a logic simulator on a computer performs the same operation as an actual chip in a clock cycle (hereinafter, cycle accurate). (Japanese Patent Application Laid-Open No. 7-282093). As another method, there is disclosed a method of dynamically switching a processor simulation model to improve a simulation speed at the time of developing the processor itself (Japanese Patent Laid-Open No. 9-2312).
No. 55).

As another verification method, a processor section is simulated by an instruction level simulator for high-speed simulation, and a logic circuit section is simulated by a cycle-accurate simulation model.
There are ways to synchronize these simulations. As another verification method, there is disclosed a method of performing a simulation by using a hardware device that emulates a processor unit and synchronizing the hardware device with a logic simulator of a logic circuit unit (Japanese Patent Laid-Open No. 9-29300).
No. 2).

Further, in the conventional instruction array system, a method of optimizing a software program code to be minimized and an optimization of a code executed at high speed on an actual processor chip are performed. Development of the compiler of the method has been performed.

[0006]

[0005] Verification using an evaluation board requires the production of an actual chip and the manufacture of an evaluation board, and the number of items to be developed before verification is increased. In the current situation where the processor section and the logic circuit section are being integrated on a semiconductor integrated circuit,
Even if an evaluation board is created, it is not easy to perform verification in a semiconductor integrated circuit.

Further, in a method of verifying by using a simulation model that performs the same operation as an actual chip in a clock cycle by a logic simulation of a processor unit and a logic circuit unit on a computer, the same operation as that of an actual chip is performed in a clock cycle. Since a cycle-accurate simulation model is used, the execution speed is slow, and it is difficult to simulate a large-scale software program code in a realistic simulation time.

Further, in the method of dynamically switching the simulation of the processor unit, the interaction with the logic circuit unit other than the processor unit cannot be simulated, and the instruction executed at a specific simulation time cannot be simulated. In addition, since the simulation model is switched according to the instruction value and the signal value, it is not possible to cope with the switching depending on the instruction sequence.

In a simulation method for simulating a processor unit with an instruction level simulator and synchronizing with a logic circuit simulation model to verify the interaction between software and hardware of the entire system, the processor unit is an instruction level simulator. However, in order to synchronize the processor simulation model and the logic circuit simulation model each time the instruction is completed, a difference in the clock cycle between the logic circuit unit and the processor unit occurs due to branching, exception processing, and the like. There's a problem.

In the method of simulating the processor section with a hardware emulator and simulating the logic circuit section with a logic simulator, an emulator for the processor section is required. However, the emulation apparatus is generally expensive and practical. is not. In addition, under the current situation in which a processor unit and a logic circuit unit are integrated on a single semiconductor integrated circuit due to the advancement of semiconductor technology, simulations are virtually performed on a computer instead of using physical emulation means. Therefore, a method capable of performing a high-speed and high-accuracy simulation is desired.

In addition to a method of simulating the entire system including a virtual processor unit and a logic circuit unit, optimization of software program codes for high-speed and high-accuracy simulation of hardware / software co-verification will be developed in the future of semiconductor development. Is needed. The present invention has been made in view of the above points, and has as its object to simulate software and hardware in a simulation of an entire system including a processor unit and a logic circuit unit, in which software program codes and hardware interact with each other. Provided is a hardware / software co-verification method capable of performing high-speed and high-accuracy simulation by dynamically switching a simulation model of a processor unit in instruction sequence dependence, branching, and exception processing of the processor unit that causes a synchronization error. Things.

Further, by having a compiler having an instruction arrangement method optimized for simulating the entire system at high speed and with high accuracy, it is possible to shorten a system verification period and a system development period. It provides a hardware / software co-verification method that can be performed.

[0013]

In order to achieve the above object, a simulation method for simulating the entire system by synchronizing a processor simulation model and a logic circuit model is provided. By providing a circuit model and dynamically switching processor simulation models during simulation execution,
The simulation of the entire system is performed at high speed and with high accuracy, including branching of the interaction between the processor unit and the logic circuit unit, exception processing, and the like.

A hardware / software co-verification method according to a first aspect is a hardware / software co-verification method in a method of simulating the operation of a circuit to be verified including a processor unit and a logic circuit unit. Processor simulation model for simulating, on a computer, an instruction operation of software for controlling a computer, a logic circuit simulation model for simulating a logic circuit section on a computer, and model switching means for dynamically switching between the plurality of processor simulation models And a synchronizing means for synchronizing the simulation of the processor simulation model selected by the model switching means and the simulation of the logic circuit simulation model, and the instruction operation of software of the processor unit interacting with each other. It is characterized in that to verify the operation of the logic circuit portion.

According to the hardware / software co-verification method of the first aspect of the present invention, the software / program code executed by the processor unit and the logic circuit unit interact with each other. Includes multiple processor simulation models and logic circuit simulation models for the simulation of the target circuit to be verified, and dynamically switches processor simulation models during simulation to improve simulation accuracy without reducing simulation speed Can be done.

According to a second aspect of the present invention, there is provided a hardware / software co-verification method according to the first aspect, further comprising: a simulation model determining unit for determining a processor simulation model to be selected according to an instruction sequence of a software program code; Is to dynamically switch the processor simulation model based on information from the simulation model determining means.

According to the hardware / software co-verification method of the present invention, the dependence is checked according to the instruction sequence of the software program code executed by the processor unit, and the processor simulation model to be selected is determined. In addition, by performing the cooperative simulation while dynamically switching the determined simulation model, it is possible to prevent deterioration of the simulation accuracy depending on the processor simulation model and the instruction sequence.

According to a third aspect of the present invention, there is provided a hardware / software co-verification method according to the first aspect, wherein synchronization processing means for advancing the simulation time of the logic circuit simulation model ahead of the simulation time of the processor simulation model; And an exception occurrence detecting means for detecting an exception processing signal input to the processor simulation model from outside the circuit to be verified, and the model switching means dynamically switches the processor simulation model based on information of the exception occurrence detecting means. .

According to the hardware / software co-verification method of the third aspect, in addition to the same effects as those of the first aspect, in the synchronization processing of the processor simulation model and the logic circuit unit, the logic circuit unit is simulated by the processor simulation model. Advance ahead of time,
By detecting exception processing such as interrupts transmitted from the logic circuit section to the processor simulation model, and dynamically switching the processor simulation model according to the occurrence of the exception processing, the interaction between the processor section and the logic circuit section can be performed. In addition, it is possible to prevent the simulation accuracy from deteriorating due to exceptionally occurring processing.

According to a fourth aspect of the present invention, there is provided a hardware / software co-verification method, which is optimized to simulate a processor simulation model at high speed, and is optimized to maintain high accuracy of co-verification with a logic circuit simulation model. In order to change the order of instructions. Claim 4
According to the described hardware / software co-verification method, by generating the software program code of the program instruction arrangement method, the instruction arrangement method of the software program code is not performed by optimizing the code amount or the speed. Optimizes hardware / software co-verification, which is performed before the actual production of hardware, for high accuracy and high speed, thus shortening the verification time of the interaction between hardware and software. it can.

According to a fifth aspect of the present invention, there is provided a hardware / software co-verification method according to the fourth aspect, further comprising a compiler having a function of determining an instruction array in a program instruction array system. According to the hardware / software co-verification method of the fifth aspect, in addition to the same effects as those of the fourth aspect, a high-level language that is actually described by a compiler that generates a software program code by a program instruction arrangement method is used. In addition, a huge amount of system verification can be shortened, and a system development period can be shortened.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 8 show a first embodiment corresponding to claims 1 and 2 of the present invention.
This will be described with reference to FIG.

FIG. 1 is a schematic conceptual diagram of the hardware / software co-verification of the first embodiment. In FIG. 1, reference numeral 101 denotes a processor simulation model 10.
3 is a software program code to be input.
Reference numeral 102 denotes a sequence dependence detection unit which is a simulation model determination unit that checks the dependence of the instruction sequence of the software program code 101 and determines a processor simulation model to be simulated. Reference numeral 103 denotes a processor simulation model for simulating, on a computer, instruction operations of software for controlling the processor unit. FIG. 1 includes two processor simulation models. An instruction level simulation model 111 simulates processing of each instruction of the processor unit. This instruction level simulation model 11
In the case of 1, the simulation is performed for each input instruction without considering the clock supplied to the processor on the actual chip. A cycle accurate model 113 simulates an operation for each clock supplied to the processor. In the model 113, in a processor in which a pipeline is realized, the pipeline operation can be simulated. Reference numeral 112 denotes a register (storage means) for storing register data inside the processor. The register 112 stores the cycle accurate model 11 from the instruction level simulation model 111.
3 is also accessed. The register 112 stores the instruction level simulation model 111 and the cycle accurate model 113 at the same simulation time.
Are not written simultaneously. Reference numeral 104 denotes an instruction level simulation model 111 and a logic circuit simulation model 1 for simulating a logic circuit unit on a computer.
Synchronization means for synchronizing 05. In FIG. 1, the simulation model of the logic circuit unit is a cycle accurate model that performs the same operation as an actual chip with respect to a clock supplied to the logic circuit unit. The synchronization unit 104 can synchronize the simulation time of the instruction level simulation model 111 with the simulation time of the logic circuit model 105 even when there is a difference between the period of the clock input to the processor unit and the period of the clock input to the logic circuit unit.

A software program code 101 is input, and a sequence dependence detecting means 102 for detecting a dependence of an instruction sequence from a plurality of models in a processor simulation model 103 dynamically switches during the execution of a simulation. Model 10
Synchronization 1 with synchronization and branch processing corresponding to 5
04.

FIG. 2 is a simulation processing flow of the processor simulation model and the logic circuit simulation model of the first embodiment. 201 is a processing flow of the processor simulation model,
02 is a processing flow of the logic circuit simulation model. The processing of 201 and 202 is executed concurrently. 211 is a processor simulation model initialization process, and 212 is a software program code reading process executed by the processor simulation model. Reference numeral 213 denotes a sequence dependence detection process for detecting dependence of an instruction to be simulated.

In this process, a processor simulation model is selected. Reference numeral 214 denotes synchronous clock number determination processing for determining the number of clock cycles for operating the logic circuit simulation model for each selected processor simulation model. A processor simulation process 215 simulates an instruction operation in the software program code by a processor simulation model. An instruction end determination process 216 determines whether the software program code has ended.

Reference numeral 221 denotes a logic circuit model initialization process, and reference numeral 222 denotes a test vector input process to be input to a circuit to be verified from other than the processor unit. Reference numeral 223 denotes a simulation process using a logic circuit simulation model. In the first embodiment, this processing is processing for one clock. 203 is means for storing shared data for exchanging data between the processor simulation model and the logic circuit simulation model.
Reference numeral 224 denotes a clock cycle determination process for determining the number of clocks for simulating the logic circuit simulation model based on the 214 cycle data, and reference numeral 225 denotes a clock control process for advancing the simulated clock cycle by one. Reference numeral 204 denotes an end synchronization signal for terminating the simulation of the logic circuit simulation model based on the synchronization signal from the instruction end determination processing in 216.

FIG. 3 is a diagram showing the flow in the processor simulation process of 215 in FIG. 2 in more detail. Reference numeral 301 denotes a model activation process for executing a simulation model using the processor simulation model selected in the series dependence detection process in 213. By the model starting process of 301, the simulation process of the instruction level model of 302 and the simulation process of the cycle accurate model of 303 are executed.

Table 1 is an example of a simulated processor instruction set.

[0030]

[Table 1]

The instruction LD is a data transfer instruction for transferring data from data in a memory area specified by an address to a register A, a register B, or a register C.
Instruction ST is a data transfer instruction for transferring data from register A, register B, or register C to a memory area specified by an address. The instruction MOV is an arithmetic operation instruction that substitutes a register A, a register B, a register C, or a constant value specified by a source into a register A, a register B, or a register C specified by a destination. Instruction ADD adds register A, register B, register C, or a constant value specified by the source to register A, register B, or register C specified by the destination, and stores the result in the register specified by the destination. Arithmetic operation instruction to be assigned. The instruction SUB subtracts a register A, a register B, a register C, or a constant value specified by a source from a register A, a register B, or a register C, specified by a destination, and assigns the result to the register specified by the destination. Arithmetic operation instruction. The instruction MUL multiplies register A, register B, register C, or a constant value specified by the source with register A, register B, or register C specified by the destination, and assigns the result to the register specified by the destination. Arithmetic operation instruction. Instruction CMP is a register A or register B or register C specified by the source or a constant value and a register A or register B specified by the destination
Alternatively, the instruction is a comparison instruction for comparing the register C and setting the comparison result flag if they are equal, and resetting the comparison result flag if they are not equal. The comparison result flag is stored until the next CMP instruction is executed. The instruction BEQ is a conditional branch instruction that causes the processing to jump to the instruction position specified by the label if the comparison result flag is set. The instruction JMP is an unconditional branch instruction that causes the processing to jump to the instruction position specified by the label. Instruction RET
I is an interrupt processing return instruction for returning the processing from the interrupt processing performed after the input of the interrupt signal to the instruction position processed before the input of the interrupt signal.
The instruction NOP does nothing.

FIG. 4 shows an example of a program to be executed.
In FIG. 4, one column represents one instruction, and is described in the order of label, instruction, destination, and source from the left. 513, 514, 515, 516, 517,
The instructions 518, 519, 520, and 521 are not labeled. FIG. 7 is a schematic diagram of a circuit to be verified. Reference numeral 801 denotes the entire circuit to be verified, and an input is given to this circuit. A processor core 803 executes the instruction code, and a memory 804 stores the instruction code. A processor unit 805 includes a processor core and an instruction memory. A logic circuit unit 802 interacts with the processor unit.

FIG. 5 shows a state 6 for each cycle and each instruction when the software program code 501 is executed.
Shading (628) indicates pipeline stall due to data hazard and dotted line (61).
8, 619) represent the clearing of the instruction by the branch instruction. 601 is the number of clock cycles. FIG. 6 is a diagram showing instructions simulated by each processor simulation model according to the first embodiment.

FIG. 8 shows an example of a hardware configuration diagram according to the first embodiment. In FIG.
Is a display device for viewing all processed information, 902 is a keyboard for the designer to input all information and processing instructions, 903 is a central processing unit for performing all processing, 904 is a storage device for storing each information It is.

Hereinafter, the hardware / software co-simulation method according to the first embodiment will be specifically described with reference to an example in which the program 501 is executed based on the flowcharts of FIGS. The processor to be simulated has 401 instruction sets,
Address [A0] of the accessible address space,
[A1], [B0], and [B1] are assumed to be assigned to registers of the logic circuit unit. This processor has a pipeline structure including three stages of an instruction fetch / decode stage, an instruction execution / memory access stage, and a write back stage, and performs branch prediction on the assumption that a branch instruction is not taken. If there is a data hazard in pipeline processing, pipeline stall occurs. According to the input vector given to the logic circuit unit and the processing in the logic circuit unit, the registers in the logic circuit unit accessible from the processor unit are stored in the registers allocated to the address space [A0] in clock cycle 2, 3 in clock cycle 10
0 shall be entered. Similarly, it is assumed that [A1] contains 10 in clock cycle 2 and 40 in clock cycle 10.

The processing flow of the processor simulation model 201 and the processing flow of the logic circuit unit 202 are executed in parallel. In the initialization processing of 211 and 221, a processor simulation model and a logic circuit simulation model are initialized. In the program reading process at 212, the software program code simulated by the processor simulation model is read and stored in the storage means, and the instruction position to be simulated is set at 511. In the input vector reading process of 222, the input vector simulated by the logic circuit simulation model is read and stored in the storage means.

In the sequence dependency detection process at 213, first, three instructions of the number of pipeline stages are read. Here, instructions 511, 512, and 513 are read,
Whether the first instruction causes a data hazard,
It is checked whether the read three instructions include a branch instruction or whether the instruction is a branch instruction. 511
Are MOV, not branch instructions,
No data hazard is generated for No. 3. Also, 51
None of 1, 512 and 513 are branch instructions.

In the cycle number determination process at 214, the number of cycles required for the instruction to be simulated is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, since the first instruction has been executed from the initial state, 3 is calculated, and is sent as synchronous data to the clock or cycle number determination processing of 224 in the logic circuit model simulation.

In the model determination activation of 301, the simulation model selected in the series dependence detection processing of 213 is executed for a new instruction. Here, an instruction level simulation model is selected, and the operation of the processor unit is simulated by 302. In the instruction end determination processing of 216, since the instruction of 511 is still being executed, the flow returns to 213 without terminating.

In the processing flow of the logic circuit section executed in parallel, a simulation for one clock cycle is performed by 223, and the number of clock cycles calculated by 214 through 224 and 225 is three. Is executed. The input vector given to the logic circuit unit and the registers assigned to the address space [A0] accessible from the processor unit in the registers in the logic circuit unit by the processing of the logic circuit unit are 20 and [A] in clock cycle 2.
1] contains 10.

In the sequence dependency detection process at 213, a new instruction 514 is read, and 512, 513, 514 are read.
Is checked for sequence dependence. 512 instructions are L
D, no data hazard is generated for 513 and 514. Also, there is no branch instruction. In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 4 is calculated and sent as synchronous data to the clock or cycle number determination processing of the logic circuit simulation model simulation of 224.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here also, the instruction level simulation model is selected, and the operation of the processor unit is simulated by 302. In the instruction end determination processing of 216, since the instruction of 511 is still being executed, the flow returns to 213 without terminating.

In the processing flow of the logic circuit section executed in parallel, the simulation for one clock cycle is performed by 223, and the simulation up to 4 clock cycles calculated by 214 through 224 and 225 is performed by the logic circuit simulation. Performed on the model. Thereafter, the operation is similarly continued until clock cycle 6, which is the execution of instruction 514.

In the sequence dependency detection processing at 213, a new instruction 517 is read, and 515, 516, and 517 are read.
Is checked for sequence dependence. The instruction at 515 is C
MP, which does not cause data hazard for 516 and 517. However, 517 is a branch instruction. 214
In the cycle number determination process, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 7 is calculated, and the clock of the logic circuit simulation model simulation of 224 is sent as synchronous data to the cycle number determination processing.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here, the instruction level simulation model is selected for the 515 CMP instruction, but the cycle-accurate model simulation is also selected for the 517 branch instruction. 303 simulates the operation for the 517 BEQ instruction. In the simulation for the CMP instruction, in the simulation of the logic circuit unit in clock cycle 2, [A0] and [A1] contain 20, 10 respectively, regA and regC have the same value, and the comparison result flag is set. You.

In the instruction end determination processing of 216, the processing is still 515
Since the instruction is being executed, the process returns to 213 without terminating.
In the processing flow of the logic circuit unit executed in parallel, 2
The simulation for one clock cycle is performed by 23, and the simulation up to the number of clock cycles 7 calculated by 214 through 224 and 225 is performed on the logic circuit simulation model.

In the sequence dependence detection processing at 213, a new instruction 518 is read, and 516, 517, and 518 are read.
Is checked for sequence dependence. 516 instructions are N
This is an OP and does not generate a data hazard for 517 and 518. However, 517 is a branch instruction and 518
Is the instruction immediately after the branch instruction. In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 8 is calculated, and the clock of the logic circuit simulation model simulation of 224 is sent as synchronous data to the cycle number determination processing.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here, the instruction level simulation model is selected for the 516 NOP instructions. For the 517 branch instructions, a cycle-accurate model has already been simulated. Since the instruction 518 is also the instruction immediately after the branch instruction, the simulation of the cycle accurate model is performed. N at 516 by 302
The operation for the OP instruction, 303 simulates 518 SUB instructions in parallel with the operation for the 517 BEQ instruction.

In the instruction end determination processing at 216, the processing is still 515
Since the instruction is being executed, the process returns to 213 without terminating.
In the processing flow of the logic circuit unit executed in parallel, 2
The simulation for one clock cycle is performed by 23, and the simulation up to the number of clock cycles 8 calculated by 214 through 224 and 225 is performed on the logic circuit simulation model.

In the sequence dependence detection processing at 213, a new instruction 519 is read, and 517, 518, and 519 are read.
Is checked for sequence dependence. The instruction 517 is a branch instruction, which is already being executed in the cycle accurate model, and the instruction 519 is a second instruction after the branch instruction. In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated.
Here, 9 is calculated, and the simulation clock of the logic circuit simulation model of 224 is sent to the cycle number determination processing 214 as synchronization data.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here, the simulation of a cycle-accurate model has already been performed for 517 BEQ instructions.
Since the instruction 519 is the second instruction after the branch instruction, the cycle accurate model is simulated. Since the comparison result flag is set by 302, a branch occurs. Therefore, in the cycle accurate model, the erasing operation of the instructions 518 and 519 is also simulated.

In the instruction end determination processing of 216, the processing is still 515
Since the instruction is being executed, the process returns to 213 without terminating.
In the processing flow of the logic circuit unit executed in parallel, 2
The simulation for one clock cycle is performed by 23, and the simulation up to the number of clock cycles 9 calculated by 214 through 224 and 225 is executed for the logic circuit simulation model.

In the sequence dependency detection processing at 213, three instructions after branching are read, and 512, 513, and 514 are read.
Is checked for sequence dependence. Reference numeral 512 denotes an instruction branched by the branch instruction 517. 512, 513, 5
No data hazard occurs at 14. In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 12 is calculated and sent as synchronous data to the clock or cycle number determination processing of the logic circuit simulation model simulation of 224.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here, a cycle-accurate model is simulated for 512 LD instructions because they are branched instructions. The instruction end determination processing of 216 is still 515
Since the instruction is being executed, the process returns to 213 without terminating.

In the processing flow of the logic circuit section executed in parallel, the simulation for one clock cycle is performed by 223, and the simulation up to 12 clock cycles calculated by 214 through 224 and 225 is performed by the logic circuit simulation. Performed on the model. In the sequence dependency detection process of 213, a new instruction 51
5, the instruction is read, and the sequence dependency is checked for 513, 514, and 515. 513, 514, 515
Has no data hazard and has no branch instructions.

In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213.
Here, an instruction level model is selected and simulated for 513 LD instructions. Thereafter, similarly, the simulation is executed until the end of the instruction. 519 instructions L
Since there is a data hazard between the instruction ADD of D and the instruction ADD of 520, pipeline stall occurs. Therefore, the instruction 520 is simulated in a cycle-accurate model.

As described above, according to the first embodiment of the present invention, the hardware / software co-verification method according to claim 1 converts a simulation model of a processor unit into an instruction-level model and a cycle-accurate model. By preparing various models and dynamically switching between them, it is possible to simulate the interaction between hardware and software with high accuracy and high speed.

Further, by the hardware / software co-verification method according to the second aspect, the point at which the simulation model of the processor section is switched is dynamically switched according to the sequence dependence of instructions, so that the hardware and software can be switched. The interaction can be simulated with high accuracy and high speed. The first
In the above embodiment, a cycle-accurate model is used for the logic circuit unit. However, a model having a required accuracy is used as the simulation accuracy. For example, when synchronization with the processor unit is performed in units of two cycles, a model for every two cycles is used. It is needless to say that the simulation can be performed by using this.

In the first embodiment, two models, ie, an instruction-level model and a cycle-accurate model, are dynamically switched as simulation models of the processor unit. Needless to say, this is possible. (Second Embodiment) A second embodiment according to claim 3 of the present invention will be described with reference to FIGS.

FIG. 9 is a simulation processing flow of a processor simulation model and a logic circuit simulation model according to the second embodiment. 1001 is a processing flow of a processor simulation model,
1002 is a processing flow of the logic circuit simulation model. The processes of 1001 and 1002 are executed concurrently. Hereinafter, only processing different from the flow of FIG. 2 will be described. Reference numeral 1015 denotes a processor simulation process using a processor simulation model that simulates an operation other than write-back by an instruction operation in the software program code. Reference numeral 1016 denotes a pre-exception simulation process for determining occurrence of an exception process input from a logic circuit simulation. Reference numeral 1017 denotes an exception determination process in which the instruction operation during the simulation is stopped when an exception occurs, and the simulation is transferred to the exception processing software program code. Reference numeral 1018 denotes a processor write-back simulation process for simulating the write-back process of the processor simulation model. Reference numeral 1023 denotes exception occurrence designation processing that defines whether a signal from the logic circuit unit causes an exception to occur in the processor. A unit 1003 stores shared data for exchanging data between the processor simulation model and the logic circuit simulation model. Reference numeral 1025 denotes an exception occurrence communication process for storing a change in the exception signal specified in 1023 and communicating with the processor simulation flow. The processing of 1015 can be shown in more detail in FIG. 3 as in the first embodiment. Here, the synchronous processing means for advancing the simulation time of the logic circuit simulation model ahead of the simulation time of the processor simulation model has been simulated up to just before the write-back processing in the processor operation simulation of 1015. Simultaneously with the processing, the simulation of the logic circuit unit is performed at 223, 224, and 225 up to the number of clocks determined by the synchronous clock number determination processing at 214, so that the logic is executed before the write-back processing at which the instruction operation of the 1018 processor ends. It is configured by advancing the simulation time of the circuit section.

The exception occurrence detecting means for detecting an exception processing signal input from the logic circuit simulation model to the processor simulation model detects a change in the signal of the logic circuit section designated by 1023 in the exception occurrence communication processing of 1025 by the processor. It communicates with the simulation and is configured by the exception processing simulation of the 1016 and 1017 processors according to the information.

The exception occurrence detecting means for detecting an exception processing signal input to the processor simulation model from outside the circuit to be verified is constituted by inputting exception information as an external signal 1016. The model switching means dynamically switches the processor simulation model according to the information of the exception occurrence detecting means. FIG. 10 shows a software program code 11 executed when an interrupt occurs.
01 is an example. In FIG. 10, one column represents one instruction, and the code 1111 describes a label, an instruction, a destination, and a source in order from the left. 11
12 is not labeled.

The hardware configuration according to the second embodiment is the same as that of FIG. 8 for describing the first embodiment. In FIG. 8, reference numeral 901 denotes a display device for viewing all processed information; Reference numeral 902 denotes a keyboard for the designer to input all information and processing instructions;
Is a central processing unit that performs all kinds of processing, and 904 is a storage device that stores each information.

FIG. 11 shows each cycle when the software program codes 501 and 1101 are executed.
The states 1211 to 1226 for each instruction are shown. Shading (1224) indicates pipeline stall due to a data hazard, and dotted lines (1214 and 1215) indicate clearing of an instruction due to a branch instruction. Reference numeral 1201 denotes a clock cycle.

FIG. 12 is a diagram showing instructions simulated by each processor simulation model according to the second embodiment. Hereinafter, the hardware / software co-simulation method according to the second embodiment will be specifically described using a case where the program 501 and the program 1101 are executed based on the flows of FIGS. 9 and 2 as an example. The processor to be simulated has an instruction set of 401, and addresses [A0], [A1], [B0],
[B1] is assumed to be assigned to the register of the logic circuit unit. This processor has a pipeline structure including three stages of an instruction fetch / decode stage, an instruction execution / memory access stage, and a write back stage. For branch instructions, branch prediction is performed on the assumption that no branch is taken. If a data hazard occurs during pipeline processing, pipeline stall occurs. In addition, the input vector given to the logic circuit unit and the registers in the logic circuit unit which are assigned to the address space [A0] accessible from the processor unit by the processing of the logic circuit unit have two cycles in clock cycle 2.
0, 30 in clock cycle 10 Similarly, it is assumed that [A1] contains 10 in clock cycle 2 and 40 in clock cycle 10. Further, it is assumed that an interrupt signal is generated in clock cycle 6 from the logic circuit unit.

The processing flow 1001 of the processor simulation model and the processing flow 1002 of the logic circuit are executed in parallel. In the initialization processing of 211 and 221, a processor simulation model and a logic circuit simulation model are initialized. In the program reading process at 212, the software program code simulated by the processor simulation model is read and stored in the storage means, and the instruction position to be simulated is set at 511. In the input vector reading process of 222, the input vector simulated by the logic circuit simulation model is read and stored in the storage means. At 1023, a signal to be notified to the processor simulation model as occurrence of an exception is specified for a signal in the logic circuit simulation model.

In the sequence dependence detection process at 213, three instructions of the number of pipeline stages are read. Here, instructions 511, 512, and 513 are read, and whether the first instruction causes a data hazard, whether the read three instructions include a branch instruction, or an instruction that has been branched by a branch instruction is determined. Checked. The instruction 511 is an MOV, is not a branch instruction, and does not generate a data hazard for 512 and 513. Also, 511,
None of 512 and 513 is a branch instruction.

In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, since the first instruction has been executed from the initial state, 3 is calculated, and is transmitted as synchronous data to the clock cycle number determination process of 224 in the logic circuit model simulation.

In the model determination processing of 301, a simulation model for simulating an instruction to be newly executed for an instruction being executed in the sequence dependence detection processing in 213 and the cycle accurate model is selected. Here, an instruction level simulation model is selected, and the operation of the processor unit is simulated by 302. In the processing flow of the logic circuit unit executed in parallel, the simulation of one clock cycle is performed by 223, and the simulation of the logic circuit simulation model of 223 is performed by the number of clock cycles 3 calculated by 214 through 224 and 225. Be executed. The registers assigned to the address space [A0] accessible from the processor unit in the registers in the logic circuit unit by the processing of the input vector given to the logic circuit unit and the processing in the logic circuit unit are 20 and [A1] in clock cycle 2. Contains 10. 1025
Then, it is determined whether the signal specified in 1023 has changed and an interrupt signal to the processor simulation model has been generated, and data is sent to an interrupt determination process in 1016. Here, no interrupt has occurred.

In steps 1016 and 1017, since no interruption has occurred, nothing is performed and the write-back simulation of 1018 is performed. In the instruction end determination process of 216, since the instruction of 511 is still being executed, 21
Return to 3. Thereafter, the same operation is performed until the instruction 513 is executed. In the sequence dependency detection process at 213, a new instruction 516 is read, and sequence dependency is checked for 514, 515, and 516. The instruction 514 is ADD, and does not generate a data hazard for 515 and 516. Also, there is no branch instruction.

In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 6 is calculated, and the simulation clock of the logic circuit simulation model of 224 is sent as synchronous data to the cycle number determination processing. In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213. Here also, the instruction level simulation model is selected, and the operation of the processor unit is simulated by 302.

In the processing flow of the logic circuit section executed in parallel, the simulation for one clock cycle is performed by 223, and the number of clock cycles calculated by 214 through 224 and 225 is 223. Is executed. At 1025, it is determined whether the signal designated at 1023 has changed and an interrupt signal to the processor simulation model has been generated. In this logic circuit unit, an interrupt signal is generated in the sixth cycle, so that data is sent to the interrupt determination process of 1016. Since an interrupt has occurred here,
The process returns to step 213 without performing the write back of step 1018 by the exception occurrence determination process of step 1017.

In the sequence dependence detection process at 213, new instructions 1111 and 1112 are read. The reason why only two are read is interrupt processing, and the second instruction is an interrupt return instruction. The sequence dependence is similarly checked for the instruction sequence after the interruption. The interrupt return instruction is a branch instruction, and a cycle-accurate model is selected as a processor simulation model.

In the cycle number determination process at 214, the number of cycles required for the simulated instruction is determined, and the number of cycles required to synchronize with the logic circuit unit is calculated. Here, 9 is calculated, and the clock of the simulation of the logic circuit simulation model of 224 is sent as synchronous data to the cycle number determination processing. In the model determination processing of 301, a simulation model is selected from the series dependence detection processing of 213. Here also, the instruction level simulation model is selected, and the operation of the processor unit is simulated by 302.

In the processing flow of the logic circuit unit executed in parallel, a simulation for one clock cycle is performed by 223, and the number of clock cycles calculated by 214 through 224 and 225 is 223 of the logic circuit simulation model. A simulation is performed. At 1025, it is determined whether the signal designated at 1023 has changed and an interrupt signal to the processor simulation model has been generated. In this logic circuit unit, no interrupt signal is generated in 7 to 9 cycles, so that 1025 sends data indicating that no interrupt has occurred to the interrupt determination processing of 1016. Here, since no interrupt has occurred, the write back of 1018 is executed and the process returns to 213.

Thereafter, the simulation is similarly executed until the end of the instruction. By executing the instruction of 1112, the instruction 514 before the occurrence of the interrupt is executed again. As described above, according to the second embodiment of the present invention,
The hardware / software co-verification method prepares an instruction-level model and a cycle-accurate model for the simulation model of the processor section, and dynamically switches between them to enhance the interaction between hardware and software. Simulation can be performed accurately and at high speed. Further, by adding an interrupt determination process, even during the simulation using the processor simulation model at the instruction level, the simulation can be performed in synchronization with the simulation of the logic circuit unit with high accuracy.

In this example, a cycle-accurate model is used for the logic circuit unit. However, a model having a required accuracy is used as the simulation accuracy. For example, when synchronization with the processor unit is performed in units of two cycles, every two cycles are used. It is needless to say that the simulation can be performed by using the model. In this example, the instruction level and the cycle-accurate model are dynamically switched as a simulation model of the processor unit.
Needless to say, simulation can be performed by adding another model.

(Third Embodiment) Claim 4 of the present invention
A third embodiment corresponding to claim 5 will be described with reference to FIGS. FIG. 13 shows an example of a compiler for hardware / software co-verification according to the third embodiment, which optimizes a processor simulation model for high-speed simulation and improves the accuracy of co-verification with a logic circuit simulation model. It has a program instruction array system for changing the instruction order so as to optimize for maintaining high precision, and has a compiler having a function of determining an instruction array of the program instruction array system.

Reference numeral 1401 denotes an input source code described in the C language. Reference numeral 1402 denotes an intermediate code generation process generated from the source code. In this process, labels are attached to all instructions, and a dependency list expressing instruction dependencies by labels is generated for each instruction. Here, the dependency list is an instruction sequence. In the dependency list of a certain instruction, for the instruction that substitutes the variable referenced by the instruction before the instruction, and for the variable that the instruction substitutes before the instruction, The instruction making reference or assignment is listed. Furthermore, it is the same as the union of the dependency lists of the instructions listed in the dependency list.
1403, an intermediate code including a label, a code, and a dependency list is generated. Reference numeral 1404 denotes an instruction order changing process for changing the order of the instruction sequence from the intermediate code in order to eliminate the dependence on the instruction sequence. 1405 is the label after the change,
Intermediate code including code and dependency list. 140
Reference numeral 6 denotes a dependency elimination process for eliminating a dependency of an instruction causing a data hazard, which cannot be canceled by the order change of 1404, by inserting a NOP instruction. 1
407 is a machine language code.

FIG. 14 is a flow chart of the instruction order changing process in step 1404. Reference numeral 1501 denotes execution unit division processing for dividing a source code for each processing unit. Thereafter, the processing is performed for each of the divided execution units. Reference numeral 1502 denotes an execution unit selection process for selecting an execution unit. The criterion selected here is that processing is performed from a higher-order execution unit. Reference numeral 1503 denotes a dependency list creation process. In step 1504, a process of changing the order of instructions in the execution unit is performed. In step 1504, the instruction order change is repeated until the dependency is minimized.

Table 2 shows an example of C language source code given to the compiler.

[0082]

[Table 2]

Tables 3 and 4 are intermediate codes created from the source code of Table 2 and are described for each execution unit. Table 3 is the whole, and Table 4 is the intermediate code of the execution unit of the while loop, and is labeled L2 in the whole of Table 3.

[0084]

[Table 3]

[0085]

[Table 4]

Table 5 shows that the intermediate code of Table 3
This is an intermediate code after the execution of the instruction order change process of No. 4. The order of the instructions L5 and L4 and the instructions L8 and L7 have been changed.

[0087]

[Table 5]

Tables 6 and 7 show the result of the instruction order changing process of 1504 for the execution unit of the while loop in Table 4. In an execution unit lower than the whole, the order is changed in addition to the instruction sequence before and after the unit, but only the instruction in the execution unit is changed, and the order added to the instruction added before and after is not changed. Table 6 shows the result of first selecting LB1 and changing the order, and Table 7 shows the result of selecting LB2 and changing the order. As a method of evaluating the result of this change, there is a dependency if the label of the instruction is in the dependency list of the instruction immediately after the instruction. L in Table 6
LB2 exists in the dependency list of the instruction LB3 immediately after B2. In Table 7, there is no such instruction sequence. Table 7
Is selected.

[0089]

[Table 6]

[0090]

[Table 7]

Tables 8 and 9 show examples of assemblers corresponding to the intermediate code and the final machine language, and are instruction sequences in which execution units are also expanded. LB2 and LB1, L5 and L
4. The order of L8 and L7 has been changed from the original instruction order. 1407 is performed on this data, but no NOP is inserted since the instruction order in Table 8 has no instruction dependency.

[0092]

[Table 8]

[0093]

[Table 9]

When the software program codes in Table 9 are executed in a hardware / software co-verification environment,
The cycle-accurate model is used in the branch instruction BEQ portion, but there is no sequence that causes a data hazard that is dependent on the instruction sequence in other instructions. Therefore, the hardware / software co-verification can be executed at higher speed. As described above, according to the third embodiment of the present invention, an instruction code that can be simulated at higher speed by hardware / software co-verification is generated by a compiler method. Can be. Further, in the hardware / software co-verification for verifying the interaction between the hardware and the software, an enormous simulation is performed, so that a higher-speed verification is possible.

[0095]

According to the hardware / software co-verification method according to the first aspect of the present invention, a software program code executed by the processor unit and the logic circuit unit interact with each other. For the simulation of the circuit under test
By providing a plurality of processor simulation models and a logic circuit simulation model, and dynamically switching the processor simulation model during execution of the simulation, the simulation accuracy can be improved without reducing the simulation speed.

According to the hardware / software co-verification method of the second aspect, the dependence is checked according to the instruction sequence of the software program code executed by the processor unit, and the processor simulation model to be selected is determined. In addition, by performing the cooperative simulation while dynamically switching the determined simulation model, it is possible to prevent deterioration of the simulation accuracy depending on the processor simulation model and the instruction sequence.

According to the hardware / software co-verification method of the third aspect, in addition to the same effects as those of the first aspect, in the synchronization processing of the processor simulation model and the logic circuit unit, the logic circuit unit is simulated by the processor simulation model. Advance ahead of time,
By detecting exception processing such as interrupts transmitted from the logic circuit section to the processor simulation model, and dynamically switching the processor simulation model according to the occurrence of the exception processing, the interaction between the processor section and the logic circuit section can be performed. In addition, it is possible to prevent the simulation accuracy from deteriorating due to exceptionally occurring processing.

According to the hardware / software co-verification method of the fourth aspect, by generating the software program code of the program instruction arrangement method, the instruction arrangement method of the software program code can be optimized for the code amount and the speed. Hardware, which is performed before the actual production of hardware,
Since optimization for high accuracy and high speed of software co-verification is performed, the verification time of the interaction between hardware and software can be reduced.

According to the hardware / software co-verification method of the fifth aspect, in addition to the same effects as those of the fourth aspect, a high-level language actually described by a compiler that generates a software program code by a program instruction array system By using, a huge amount of system verification can be shortened, and the system development period can be shortened.

[Brief description of the drawings]

FIG. 1 is a schematic conceptual diagram of hardware / software co-verification according to a first embodiment of the present invention.

FIG. 2 is a processing flow of a processor simulation model and a logic circuit simulation model according to the first embodiment of the present invention.

FIG. 3 is a switching flow of a processor simulation model in the first and second embodiments of the present invention.

FIG. 4 is an example of a software program code provided to a processor according to the first and second embodiments of the present invention.

FIG. 5 is an explanatory diagram showing a flow of instructions executed by a processor unit according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram showing instructions simulated by each processor simulation model in the simulation according to the first embodiment of the present invention.

FIG. 7 is an overall schematic diagram of a circuit to be verified according to the first and second embodiments of the present invention;

FIG. 8 is a diagram showing an example of a hardware configuration for realizing the hardware / software co-verification method of the present invention.

FIG. 9 is a processing flow of a processor simulation model and a logic circuit simulation model according to the second embodiment of the present invention.

FIG. 10 is an example of a software program code at the time of interrupt processing given to a processor according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a flow of instructions executed by a processor unit according to the second embodiment of the present invention.

FIG. 12 is a diagram showing instructions simulated by each processor simulation model according to the second embodiment of the present invention.

FIG. 13 is a diagram illustrating an example of a processing flow of a compiler according to the third embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a processing flow of a compiler according to the third embodiment of the present invention.

[Explanation of symbols]

103 Processor simulation model 105 Logic circuit simulation model 201, 1001 Processor simulation model processing flow 202, 1002 Logic circuit simulation model processing flow 213 Instruction sequence dependence detection processing 302 Processor instruction level simulation model 303 Processor cycle accurate simulation model 401 Processor instruction set 501 Software program code 801 Circuit to be verified 1016 Exception determination processing 1023 Exception signal specification processing 1025 Exception occurrence detection processing 1101 Exception processing software program code 1404 Instruction order change processing 1406 Dependency resolution processing 1504 Instruction order change within execution unit Processing 1701 intermediate code 2002 corresponding to machine language Assembler code

Claims (5)

[Claims] 1. A hardware / software co-verification method in a simulation method for an operation of a circuit to be verified including a processor unit and a logic circuit unit, wherein an instruction operation of software for controlling the processor unit is executed on a computer. A plurality of processor simulation models to be simulated; a logic circuit simulation model for simulating the logic circuit unit on a computer; a model switching unit for dynamically switching the plurality of processor simulation models; And a synchronization unit for synchronizing the simulation of the processor simulation model and the simulation of the logic circuit simulation model, and verifies the instruction operation of software of the processor unit and the operation of the logic circuit unit that interact with each other. Hardware / software co-verification method comprising Ukoto. 2. A method for determining a processor simulation model to be selected according to an instruction sequence of a software program code, comprising: a simulation model determining unit configured to dynamically convert the processor simulation model based on information from the simulation model determining unit; 2. The hardware / software co-verification method according to claim 1, wherein the method is switched to: 3. A synchronous processing means for advancing the simulation time of the logic circuit simulation model ahead of the simulation time of the processor simulation model, and exception processing input to the processor simulation model from outside the logic circuit simulation model and the circuit to be verified. 2. The hardware / software co-verification method according to claim 1, further comprising: an exception occurrence detecting unit that detects a signal, wherein the model switching unit dynamically switches a processor simulation model based on information of the exception occurrence detecting unit. 4. A program instruction array system for optimizing a processor simulation model for high-speed simulation and changing an instruction order so as to optimize for cooperative verification with a logic circuit simulation model to maintain high accuracy. A hardware / software co-verification method having: 5. The hardware / software co-verification method according to claim 4, further comprising a compiler having a function of determining an instruction array in a program instruction array system.