JP2994280B2 - Computer system performance evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system, and more particularly to a method for evaluating the performance of a computer system.

[0002]

2. Description of the Related Art With the recent development of semiconductor technology, computers of various architectures have been devised and put into practical use.

[0003] Since the computer system in the early days had a relatively simple configuration, its processing capability was limited to a central processing unit (CP).
U), but the architecture is becoming more and more complicated with a hierarchical memory structure, multiple buses, write buffers, etc., for further improving the processing capability. As a result, the performance of the computer system strongly depends not only on the processing capability of the CPU itself but also on the architecture of the entire computer such as the memory, I / O, and bus. Therefore, in order to develop a computer or run an application program at a high speed on a specific computer system,
Hardware needs to be optimized for the architecture.

[0004] Under the above-mentioned background, a technique of performance evaluation has been attracting attention as a technique for optimizing the operation of a hardware architecture in advance by simulating the operation of the hardware architecture.

In the conventional performance evaluation method, a strict operation model of a cache memory and a main memory is prepared, and it is determined whether or not a memory access is made for each instruction of a program to be evaluated. Strictly evaluates the operation of the cache from the reference address, and determines a cache hit / miss. In the case of a cache miss, the operation of the main memory is strictly evaluated from the reference address, and a page hit / miss is determined. A rigorous evaluation of these memories is performed for every executable instruction.

[0006]

The above-described conventional method for evaluating the performance of a computer system prepares and evaluates detailed operation models of the cache memory and the main memory, so that accurate performance estimation can be performed. Requires a large amount of time, requires a detailed operation model of the memory, and has a problem that it is difficult to obtain the execution time of the program using the cache hit ratio and the page hit ratio as parameters.

An object of the present invention is to provide a computer system performance evaluation method which realizes high-speed performance evaluation without requiring detailed operation models of a cache memory and a main memory.

[0008]

A computer system performance evaluation method according to the present invention fetches instructions of a program to be evaluated in the order of execution, determines whether the instructions have memory access, and does not include memory accesses. If the CPU
The number of execution clocks of the instruction is obtained from an execution clock table that stores information on the number of clocks necessary to execute each execution instruction of the above instruction, and is added to the total execution clock counter.If the instruction includes a memory access, , A cache hit / miss is stochastically determined from a reference address of an instruction and a cache hit rate parameter at the time of cache memory access, and in the case of a cache hit, the number of clocks required for cache access is obtained from the execution clock table to execute the total execution. In the case of a cache miss, a page hit / miss is determined stochastically from the reference address of the instruction and a page hit rate parameter at the time of memory access, and the execution clock table is determined according to the page hit / miss. Number of clocks required for memory access Calculated by adding the total execution clock counter, and obtains the total number of clocks for executing said evaluation object program.

[0009]

Next, an embodiment of the present invention will be described.
This will be described in detail with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the performance evaluation method of the present invention. As shown in FIG. 1, the total execution clock counter is initialized (11), and one instruction to be executed is extracted from the evaluation target program (12). Next, the extracted instruction is checked for its bit string, and it is determined whether the instruction includes a memory access or an instruction using only the ALU (13).

When the memory access is not included, the number of execution clocks corresponding to each instruction is obtained by using the execution clock table and added to the total execution clock number counter (1).
4). When the instruction includes a memory access, a cache hit / miss is determined using a probability function from a cache hit rate given in advance. The probability function is realized by randomly generating a number from 0 to 1.0 using a random function, for example, and comparing it with a preset cache hit rate (0 <cache hit rate <1.0). .

If a cache hit is determined, the number of clocks required for cache access is obtained from the execution clock table and added to the total execution clock counter (17). When a cache miss is determined, a page hit / miss at the time of memory access is determined using a probability function from a page hit rate given in advance. The probability function is realized by the same principle as that of the cache hit / miss determination.

After the page hit / miss determination, the number of clocks required for memory access according to the page hit / miss is obtained from the execution clock table, and added to the total execution clock counter (19, 20). The above processing is executed for all the instructions executed by the evaluation target program.

In this embodiment, when evaluating the operation of the cache memory and the main memory system, the function evaluation of the memory system can be simplified by using a probability function, and high-speed performance evaluation can be realized. Further, it is possible to evaluate hardware and software to be evaluated using the cache hit ratio and the page hit ratio as parameters.

When the hardware architecture such as the cache memory size, the memory size, and the page size of the computer to be evaluated is changed, it is dealt with by changing the parameters of the cache hit ratio and the page hit ratio.

[0016]

As described above, in the performance evaluation method of the computer system according to the present invention, a cache hit / miss and a page hit / miss are determined by a probability function. This eliminates the need for high-speed simulation, and enables evaluation of the hardware and software to be evaluated by obtaining the total number of clocks during program execution using the cache hit ratio and page hit ratio as parameters. Has the effect of becoming

[Brief description of the drawings]

FIG. 1 is a flowchart showing one embodiment of a performance evaluation method of the present invention.

[Explanation of symbols]

 11-20 processing steps

Claims (3)

(57) [Claims] 1. An instruction of a program to be evaluated is fetched in an execution order, and it is determined whether or not the instruction has a memory access. If the instruction does not include a memory access, it is necessary to execute each execution instruction of a CPU. The number of execution clocks of the instruction is obtained from an execution clock table storing information on the number of clocks, and added to the total execution clock counter. If the instruction includes a memory access, a reference address of the instruction and a cache memory access time A cache hit / miss is stochastically determined from the cache hit ratio parameter. In the case of a cache hit, the number of clocks required for cache access is obtained from the execution clock table and added to the total execution clock counter. Is the reference address of the instruction and the A page hit / miss is stochastically determined from the di-hit ratio parameter, the number of clocks required for memory access is obtained from the execution clock table in accordance with the page hit / miss, and added to the total execution clock counter; A method for evaluating the performance of a computer system, comprising: obtaining a total number of clocks for executing the program. 2. A cache hit rate parameter and a page hit rate parameter are changed when a hardware architecture such as a cache memory size, a memory size, and a page size of a computer to be evaluated is changed. A method for evaluating the performance of a computer system according to claim 1. 3. An execution clock table for storing information on the number of clocks required to execute each execution instruction of a CPU, a cache hit rate parameter when accessing a cache memory, a page hit rate parameter when accessing a memory, A total execution clock counter for calculating the total number of clocks for executing the program, fetching the instructions of the program to be evaluated in the order of execution, determining the presence or absence of memory access of the instructions, and If not, the number of execution clocks of the instruction is obtained from the execution clock table and added to the total execution clock counter.If the instruction includes memory access, the reference address of the instruction and the cache hit ratio parameter are used. Cache hit / miss is determined stochastically, and cache hit In the case of a cache hit, the number of clocks required for cache access is obtained from the execution clock table and added to the total execution clock counter. In the case of a cache miss, a page hit / miss is obtained from the reference address of the instruction and the page hit rate parameter. Is determined stochastically, the number of clocks required for memory access is obtained from the execution clock table in accordance with a page hit / miss, and added to the total execution clock counter to obtain the total execution clock number of the evaluation target program. A computer system characterized by the following.