JPH07191844A - Microprocessor with programmable logic - Google Patents

Abstract

PURPOSE:To arbitrarily define one part of a system non-defined instruction as a user defined instruction at least and further to execute the user defined instruction without delaying it. CONSTITUTION:At the time of starting a system, configuration control data are written in a RAM part 20 of an FPGA 10 by operating an instruction executing part 4 according to an initializing program so that a control logic decided by those configuration control data can be constructed on a logic part 30. This control logic is provided with the functional configuration of an instruction analystic part 31 and an instruction executing part 32 or the like which are turned to an enable state by a non-defined signal transmitted through a control line 14 when the system non-defined instruction is analyzed by an instruction analystic part 3, this system non-defined instruction is received through an internal bus 11 and analyzed and when it is the user defined instruction, processing designated by that instruction is executed. When it can be normally executed, status information showing that is reported through a gate 33 to the instruction executing part 4 and the generation of internal exceptional interruption based on the non-defined signal is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable microprocessor suitable for executing at least a part of system-undefined instructions as user-defined instructions in a standard microprocessor whose executable functions are fixedly determined. Regarding a microprocessor with logic.

[0002]

2. Description of the Related Art Generally, in a microprocessor such as a RISC (reduced instruction set computer) processor which does not adopt a microprogram system, all the functions that it can execute are fixedly determined. Therefore, in order to realize the required function for each user, it is necessary to provide an external logic and control the external logic.

However, the only instructions that can be used to control the external logic are input / output instructions (load instructions / store instructions). Therefore, for example, to output the result of a certain operation performed by the microprocessor to the external logic,
A lot of instruction processing is required, such as executing an arithmetic instruction and outputting the result obtained by executing the arithmetic instruction to an external logic by an input / output instruction, which is very difficult for a user to execute a required function. I needed time.

Further, in this type of microprocessor,
Some instruction code is undefined. For example, 256 types of instructions can be defined with an 8-bit instruction word code, but only about 80 types are defined by a standard microprocessor, and the rest are undefined. When this undefined instruction word code appears in the program, an undefined signal is generated in the conventional microprocessor (at the time of execution of the undefined instruction), an internal exception interrupt occurs, and the software (operating system) An undefined instruction was being processed. For this reason, there is a problem that the processing becomes slow if an undefined instruction is defined for each user and executed by the system.

[0005]

As described above, in a microprocessor that does not adopt the microprogram system, that is, in the microprocessor in which executable instructions are fixedly defined, conventionally, the functions that cannot be executed by the microprocessor. If you try to realize the above for each user, you will have to control the external logic using input / output instructions, or process it by software in response to an internal exception interrupt that occurs when an undefined instruction is executed, which slows down processing. was there.

The present invention has been made in consideration of the above circumstances, and an object thereof is to realize an arbitrary function by rewriting configuration control data in a standard microprocessor in which executable instructions are fixedly defined. By including programmable logic that can be built, at least part of system undefined instructions can be arbitrarily defined as user-defined instructions.
Moreover, it is to provide a microprocessor with a programmable logic capable of executing the user-defined instruction without causing a delay in processing.

Another object of the present invention is to provide a microprocessor with programmable logic in which the microprocessor function can be easily customized for each user.

Still another object of the present invention is to provide a microprocessor with programmable logic, which allows a user to directly control logic outside the processor for determining specifications.

[0009]

Means and Actions for Solving the Problems
A system that cannot be executed by the microprocessor by incorporating programmable logic into a standard microprocessor in which executable instructions are fixedly defined and by writing arbitrary configuration control data to the programmable logic. Control logic for interpreting / executing at least a part of undefined instructions as user-defined instructions. If the instruction to be executed is a user-defined instruction, internal control is performed according to an undefined signal generated by the microprocessor. It is characterized in that the control logic for suppressing the occurrence of the exception interrupt is constructed.

In such a configuration, by selecting the configuration control data written in the memory part of the programmable logic, it is possible to realize a control logic that interprets and executes at least a part of the system undefined instruction as a user-defined instruction. The user-defined instruction requested by the user can be executed without causing a delay in processing. Moreover, the control logic realized in this manner can prevent the internal exception interrupt from being generated in response to the undefined signal generated by the microprocessor when the instruction to be executed is the user-defined instruction. Therefore, the execution of the user-defined instruction in the control logic (the programmable logic that constructs the control logic) is not wasted.

The present invention is also characterized in that the configuration control data is written to the programmable logic by executing an initialization program consisting of a sequence of fixedly defined instructions (system-defined instructions). .

By doing so, arbitrary configuration control data for realizing the function required by the user can be
Programmable by initialization processing at system startup
Since the data can be written in the memory part of the logic, the microprocessor function can be easily customized for each user.

Further, according to the present invention, a first signal line for transmitting information from a logic external to the processor whose specifications can be arbitrarily determined to a programmable logic, and control information from the programmable logic to the external logic. And a second signal line for controlling the external logic when the user-defined instruction to be executed is defined by the configuration control data written in the programmable logic. The instruction and the information transmitted from the external logic via the first signal line are interpreted and executed, and the execution result is output to the external logic via the second signal line for control. It is also characterized by constructing a control logic to do so.

By doing so, the control logic (programmable logic that constructs the) executes a user-defined instruction for controlling the external logic, and the external logic is directly controlled based on the execution result. Is possible.

[0015]

1 is a block diagram showing the structure of a microprocessor with programmable logic according to an embodiment of the present invention. The microprocessor shown in FIG.
It is, for example, a one-chip microprocessor that does not adopt a microprogram system, which is represented by an ISC processor.

The present microprocessor includes a bus controller (BC) 1 for controlling an interface with a system bus (not shown) outside the processor, and a bus controller 1.
An instruction buffer 2 for temporarily holding the instructions read from a memory (not shown) through the reading order,
The instruction analysis unit 3 analyzes (decodes) the processing contents designated by the instructions held in the instruction buffer 2 in order and outputs various control signals necessary for the processing to each unit in the processor. When the analyzed instruction is an undefined instruction in the system (system undefined instruction), the instruction analysis unit 3
It outputs an undefined signal.

The present microprocessor also has an instruction execution unit 4 for executing the processing instructed by the instruction (system-defined instruction) analyzed by the instruction analysis unit 3 based on the analysis result of the instruction analysis unit 3. ing. When the instruction analyzed by the instruction analysis unit 3 is a system undefined instruction, the instruction execution unit 4 outputs the instruction output from the instruction analysis unit 3 unless status information on the control line 15 described later is valid. An internal exception interrupt is generated based on the definition signal. In addition, the instruction execution unit 4 also writes the configuration control data to the RAM unit 20 of the FPGA 10 described later according to the initialization program (system definition instruction sequence therein) at the time of initialization.

The present microprocessor further holds an operand buffer 5 for temporarily holding the operand data which is the execution result (instruction processing result) of the instruction execution section 4, and the operand data held in this operand buffer 5. A register file (RF) 6 composed of a register group for

In addition to the bus controller 1, the instruction buffer 2, the instruction analysis unit 3, the instruction execution unit 4, the operand buffer 5 and the register file 6 described above, a part or all of the system undefined instructions are included in the present microprocessor. Programmable logic that realizes an arbitrary control logic for interpretation / execution as a user-defined instruction, such as F
A PGA (Field Programmable Gate Array) 10 is built in.

As is well known, the FPGA 10 is composed of a RAM section 20 in which configuration control data is set, and a logic section 30 which realizes a function determined by the configuration control data set in the RAM section 20.

The FPGA 10 is connected to the instruction analysis unit 3 by the internal bus 11, the instruction execution unit 4 by the internal bus 12, and the operand buffer 5 by the internal bus 13.

The internal bus 11 is for transmitting the instruction analyzed by the instruction analysis unit 3 to the logic unit 30 of the FPGA 10. The internal bus 12 is for transmitting the execution result of the instruction execution unit 4 to the RAM unit 20 or the logic unit 30 of the FPGA 10. The internal bus 13
It is for transmitting a user-defined instruction execution result of an instruction execution unit 32, which will be described later, realized in the logic unit 30 of the FPGA 10 to the operand buffer 5.

The FPGA 10 is also connected to the instruction analysis unit 3 by the control line 14, the instruction execution unit 4 by the control line 15, and the logic (not shown) outside the processor by the control lines 16 and 17. . The external logic allows the user to determine the specifications, and is, for example, an audio device.

The control line 14 sends an undefined signal generated when the instruction analysis unit 3 analyzes the system undefined instruction to the FPG.
It is for transmission to the logic unit 30 of A10.
The control line 15 is for transmitting status information indicating a user-defined instruction execution state in the instruction execution unit 32 realized by the logic unit 30 of the FPGA 10 to the instruction execution unit 4. The control line 16 transmits information (status information) from the external logic to the logic unit 30 of the FPGA 10, and the control line 17 is a control signal for controlling the external logic from the instruction execution unit 32 in the logic unit 30. It is for transmitting.

The logic unit 30 of the FPGA 10 is a RAM
The control logic including the instruction analysis unit 31, the instruction execution unit 32, and the gate (G) 33 is realized by the configuration control data set in the unit 20.

The command analysis unit 31 selects a system undefined command defined as a user-defined command by the configuration control data set in the RAM unit 20 among the commands transmitted via the internal bus 11, and further controls the control line 16. It is configured to analyze the processing content designated by the instruction based on the status information from the external logic transmitted via the.
The instruction analysis unit 31 is enabled (operable) only when a valid undefined signal is transmitted via the control line 14, for example.
It becomes a state.

The instruction execution section 32 is configured to execute the processing instructed by the instruction (user-defined instruction) analyzed by the instruction analysis section 31. Gate 33 is control line 1
When the undefined signal transmitted to the instruction analysis unit 31 via 4 is valid, status information indicating a user-defined instruction execution state in the instruction execution unit 32 is output to the control line 15.

Next, the operation of the configuration shown in FIG. 1 will be described. First, when the system is started up, an initialization program is executed in the microprocessor of FIG. 1, and as described below, a process of writing configuration control data arbitrarily determined by the program into the RAM section 20 of the FPGA 10 is performed. At system startup, depending on the status of a specific bit in the control register (not shown), the FPGA
R of the RAM section 20 and the logic section 30 in 10
The AM section 20 is set to the enabled state, and after the system is started up, the logic section 30 is set to the enabled state.

Now, at the time of system startup, it is assumed that an instruction sequence forming an initialization program is read from the memory into the microprocessor through the bus controller (BC) 1 and held in the instruction buffer 2. The instruction sequence held in the instruction buffer 2 is transferred to the instruction analysis unit 3 one instruction at a time, for example.

The instruction analysis unit 3 analyzes the processing content designated by the instruction transferred from the instruction buffer 2. The instruction analysis unit 3 also outputs various control signals necessary for executing the analyzed processing to the instruction execution unit 4 and the like. Further, the instruction analysis unit 3 reads the operand data used for the analyzed processing from the register file (RF) 6 and outputs it to the instruction execution unit 4.

The instruction execution unit 4 is activated by a control signal from the instruction analysis unit 3 and uses the operand data output from the instruction analysis unit 3 to execute the processing instructed by the corresponding instruction. If this instruction is RA of FPGA10
If the instruction is to write the configuration control data to the M unit 20, the instruction execution unit 4 executes the operation so that the operand data designated by the instruction is internally stored at the address of the RAM unit 20 designated by the instruction as the configuration control data. Written via bus 12.

By repeating the above, R of FPGA 10
The configuration control data determined by the initialization program is written in the AM unit 20. Therefore, for each user,
An arbitrary initialization program is prepared so that any configuration control data can be stored in the RAM section 20 in the initialization process when the system is started up.
To the logic unit 30 of the FPGA 10 by writing
The function (control logic) desired by the user can be realized on the above. The inside of the logic unit 30 in FIG. 3 shows this state, and the control logic including the instruction analysis unit 31, the instruction execution unit 32, and the gate (G) 33 is changed by the configuration control data written in the RAM unit 20. Has been realized.
Also, the analysis function of the instruction analysis unit 31 can be arbitrarily realized by the configuration control data. Here, a function of analyzing some or all of the instructions handled as undefined instructions by the instruction analysis unit 3 as user-defined instructions is added.

Next, the operation after writing the above configuration data, that is, the operation after the system is started up will be described.
First, it is assumed that the instruction to be executed by the microprocessor of FIG. 1 is read from the memory through the bus controller 1 and transferred to the instruction analysis unit 3 through the instruction buffer 2.

The instruction analysis unit 3 analyzes the processing content designated by the instruction transferred from the instruction buffer 2 and outputs various control signals necessary for executing the analyzed processing to the instruction execution unit 4 and the like. If an instruction whose processing content is not defined, that is, a system undefined instruction is analyzed, the instruction analysis unit 3 outputs an undefined signal to the instruction execution unit 4. Even in this case, some control signal is output to the instruction execution unit 4 or the like as a result of instruction analysis, and some execution processing is performed.

At the same time, the instruction analysis unit 3 outputs this undefined signal on the control line 14 and the corresponding system undefined instruction on the internal bus 11, respectively. The instruction analysis unit 31 implemented on the logic unit 30 of the FPGA 10 is enabled when an undefined signal on the control line 14 is valid, and an instruction transmitted via the internal bus 11 (here, it is not in the system). Analyze the processing contents instructed by the definition user-defined instruction). At this time, depending on the user-defined instruction, the processing content is analyzed based on the instruction and the status information of the external logic transmitted via the control line 16.

When the analyzed instruction (system undefined instruction) is a user-defined instruction, the instruction analysis unit 31 outputs various control signals necessary for executing the analyzed processing to the instruction execution unit 3
Output to 2 etc. The instruction analysis unit 31 also outputs the valid undefined signal on the control line 14 to the gate 33 as it is.

On the other hand, if the analyzed system undefined instruction is not a user-defined instruction, or if it is a user-defined instruction to be analyzed including the status information on the control line 16, the status information (external logic If it is in the disabled state (because it is not connected),
The output of a valid undefined signal to the gate 33 is suppressed. In this case, since the gate 33 is closed, valid status information is not transmitted to the instruction execution unit 4 via the control line 15.

The instruction execution section 4 performs some execution processing according to the control signal from the instruction analysis section 3 regardless of whether or not the system undefined instruction is discriminated by the instruction analysis section 3. However, when the system undefined command is determined (that is, when the command analysis unit 3 outputs an undefined signal), and when valid status information indicating normal execution is not transmitted from the control line 15, the command The execution unit 4 generates an internal exception interrupt as in the conventional case, and leaves the processing of the undefined instruction to software (operating system). In this case, the execution result of the instruction execution unit 4 becomes invalid.

Now, the instruction executing section 32 has the instruction analyzing section 31.
It is activated by the control signal from and executes the processing content analyzed by the instruction analysis unit 31. Then, if the instruction execution unit 32 can be normally executed, it outputs valid status information indicating that to the gate 33. At this time, if the undefined signal is output from the instruction analysis unit 3 to the gate 33 as described above, the valid status information from the instruction execution unit 32 is transferred from the gate 33 to the instruction execution unit via the control line 15. 4 is transmitted.

The instruction executing section 32 also writes the execution result of the user-defined instruction in the operand buffer 5. The execution result stored in the operand buffer 5 is transferred to the register file (R
F) It is written back to 6.

If the user-defined instruction is defined to control the external logic, the instruction execution section 32 outputs the execution result of the user-defined instruction to the external logic via the control line 17, and the external logic is executed. Control the logic directly.

In the case of a user-defined instruction defined to utilize the arithmetic function (calculation result) of the instruction execution unit 4, the instruction execution unit 32 transfers the calculation result of the instruction execution unit 4 to the internal bus 12. And receive the necessary processing. Even if this is a user-defined instruction that is undefined in the system, the instruction execution unit 4 performs some execution processing according to the analysis result of the instruction analysis unit 3. Therefore, depending on the instruction,
This is because it is possible to use the execution result of the instruction execution unit 4 without invalidating it.

The instruction executing section 4 executes normally via the control line 15 even when the instruction analyzing section 3 determines a system undefined instruction and the instruction analyzing section 3 outputs an undefined signal. When the valid status information indicating the is transmitted, the occurrence of the internal exception interrupt is suppressed (assuming that the undefined instruction is normally executed on the FPGA 10 side as the user-defined instruction). This allows the FPG
The execution result in the instruction execution unit 32 realized on the logic unit 30 of A10 becomes valid, and the execution result in the instruction execution unit 4 can be used in the instruction execution unit 32 as described above.

In the above embodiment, the instruction analysis unit 31 on the logic unit 30 of the FPGA 10 is not designed to control the instruction execution unit 4, but in the case of a user-defined instruction, the instruction analysis unit 3 outputs The output control signal may be invalidated, and the instruction analysis unit 31 itself may control the instruction execution unit 4 in the same manner as the instruction execution unit 32. Further, the instruction analysis unit 31 may use the register file 16 similarly to the instruction analysis unit 3.

[0045]

As described above in detail, according to the present invention,
A system that cannot be executed by the microprocessor by incorporating programmable logic into a standard microprocessor in which executable instructions are fixedly defined and by writing arbitrary configuration control data to the programmable logic. Since the control logic for interpreting and executing at least a part of the undefined instruction as a user-defined instruction is constructed, if the instruction is a user-defined instruction even if it is a system undefined instruction, In this case, the processing can be executed without delaying the processing. Moreover, the control logic constructed in this way can prevent the internal exception interrupt from being generated in response to an undefined signal generated by the microprocessor when the instruction to be executed is a user-defined instruction. Therefore, the execution of the user-defined instruction in the control logic (the programmable logic that constructs the control logic) is not wasted.

Further, according to the present invention, by writing the configuration control data to the programmable logic by executing an initialization program consisting of a sequence of fixedly defined instructions (system-defined instructions), The processor function can be easily customized for each user.

Further, according to the present invention, the logic outside the processor and the programmable
If the user-defined instruction to be executed is a system undefined instruction that controls the external logic by the configuration control data written in the programmable logic by providing the input / output signal line with the logic, , The instruction logic and the information given from the external logic are interpreted and executed, and the execution result is output to the external logic to construct the control logic. By executing a user-defined instruction for controlling the external logic with (logic), the external logic can be directly controlled based on the execution result.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor with programmable logic according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Bus controller (BC), 2 ... Instruction buffer, 3
... instruction analysis unit, 4 ... instruction execution unit, 5 ... operand buffer, 6 ... register file (RF), 10 ... FPGA
(Programmable logic), 20 ... RAM section (memory section), 30 ... Logic section, 31 ... Instruction analysis section, 32 ...
Instruction execution unit, 33 ... Gate (G), 11 ... Internal bus, 1
2 ... internal bus, 13 ... internal bus, 14 ... control line, 15 ...
Control line, 16 ... Control line (first signal line), 17 ... Control line (second signal line).

Claims (3)

[Claims] 1. A microprocessor for generating an undefined signal for generating an internal exception interrupt when an executable instruction is fixedly defined and the instruction to be executed is an undefined instruction in the system. A programmable logic that realizes an arbitrary control logic according to the set configuration control data, and by writing the arbitrary configuration control data in the programmable logic, at least part of the system undefined instruction Is a control logic for interpreting and executing as a user-defined instruction, and when the instruction to be executed is the user-defined instruction, the generation of the internal exception interrupt due to the generation of the undefined signal in the microprocessor is suppressed. A programmable logic controller with a programmable logic Black processor. 2. The programmable logic according to claim 1, wherein the configuration control data is written to the programmable logic by executing an initialization program consisting of the fixedly defined sequence of instructions. With microprocessor. 3. A first signal line for transmitting information from a logic external to the processor, the specification of which can be arbitrarily determined, to the programmable logic, and for transmitting control information from the programmable logic to the external logic. And a second signal line of the above, the instruction is executed when the user-defined instruction to be executed is a system undefined instruction defined by the configuration control data written in the programmable logic to control the external logic. Is executed based on the instruction and the information transmitted from the external logic via the first signal line, and the execution result is output to the external logic via the second signal line. 2. The microprocessor with programmable logic according to claim 1, wherein the control logic for controlling the microprocessor is constructed.