JPH10307607A - Main processor and programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a controller which makes a ladder language and a flow language usable and enables a main and a subordinate processor to operate in parallel by providing a data for passing data between the main and subordinate processors and a means which arbitrates access to a memory from the main and subordinate processors. SOLUTION: The main processor 1 has an arithmetic circuit 11, a 1st register 12a and a 2nd internal register 12b, a table 13, an arbitrating circuit 14, etc. The main processor 1 executes basic instructions. When there is an application instruction macro, parameters which are needed for execution by the subordinate processor 2 are stored in the table 13 and the subordinate processor 2 reads the table 13 once interruption is initiated and then executes the application macroinstruction. An arbitrating circuit 14 arbitrates access from the main processor 1 to the memory 3 and access from the subordinate processor 2 to the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main processor or a programmable controller that uses a ladder language or a flow language and performs a sequence operation with a plurality of processors, and more particularly to a method of handing over processing between the processors.

[0002]

2. Description of the Related Art Conventionally, FIG. 7 shows the configuration of a programmable controller using a ladder language and using two processors for sequence operation.

A conventional programmable controller is composed of a main processor 1 ', a sub processor 2', a memory 3 ', buses 4a', 4b ', etc.

The main processor 1 'and the sub processor 2'
It is connected by a bus 4a 'and the main processor 1'
And the memory 3 ′ were connected by the bus 4b ′.

One interrupt signal IRQ1 'is connected from the main processor 1'to the sub processor 2'.

The main processor 1 'has an arithmetic circuit 11', a register 12 ', a table 13' and the like.

The output of the register 12 is the interrupt signal IRQ.
1 '.

The parameter table 13 'stores parameters necessary for the sub-processor 2' to execute the application instruction macro.

The main processor 1 'executes basic ladder instructions such as contacts, coils, etc.
The interrupt to the sub-processor 2 'has been executed by the interrupt signal IRQ1' output from 2 '.

The sub processor 2'via the bus 4a ',
It was executing the application instructions of the ladder.

The memory 3'stores user programs, system programs, I / O data, etc., and the bus 4b '.
And exchanges data with the main processor 1 'via the.

There are various methods of sharing the processing between the main processor 1 'and the sub-processor 2'.
Assuming that the application instruction is executed by the sub-processor 2 ', a description will be given of a conventional processing delivery method with reference to FIGS. 8, 9 and 10. FIG.

FIG. 8 shows a part of a ladder program input by a user using a dedicated ladder language input device. As shown in FIG. 'Is stored in the user program area.

The application instructions in the ladder program generally take the form of subroutines, and the actual processing is stored in the system program area.

Further, in FIG. 8, the application instruction 1 outputs the operation result as X.
1 indicates that the instruction is reflected in 1, and the application instruction 2 indicates that the operation result is not reflected anywhere. Other arguments and the like are not specified here.

FIG. 10 is a time chart showing an outline of the operation of each processor.

When activated, the main processor 1 'starts executing from the top of the user program.

When step n + 3 is executed, the internal register 1
"1" is written to 2 ', an interrupt is output to the sub processor 2, and the main processor 1' enters the WAIT state. At this time, it is assumed that the parameters necessary for the sub processor 2'to execute the application instruction 1 are stored in the parameter table 13 'in the main processor 1'.
When an interrupt occurs, the sub-processor 2 'reads the parameter table 13' and starts executing the application instruction 1 macro. At the end of the execution of the application instruction 1 macro, "0" is stored in the internal register 12 'of the main processor 1' via the bus 4a '.
Write. At this point, the main processor 1'cancels the WAIT and starts executing the next instruction of the user program.

This is executed up to the end of the user program to complete one scan.

[0020]

In the above-mentioned conventional technique, the main processor 1'is always in the WAIT state while the sub processor 2'is executing the macro of the application instruction.

In the user program shown in FIG. 8, since the applied instruction 1 is an instruction for reflecting the operation result on X1, the main processor 1 'needs to be in the WAIT state until the processing is completed. However, as in the case of the instruction having no return of the operation result shown in the application instruction 2, even the instruction that can be executed by the main processor 1 'without waiting until the sub-processor 2' completes the processing enters the WAIT state.

An object of the present invention is to provide a programmable controller which can use a ladder language and a flow language, and in which a main processor and a sub-processor can operate in parallel.

[0023]

In order to achieve the above object, the present invention provides a program and I / O created by a user.
In a main processor used for a programmable controller including a memory for storing data, a main processor that starts an operation upon activation by a user, and a sub-processor that executes a sequence operation in response to an interrupt from the main processor, When executing a specific instruction of a kind, a register of two or more to which a specific value is written, a table for passing data between the main processor and the sub processor, and access to the memory from the main processor and the sub processor. Is a main processor for a programmable controller having a means for arbitrating.

Further, the present invention provides a memory for storing a program and I / O data created by a user, a main processor for starting an operation upon activation by a user, and a sub-processor for executing a sequence operation by an interrupt from the main processor. And a processor, wherein the main processor is configured to execute, when executing a plurality of types of specific instructions, two or more registers to which specific values are written;
The programmable controller includes a table for passing data between the main processor and the sub-processor, and means for arbitrating access from the main processor and the sub-processor to the memory.

The present invention is a main processor or programmable controller whose language is a ladder language.

Further, the present invention is a main processor or a programmable controller in which the number of sub-processors is one, the number of interrupts is two, and the number of registers is two.

Further, the present invention is a main processor or programmable controller whose flow language is a flow language.

The present invention is a main processor or programmable controller in which the number of sub-processors, the number of interrupts, and the number of registers are all the same and two or more.

Furthermore, the present invention is a main processor or a programmable controller in which a sub processor can read or write a plurality of registers provided in the main processor.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.

An embodiment using a ladder language for the main processor and the programmable controller of the present invention will be described below with reference to FIGS.

FIG. 1 shows the configuration of a programmable controller using two processors.

The programmable controller of this embodiment comprises a main processor 1, a sub processor 2, a memory 3, and buses 4a and 4b.

The main processor 1 and the sub processor 2 are connected by a bus 4a, and the main processor 1 and the memory 3 are connected by a bus 4b.

Two interrupt signals IRQ1 and IRQ2 are connected from the main processor 1 to the sub processor 2.

The main processor 1 includes an arithmetic circuit 11, a first register 12a, a second internal register 12b, and a table 1.
3, arbitration circuit 14 and the like.

The output of the first internal register 12a is IRQ1.
The output of the second internal register 12b is connected to IRQ2.

The table 13 stores parameters necessary for the sub processor 2 to execute the application instruction macro.

The main processor 1 executes the basic instructions of the ladder such as contacts and coils, and the first register 12a and the second register 12a.
First interrupt signal IRQ1 output from register 12b
And an interrupt to the sub-processor 2 is executed by the second interrupt signal IRQ2.

The sub processor 2 executes the application instruction of the ladder.

The memory 3 stores a user program, a system program, and I / O data.

The use of the programmable controller will be described.

The main processor 1 executes basic instructions. If there is an application instruction macro, the sub-processor 2 executes it. Therefore, the parameters necessary for the execution of the sub-processor 2 are stored in the table 13. Run the macro. Specifically, the start address of the application instruction macro, the start address of I / O data, and the like are stored.

The arbitration circuit 14 arbitrates access from the main processor 1 to the memory 3 and access from the sub processor 2 to the memory 3.

Here, the method of transferring the processing between the processors will be described in detail with reference to FIGS. 2, 3, and 8.

FIG. 8 shows a part of the ladder program programmed by the user using a dedicated input device, which is the same as the conventional one. This is the main processor 1
Is converted into an executable instruction format and stored in the user program area shown in FIG. Here, the application instruction 1 and the application instruction 2 are converted into the form of a subroutine call. However, since the application instruction 1 is an instruction for reflecting the operation result on X1, it is included in CALLX (an instruction for reflecting the operation result on X1). The application instruction 2 is converted into CALLY (instruction that does not reflect the operation result in X1) because it does not reflect the operation result anywhere.

In the present embodiment, the plurality of types of specific instructions are CALLX (instruction for reflecting the operation result in X1) and CALLY (instruction for not reflecting the operation result in X1).
There are types.

When the main processor 1 is activated, it starts executing from the beginning of the user program. Step n, n +
1, n + 2 is a contact and coil instruction, so the main processor 1
To run. Next, since step n + 3 is the CALLX instruction, "1" is written in the first internal register 12a. As a result, the output of the first internal register 12a becomes "1" from the next cycle, and the interrupt signal IRQ is sent to the sub processor 2.
1 is output, and the main processor 1 enters the WAIT state.

When the sub processor 2 is interrupted by IRQ1, it reads the parameters necessary for executing the application instruction from the table 13 and executes the application instruction 1 macro.

As described above, while the operation of the main processor 1 is stopped while the IRQ1 is being output, the access from the sub-processor 2 to the memory 3 is occupied.

When the sub-processor 2 finishes executing the application instruction 1 macro, writing "0" to the 1 internal register 12a of the main processor 1 releases the WAIT of the main processor 1 and executes the next step.

Since step n + 4 is a CALLY instruction,
"1" is written to the second internal register 12b when executing the instruction. As a result, from the next cycle, the second internal register 1
The output of 2b becomes "1", an interrupt signal IRQ2 is output to the sub processor 2, and the main processor 1 enters the WAIT state.

On the other hand, when the sub-processor 2 is interrupted by the IRQ 2, the sub-processor 2 first writes "0" in the second internal register 12b of the main processor 1, and releases the WAIT. After that, the table 13 is read and the application instruction 2 macro is executed in the same manner as the interrupt processing by the IRQ1.

Here, WAIT is released and step n +
Contention of access to the memory 3 occurs between the main processor 1 executing the program 5 and the sub-processor 2 executing the application instruction 2 macro. This is arbitrated by the arbitration circuit 14 by appropriate means.

As described above, according to the present embodiment, the secondary processor 2
The processing result of the application instruction macro processed by the main processor 1
When it is not necessary to reflect the above in the above, the main processor 1 and the sub processor 2 operate in parallel, and therefore the processing time of the entire user program can be shortened.

The main processor 1 outputs only one interrupt signal, the logical sum of the first internal register 12a and the second internal register 12b is output, and the sub-processor 2 passes the processing by the method of analyzing the interrupt factor. It is also possible to determine the scheme.

Also, the first register 12a and the second internal register 12b do not output as interrupt signals, and the sub-processor 2 can always monitor these registers to recognize a request for processing transfer.

Next, a second embodiment of the main processor and programmable controller of the present invention will be described with reference to FIGS. 4 to 6 using flow language as an example.

FIG. 4 shows the configuration of a programmable controller using a main processor and two sub processors.

The programmable controller includes a main processor 1, a first sub-processor 2a, and a second sub-processor 2.
b, memory 3, buses 4a, 4b, 4c and the like.

The main processor 1, the first sub-processor 2a and the second sub-processor 2b are connected by buses 4a and 4b,
The main processor 1 and the memory 3 are connected by a bus 4c.

The IRQ1 is transmitted to the first sub-processor 2a by an IR
Q2 is connected to each of the second sub-processors 2b.

FIG. 5 shows an outline of a flow language executable by the programmable controller. Here, processing 2 (processing 3), processing 4 (processing 5), and processing 6 (processing 7) can be executed in parallel. Therefore, when this flow language is converted into an instruction form that can be executed by each processor and stored in the user program, processing 2 and processing 3, processing 4 and processing 5, processing 6 and processing 7 are scheduled to the respective processors. It is possible to do.

The processing 1, processing 6, processing 7, and processing 8 of the flow language are executed by the main processor 1, processing 2, and processing 3 by the first sub processor 2a, and processing 4, and processing 5 by the second sub processor 2b. FIG. 6 shows an outline of the user program scheduled and stored in the user program area in the memory 3.

When activated by the user, the main processor 1 starts execution from the beginning of the user program, and first executes processing 1. Next, in order to execute the processing 2, the processing 4, and the processing 6 in parallel, it is necessary to pass the processing to the first sub-processor 2a and the second sub-processor 2b. Here, CA
In order to execute the LLX instruction (instruction for the first sub-processor 2a), "1" is written in the first internal register 12a and IRQ1 is output to let the first sub-processor 2a execute the processing 2 and the processing 3. When the first sub-processor 2a accepts the interrupt, it first sets "0" in the first internal register 12a.
Is written, the WEIT of the main processor 1 is released, and the processing 2 and the processing 3 are executed.

When the WAIT is released, the main processor 1 executes a CALLY instruction (an instruction for the second sub-processor 2b), writes "1" in the second internal register 12b, and outputs an IRQ2.

In this embodiment, the plurality of types of specific instructions include a CALLX instruction (instruction for the first sub-processor 2a) and a CALLY instruction (instruction for the second sub-processor 2b), and generally, the specific instruction type Are the number of the sub processors 2a, 2b,...

When the second sub-processor 2b receives the interrupt, it first writes "0" in the second internal register 12b to release the WAIT of the main processor 1 and executes the processing 4 and the processing 5.

When the WAIT is released, the main processor 1 executes processing 6 and processing 7. After that, the process waits until the first sub-processor 2a and the second sub-processor 2b complete their respective processes in the synchronous process, and the post-termination process 8 is executed.

As described above, according to the present embodiment, the flow language type user program is scheduled and operated in advance in a processing unit which can be executed in parallel by each processor, so that the overall processing time can be reduced. However, although not specifically stated, the arbitration in the case where the access conflict between the first sub-processor 2a and the second sub-processor 2b with respect to the bus 4a occurs is the first sub-processor 2a and the second sub-processor 2b.
Just go between them.

[0071]

According to the present invention, the ladder language and the flow language can be used, and when the sequence operation is performed by a plurality of processors, each processor can operate in parallel, so that the entire user program can be operated. Execution time can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of an outline of a program after ladder language conversion used in the present invention.

FIG. 3 is an explanatory diagram of an example of operation timing according to the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of an example of a program in a flow language used in the present invention.

FIG. 6 is an explanatory diagram of an example of an outline of a program after flow language conversion used in the present invention.

FIG. 7 is an explanatory diagram of a configuration of a conventional system.

FIG. 8 shows an example of a program in a ladder language.

FIG. 9 is an explanatory diagram of an outline of a program after conversion of a conventional ladder language.

FIG. 10 is an explanatory diagram of operation timing of a conventional system.

[Explanation of symbols]

 1 Main Processor 11 Arithmetic Circuit 12, 12a, 12b Internal Register 13 Table 14 Arbitration Circuit 2, 2a, 2b Sub Processor 3 Memory 4a, 4b, 4c Bus

 ───────────────────────────────────────────────────の Continuing from the front page (72) Inventor Makoto Ogura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. Program and I / O created by a user
A main processor used in a programmable controller that is composed of a memory that stores data, a main processor that starts an operation when activated by a user, and a sub processor that executes a sequence operation by an interrupt from the main processor. When executing a specific instruction of a kind, a register of two or more to which a specific value is written, a table for passing data between the main processor and the sub processor, and access to memory from the main processor and the sub processor A main processor for a programmable controller, which comprises: 2. Program and I / O created by a user
In a programmable controller including a memory for storing data, a main processor that starts an operation upon activation by a user, and a sub-processor that executes a sequence operation in response to an interrupt from the main processor, a main processor includes a plurality of types of main processors. When executing a specific instruction, two or more registers to which a specific value is written, a table for passing data between the main processor and the sub processor, and arbitration of memory access from the main processor and the sub processor. And a means for performing the programmable controller. 3. The main processor or the programmable controller according to claim 1, wherein a language to be used is a ladder language. 4. The main processor according to claim 1 or 3, or the programmable controller according to claim 2 or 3, wherein the number of sub-processors is 1, the number of interrupts is 2,
The main processor or programmable controller is characterized in that the number of registers is two. 5. The main processor according to claim 1, or the programmable controller according to claim 2, wherein the language used is a flow language. 6. The main processor according to claim 1 or 5, or the programmable controller according to claim 2 or 5, wherein the number of sub-processors, the number of interrupts, and the number of registers are all the same and are two or more. Characteristic main processor or programmable controller. 7. The main processor or the programmable controller according to claim 1, wherein a sub processor can read or write a plurality of registers included in the main processor. Main processor or programmable controller.