JPS62196755A - Data processing method - Google Patents

Data processing method

Info

Publication number
JPS62196755A
JPS62196755A JP61037297A JP3729786A JPS62196755A JP S62196755 A JPS62196755 A JP S62196755A JP 61037297 A JP61037297 A JP 61037297A JP 3729786 A JP3729786 A JP 3729786A JP S62196755 A JPS62196755 A JP S62196755A
Authority
JP
Japan
Prior art keywords
input
instruction
output device
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61037297A
Other languages
Japanese (ja)
Inventor
Akira Kato
明 加藤
Hiromi Kawabata
川畑　広実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61037297A priority Critical patent/JPS62196755A/en
Publication of JPS62196755A publication Critical patent/JPS62196755A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To prevent an overload of a central processor, and to improve the throughput of the whole system by processing separately input and output instructions by each input/output device controlling circuit. CONSTITUTION:Each input/output device controlling circuit C0-Cn receives an instruction which has been outputted onto a processor bus 2 from a main storage device 3, executes automatically its instruction in case of the instruction related to its own input/output device, and executes nothing in case it is not related to its own input/output device. The input/output device controlling circuits C0-Cn bring the next instruction to an access to the main storage device 3, when an execution of the instruction of its own device is ended, and end its operation by outputting an instruction onto the processor bus 2. Each input/output device controlling circuit C0-Cn receives a discriminating signal of instruction/data from a central processor 4, and in case it is an instruction, information which has been outputted onto the processor bus 2 is fetched as the instruction. As for an operation of the whole system, the central processor 4 and one of the input/output device controlling circuits C0-Cn are operated at every instruction, and the central processor 4 manages a state of the system, in case its own device is in a dead state against the instruction.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデータ処理方法に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a data processing method.

〔従来の技術〕[Conventional technology]

従来のデータ処理システムは第３図に示すように構成さ
れていた。第３図において、１は中央処理装置、２はプ
ロセッサバス、３は主記憶装置、ＡＯ〜Ａｎは入出力装
置、ＢＯ〜Ｂｎは入出力装置制御回路である。A conventional data processing system was configured as shown in FIG. In FIG. 3, 1 is a central processing unit, 2 is a processor bus, 3 is a main storage device, AO to An are input/output devices, and BO to Bn are input/output device control circuits.

中央処理装置１は、プロセッサバス２に接続されている
主記憶装置３．入出力装置ＡＯ〜Ａｎ等のシステム全体
の管理と主記憶装置３から取り出された命令を処理実行
し、命令の内容により主記憶装置３や入出力装置ＡＯ〜
７１．ｎをアクセスする。The central processing unit 1 includes a main memory 3 . connected to a processor bus 2 . Management of the entire system such as input/output devices AO to An, processing and execution of instructions retrieved from the main storage device 3, and depending on the content of the instructions, the main storage device 3 and input/output devices AO to
71. Access n.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のデータ処理方法は、中央処理装置１がシ
ステムの管理および命令の処理実行を一括して行なう方
法となっている。そのため、中央処理装置１が入出力装
置ＡＯ〜Ａｎを用いる命令を実行させるためには、まず
、中央処理装置１は主記憶装置３に対してアクセスを行
ない、命令を処理し、次に入出力装置ＡＯ％Ａｎに対し
て起動をかけ、その後、入出力装置ＡＯ〜Ａｎからの終
了報告を受は取り処理を終了させる。この間に、中央処
理装置１は、システム内の他装置からの割込み等の受付
は処理などのシステム全体の制御および管理も行なわな
ければならない。The conventional data processing method described above is a method in which the central processing unit 1 manages the system and executes command processing all at once. Therefore, in order for the central processing unit 1 to execute an instruction using the input/output devices AO to An, the central processing unit 1 first accesses the main storage device 3, processes the instruction, and then input/output devices AO to An. The device AO%An is activated, and then completion reports are received from the input/output devices AO to An and the processing is terminated. During this time, the central processing unit 1 must also control and manage the entire system, such as accepting and processing interrupts from other devices within the system.

このように、命令実行中の割込み処理等を中央処理装置
１がすべて行なわなければならないため、割込み処理等
の処理が多くなるとシステム全体の処理能力が低下する
という欠点があった。As described above, since the central processing unit 1 has to perform all interrupt processing during instruction execution, there is a drawback that the processing capacity of the entire system decreases when the number of interrupt processing and other processing increases.

ｃ問題点を解決するための手段〕 このような欠点を除去するために本発明は、中央処理装
置は処理システム全体の管理および入出力装置制御回路
を用いない内部演算処理等の命令の処理を行ない、各入
出力装置制御回路はプロセッサバス上の情報を中央処理
装置からの命令／データ信号より判定し、入出力命令以
外は中央処理装置が処理し、入出力命令でかつ自装置に
対する命令である場合には該当する入出力装置制御回路
が自動的に処理し、入出力命令終了時には入出力命令を
処理した中央処理装置又は入出力装置制御回路が次命令
をアクセスするようにしたものである。Means for Solving Problem c] In order to eliminate such drawbacks, the present invention provides a system in which the central processing unit manages the entire processing system and processes instructions such as internal arithmetic processing without using the input/output device control circuit. Each input/output device control circuit determines the information on the processor bus based on the command/data signal from the central processing unit, and the central processing unit processes all but the input/output commands. In some cases, the corresponding input/output device control circuit automatically processes the instruction, and when the input/output instruction is completed, the central processing unit or input/output device control circuit that processed the input/output instruction accesses the next instruction. .

〔作用〕[Effect]

本発明においては、入出力命令は各入出力装置制御回路
側に処理される。In the present invention, input/output commands are processed by each input/output device control circuit.

〔実施例〕〔Example〕

本発明に係わるデータ処理方法の一実施例が適用される
データ処理システムを第１図に示す。プロセッサバス２
には、中央処理装置４と主記憶装置３そして入出力装置
制御回路ＣＯ〜Ｃｎを介して入出力装置ＡＯ−Ａｎが接
続されている。また、中央処理装置４と入出力装置制御
回路ＣＯ〜Ｃｎは中央処理装置アクセスバス５により接
続されている。FIG. 1 shows a data processing system to which an embodiment of the data processing method according to the present invention is applied. processor bus 2
The input/output devices AO-An are connected to the central processing unit 4, the main storage device 3, and the input/output device control circuits CO-Cn. Further, the central processing unit 4 and the input/output device control circuits CO to Cn are connected by a central processing unit access bus 5.

各入出力装置制御回路ＣＱ　−Ｃｎは、主記憶装置３か
らプロセッサバス２上に出された命令を受は取り、日入
出力装置に関する命令であった場合には自動的にその命
令を実行し、日入出力装置に関しない場合は何もしない
。入出力装置制御回路Ｃ（１”ｃｎは、自装置の命令の
実行が終了する際、主記憶装置３に対して次命令をアク
セスし、プロセッサハス２上に命令を出させてその動作
を終了させる。各入出力装置制御回路ＣＯ〜Ｃｎは、中
央処理装置４からの命令／データの判別信号を受け、命
令であった場合には、プロセッサバス２上に出されてい
る情報を命令として取り込む。Each input/output device control circuit CQ-Cn receives an instruction issued from the main storage device 3 onto the processor bus 2, and automatically executes the instruction if the instruction is related to an input/output device. , do nothing if it is not related to the input/output device. When the input/output device control circuit C (1"cn finishes executing the instruction of its own device), it accesses the next instruction from the main storage device 3, issues the instruction to the processor hash 2, and finishes the operation. Each input/output device control circuit CO to Cn receives an instruction/data determination signal from the central processing unit 4, and if it is an instruction, takes in the information issued on the processor bus 2 as an instruction. .

中央処理装置４は、システム全体の管理および主記憶装
置３との演算命令を行ない、プロセッサバス２上の情報
が命令かデータかを各入出力装置制御回路Ｃ０−Ｃｎに
通知する。The central processing unit 4 manages the entire system and performs arithmetic instructions with the main storage device 3, and notifies each input/output device control circuit C0-Cn whether the information on the processor bus 2 is an instruction or data.

また、入出力装置制御回路ＣＯ〜Ｃｎは、前命令での結
果を用いる場合、中央処理装置アクセスバス５を介して
そのデータを中央処理装置４内のレジスタより受は取り
、命令終了時、中央処理装置アクセスバス５を介して結
果を中央処理装置４内のレジスタへ書き込む。In addition, when using the result of the previous instruction, the input/output device control circuits CO to Cn receive the data from a register in the central processing unit 4 via the central processing unit access bus 5, and when the instruction ends, the The result is written to a register within the central processing unit 4 via the processing unit access bus 5.

システム全体の動作としては、命令ごとに中央処理装置
４や入出力装置制御回路ＣＯ％　Ｃｎのうちの１つが動
作し、中央処理装置４は、自装置が命令に対して空状態
の時、システムの状態を管理している。As for the operation of the entire system, the central processing unit 4 or one of the input/output device control circuits CO%Cn operates for each command. is managing the status of.

次に命令の流れの例を第２図に示す。第２図において、
命令番号“■”、“■”および“■”の命令は中央処理
装置４関連の命令であり、命令番号“■”の命令は入出
力装置制御回路ＣＯ関連の命令、命令番号“■”の命令
は入出力装置制御回路０２関連の命令、命令番号“■”
の命令入出力装置制御回路Ｃｎ関連の命令である。また
、期間６１〜６６は中央処理装置４または各入出力装置
制御回路が動作中の期間を示し、時点７１〜７６は中央
処理装置４または各入出力装置制御回路が次命令アクセ
スを行なう時点を示し、期間８１〜８７は命令／データ
信号がプロセッサバス２上に在る期間を示す。さらに、
鎖線１００は中央処理装置４がシステム管理動作中であ
ることを示し、破線２００は各入出力装置制御回路が空
状態であることを示す。Next, an example of the flow of instructions is shown in FIG. In Figure 2,
The instructions with instruction numbers "■", "■", and "■" are instructions related to the central processing unit 4, and the instructions with instruction number "■" are instructions related to the input/output device control circuit CO, and the instructions with instruction number "■" are related to the input/output device control circuit CO. The command is a command related to input/output device control circuit 02, command number “■”
This is a command related to the command input/output device control circuit Cn. Further, periods 61 to 66 indicate the periods during which the central processing unit 4 or each input/output device control circuit is in operation, and points 71 to 76 indicate the points in time when the central processing unit 4 or each input/output device control circuit accesses the next instruction. , and periods 81 to 87 indicate the period during which the instruction/data signal is on the processor bus 2. moreover,
A dashed line 100 indicates that the central processing unit 4 is in system management operation, and a broken line 200 indicates that each input/output device control circuit is in an empty state.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入出力命令を各入出力装
置制御回路側に処理することにより、中央処理装置の過
負荷を防ぎ、これにより、システム全体の処理能力を向
上させる効果がある。As described above, the present invention has the effect of preventing overload of the central processing unit by processing input/output commands to each input/output device control circuit, thereby improving the processing capacity of the entire system.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係わるデータ処理方法の一実施例が適
用されるデータ処理システムの系統図、第２図は第１図
のデータ処理システムにおける中央処理装置および入出
力装置制御回路の動作を説明するためのタイムチャート
、第３図は従来のデータ処理方法が適用されるデータ処
理システムの系統図である。 ２・・・・プロセッサバス、３・・・・主記憶装置、４
・・・・中央処理装置、５・・・・中央処理装置アクセ
スバス、ＡＯ〜Ａｎ・・・・入出力装置、Ｃ０−Ｃｎ・
・・・入出力装置制御回路。FIG. 1 is a system diagram of a data processing system to which an embodiment of the data processing method according to the present invention is applied, and FIG. 2 shows the operation of the central processing unit and input/output device control circuit in the data processing system of FIG. A time chart for explanation and FIG. 3 is a system diagram of a data processing system to which a conventional data processing method is applied. 2...Processor bus, 3...Main storage device, 4
... Central processing unit, 5... Central processing unit access bus, AO~An... Input/output device, C0-Cn.
...I/O device control circuit.

Claims (1)

【特許請求の範囲】[Claims] 中央処理装置と複数の入出力装置制御回路とを有する情
報処理システムにおけるデータ処理方法において、前記
中央処理装置は処理システム全体の管理および少なくと
も入出力装置制御回路を用いない内部演算処理の命令の
処理を行ない、前記各入出力装置制御回路はプロセッサ
バス上の情報を前記中央処理装置からの命令／データ信
号より判定し、入出力命令以外は前記中央処理装置が処
理し、入出力命令でかつ自装置に対する命令である場合
には該当する入出力装置制御回路が自動的に処理し、前
記入出力命令終了時には前記入出力命令を処理した前記
中央処理装置又は入出力装置制御回路が次命令をアクセ
スすることを特徴とするデータ処理方法。In a data processing method in an information processing system having a central processing unit and a plurality of input/output device control circuits, the central processing unit manages the entire processing system and at least processes instructions for internal arithmetic processing that does not use the input/output device control circuits. Each of the input/output device control circuits determines the information on the processor bus based on command/data signals from the central processing unit, and processes other than input/output commands by the central processing unit. If it is a command to a device, the corresponding input/output device control circuit automatically processes it, and when the input/output command ends, the central processing unit or input/output device control circuit that processed the input/output command accesses the next command. A data processing method characterized by:
JP61037297A 1986-02-24 1986-02-24 Data processing method Pending JPS62196755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61037297A JPS62196755A (en) 1986-02-24 1986-02-24 Data processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61037297A JPS62196755A (en) 1986-02-24 1986-02-24 Data processing method

Publications (1)

Publication Number Publication Date
JPS62196755A true JPS62196755A (en) 1987-08-31

Family

ID=12493767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61037297A Pending JPS62196755A (en) 1986-02-24 1986-02-24 Data processing method

Country Status (1)

Country Link
JP (1) JPS62196755A (en)

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