JPH0225931A - Microprogram control system - Google Patents

Abstract

PURPOSE:To suppress the deterioration of the execution control efficiency of a microinstruction and at the same time to reduce the bit width of a control word by selecting the execution unit which is used in each control field based on the contents of a field control part of the control word and instructing the executing cycle of each execution unit. CONSTITUTION:The execution units 8-10 which are used in the control field parts 5-7 are selected based on the contents of a field control part 3. At the same time, the executing cycles of the units 8-10 are instructed. Thus the units 8-10 are optionally selected for use in the parts 5-7 based on the contents of the part 3 and the executing cycles are instructed for the units 8-10. As a result, the executing control efficiency is improved for a microinstruction. In addition, the bit width of a control word can be reduced for the microinstruction since the parts 5-7 can be selected for application based on the contents of the part 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram control system, and in particular,
This invention relates to a microprogram control system that controls the processing of microinstructions in a plurality of execution cycles using an instruction control word read out from a control memory in one access unit.

[Conventional technology]

In a microprogram control type processing device, microinstructions stored in a control memory are read out one by one, and each instruction execution unit within the processing device is repeatedly operated based on the microinstructions. Since the operating speed of the processing device corresponds to this green-turning operation time, the repetitive operation is performed at high speed in order to increase the operating speed.

For this reason, in microprogram control type processing devices, the reading of microinstructions and the execution of instruction processing are made to operate independently, so that while a certain microinstruction is being executed, the next microinstruction to be executed is read out. By that,
Read control is performed to make the apparent microinstruction read time zero. However, if the access time of the memory used for control storage is slower than the operating time of the instruction execution unit, the readout time of the microinstruction is ostensibly longer than the execution time of the instruction execution unit. Therefore, there is a problem that an extra execution cycle time is required and the processing speed of instruction processing is slowed down.

As one method for solving this problem, a microprogram control method is known in which microinstructions for a plurality of execution cycles are simultaneously read from a control memory. According to this method, even if the read cycle of a microinstruction is longer than the execution cycle of one microinstruction, as long as one control memory access is possible in the execution cycle of multiple microinstructions, In execution, it is possible to prevent invalid cycles from occurring. However, the number of microinstructions to be read simultaneously is determined depending on the machine cycle, control memory access time, etc.

FIG. 4 is a time chart illustrating an example of a microprogram control method for simultaneously reading microinstructions for a plurality of execution cycles.

The time chart in FIG. 4 shows an example in which two microinstructions are read in one access unit and instruction processing is executed. Continuing with the explanation of the case where two microinstructions, which are consecutive execution units, are read simultaneously and the processing of the microinstructions is executed with reference to FIG. The set of microinstruction A and microinstruction B, which is the execution unit, is read from the control memory, and microinstruction A is executed in the third machine cycle.
Then, microinstruction B is executed in the next fourth machine cycle. At this time, the next two consecutive microinstructions C and 2 are read out, overlapping with the execution of microinstructions A and B.

Then, in the fifth machine cycle following the completion of the microinstruction B in the fourth machine cycle, the microinstruction C that has already been read is executed, and then the next microinstruction is executed. Also, at this time, the execution overlaps with the execution of microinstruction C and microinstruction.

The next two consecutive microinstructions E and F are read. In this way, each microinstruction can be executed successively, and invalid cycles on the instruction execution cycle can be eliminated. In such a method, it is necessary to simultaneously read two execution cycles worth of microinstructions from control memory in one access, so the bit width of the instruction control word increases, reducing the storage capacity of control memory and the control memory data. A problem arises in that the capacity of the register increases.

To solve this problem, for example, a specific field of a microinstruction can have a double meaning, and one of the fields can be used depending on the instruction data of other fields. Therefore, a microprogram control method with a reduced number of fields has been proposed. The central processing unit described in Japanese Unexamined Patent Publication No. 57-161940 is an example of such a microprogram control system. In this microprogram control central processing unit, a branch control field and an arithmetic control/branch address field are provided in the control word of a microinstruction, and when a branch is to be executed, an arithmetic control/branch address field is provided. Information in the address field is used as a branch address, and in cases other than one branch, it is used as calculation control information. This makes effective use of the control word of the microinstruction and reduces the bit width of the control memory.

[Problem to be solved by the invention]

By the way, in the above-mentioned microprogram control method, a branch control field and an arithmetic control/branch address field are provided in the control word of a microinstruction, and when a branch is to be made, the arithmetic control/branch address field is provided. The information in the branch address field is used as a branch address, and in cases other than branches, it is used as calculation control information. Therefore, the control word of the microinstruction can be effectively used, and the bit width of the control memory can be reduced.

However, in this method, the information in the arithmetic control/branch address field of the control word of one access unit microinstruction is also used as branch address information or arithmetic control information, so when branching is performed by microinstruction execution control, cannot perform arithmetic control, and similarly, when performing arithmetic control, it is not possible to perform branching execution control, which has the problem of reducing execution efficiency when executing microinstructions. .

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to minimize the decrease in execution efficiency of microinstruction execution control and to reduce the bit width of a microinstruction control word in a microprogram control system.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, in the present invention.

In a processing device that performs processing using a microprogram control method that reads a control word of a microinstruction stored in a control memory and controls the microinstruction, the control word that has a field control section and a plurality of control field sections is stored in the control memory. It is equipped with a control circuit that reads in one access unit and controls multiple execution cycles using a control word, and a plurality of execution units that can operate for each execution cycle. It is characterized in that the control field section selects the execution unit to be operated and also instructs the execution cycle of each execution unit.

[Effect]

According to the above means, it is possible to include a control circuit that controls a plurality of execution cycles using a control word read from the control memory in one access unit, and a plurality of execution units that can operate for each execution cycle. A control word of a microinstruction is provided with a field control section and a plurality of control field sections. The control field section is divided into, for example, one or more control fields that operate in the first execution cycle and one or more control fields that operate in the second execution cycle, and based on the contents of the field control section, An execution unit to be operated on each control field section is selected, and an execution cycle instruction for each execution unit is given.

As a result, when controlling the execution of microinstructions, the execution unit to be acted on in each control field part is arbitrarily selected based on the contents of the field control part, and the execution cycle instruction of the execution unit is given. Control can be performed efficiently. Further, since the control field section can be selectively used as the field control section depending on the contents, the bit width of the control word of the microinstruction can be reduced.

For example, the control field section contains branch control information when a predetermined specific field among the control fields operating in the second execution cycle branches according to an instruction from the field control section.

Control is performed to use it as branch address information, and if no branch is taken, control is performed to use it as a control field in the second execution cycle.

That is, in a preferred embodiment, a control circuit that controls execution cycles of two machine cycles using a control word read from a control memory in one access unit, and a plurality of execution units operable for each execution cycle are provided. A control word is provided with one field control section and a plurality of control field sections. The control field section includes one or more control fields that operate in a first execution cycle and a control field that operates in a first execution cycle.
The control field is divided into one or more control fields that operate in an execution cycle. Among the control fields operated in the second execution cycle, a predetermined specific field is controlled to be used as branch control information 9 branch address information when branching is performed according to an instruction from the field control unit. Further, if a branch is not taken, it is controlled to be used as a control field in the second execution cycle.

In this way, when a microinstruction does not involve a branch, the control field read from the control memory is operated on by the execution unit in the first execution cycle and the second execution cycle, respectively, and the current control memory address is set as the next address. The next value of is selected. Execution control is such that each execution unit is selected and processed through sequential processing, and the processing progresses.

If a branch is involved, the first execution cycle operates according to information in the control field for the first execution cycle, and
Branch control is performed based on branch control information and branch address information indicated by a specific field determined in the control field for the second execution cycle according to instructions from the field control unit. When a branch is established, the control memory is read from the address indicated by the 1-branch address information, and execution control is performed to continue the process. Furthermore, if the branch is not taken, the remaining fields that are not used for branch control information and branch address information among the control fields for the second execution cycle are operated by the execution unit in the second execution cycle.

Because such execution control operations are performed, when a branch is not taken, the control field is restricted in the second execution cycle, but when the first branch is taken, the control field is not restricted, which improves the execution efficiency of microinstruction execution control. Can be branched without degradation. This makes it possible to minimize the decrease in execution efficiency of microinstructions including one branch and reduce the bit width of the control word.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram of a processing device using a microprogram control method according to an embodiment of the present invention. In FIG. 1, 1 is a control storage section, 2 is a control storage data register, 3 is a field control circuit section, 4 is an execution cycle control section, and 5 to 7 are selectors. Reference numerals 8 to 10 are execution units that execute microinstructions of each field, 11 to 12 are switchers, and 13 is a branch control unit. Further, 14 is a selector, 15 is a control storage address register, and 16 is an incrementer.

One control word, which is one access unit of the control storage section 1, is used by dividing each field in the control storage data register 2. That is, one X field which is a field control part, six control fields which are a control field part, that is, the CO field, FO field, and LO field of the microinstruction for the first execution cycle, and the second execution cycle It is divided into the C1 field, Fl field, and L1 field of the microinstruction for use. When the execution cycle is the first execution cycle, the control word read out in one access unit from the control storage unit 1 and latched in the control storage data register 2 is read out from the control storage data register 2 in accordance with an instruction from the execution cycle control unit 4. Field, FO field and LO field are selected by selectors 6.6.7 and sent to execution units 8, 9.10 for each field. Similarly, during the second execution cycle, the C1 field, Fl field, and LL field are selected by the selectors 5.6.7 and sent to the execution unit 8.9.10 according to instructions from the execution cycle control section 4, respectively.

When a microinstruction is processed sequentially without branching, the control memory address stored in the control memory address register 15 is sequentially incremented by the incrementer 16, and the next control is performed according to the control memory address in the control memory address register 15. A word is read from the control store 1.

When the microinstruction includes a branch, the field control circuit unit 3 operates according to the X field information of the control storage data register 2, and the information in the F1 field is converted into branch control information (T field) according to instructions from the field control circuit unit 3.
The signal is taken into the branch control unit 13 through the switch 11 as a signal. When a branch is established, the information in the L1 field is used as a branch address (B field) by the switch 12. The data is taken into the control storage address register 15 via the selector 14. As a result, the read address data of the next control word becomes the branch address of the B field, and the control word of the control storage section 1 is read out using this address data, and branching is performed. If the branch is not taken, the branch address in the B field is not taken into the control storage address register 15, and the next incremented address data is taken into the control storage address register 15 from the incrementer 16 via the selector 14. In this case, the second execution cycle operates next, and only the 01 field of the control fields for the second execution cycle is sent to the execution unit 8.

FIG. 2 is a diagram showing an example of a control word for explaining microinstruction execution control accompanied by branch control. Also,
FIGS. 3a and 3b are time charts for explaining microinstruction execution control accompanied by branch control.

As shown in FIG. 2, the control word of the microinstruction is stored at addresses NO to N2 . N5-N6. BO~
B1, and with these control words,
An example of controlling execution of microinstruction processing will be described.

See Figure 3a. In machine cycles 1 and 2,
A read operation from the control memory unit 1 is performed according to the address data NO of the control memory address register 15, and execution control of the read control word COFOLOCIFILI is performed in machine cycles 3 to 4. In the machine cycle 3, the execution cycle control unit 4 is set to logic “0”.
It outputs a signal to indicate that machine cycle 3 is the first execution cycle, and controls selectors 5, 6.7 to execute the first execution cycle.
The control field C0FOLO of the execution cycle is executed by execution units 8, 9.10. Next machine cycle 4
In this case, the execution cycle control unit 4 outputs a logic 1'1'' signal to indicate that the machine cycle 4 is the second execution cycle, so each control of the second execution cycle is controlled by the selectors 5, 6.7. Field CI F I L 1 is executed in execution units 8, 9 and 10. In machine cycles 3 and 4, at this time, the address data in the control storage address register 15 is updated to address N1, and this address data N1 , a read operation of the next control word from the control storage unit 1 is performed.The second control word C2F2L2C3TOBO read in this read operation
Execution control is performed in the next machine cycles 5 and 6.

Since the second control word C2F2L2C3TOBO is indicated to contain a branch by the logic 111'1 of the X field indicating field control,
In machine cycles 5 and 6, the field control circuit unit 3 outputs a logic 1 (172) signal to control the execution of the second control word C2F2L2C3TOBO including one branch.

In machine cycle 5, execution cycle control section 4 outputs a logic "0" signal, indicating that machine cycle 5 is the first execution cycle. In this case, the selectors 5, 6.7 are controlled, and the execution control of the control field C2F2L2 of the first execution cycle is controlled by the execution units 8, 9.
10. On the other hand, at this time, machine cycle 5
indicates that it is the first execution cycle, but the field control circuit unit 3 outputs a logic 111 IT double signal, and the information in the control field To of the second execution cycle is used as information to perform branch control. The signal is applied to the branch control section 13 via the switch 11. Then, in this machine cycle 5, the branch control section 13 operates.

In this case, since the branch is not taken, the control storage address register 15 is updated to address N2, and this address data N2 causes the next control word to be read from the control storage section. In the next machine cycle 6, the execution cycle control unit 4 outputs a logic it 1 + signal, indicating that the machine cycle 6 is the second execution cycle.

The selectors 5 and 6.7 are controlled, but in this case, the information of the control field of the second execution cycle is not added to the selector 6.7, and only the execution unit 8 executes the control field C3. At the end of machine cycle 6, control storage address register 15 has already been updated to address N2 as described above, and with this address data N2.

The next control word C4F4L4C5F5L5 is read from the control memory 1 (not shown).

In the next machine cycle 7.8, machine cycle 3
, 4 will be performed.

Next, in machine cycles io and ii, a case in which a branch is established by controlling the execution of a microinstruction using a control word that includes a branch, will be described with reference to FIG. 3b. , a read operation from the control storage unit 1 is performed, and the read control word C
Execution control of 6F6L6C7TIBO takes place in machine cycle 12.13. In machine cycle 12, execution cycle control unit 4 outputs a logic xi Ohp times signal, indicating that machine cycle 12 is the first execution cycle. In this case, selectors 5, 6.7
is controlled, and the control field C6F of the first execution cycle
Execution control of 6L6 is performed by execution units 8, 9.10. At this time, the machine cycle 12 is indicating that it is the first execution cycle, but the field control circuit section 3 is outputting a logic 111 II times signal, and the information in the control field T1 of the second execution cycle is It is added to the branch control unit 13 via the switch 11 as information for controlling. Then, in machine cycle 12, branch control unit 1
When the operation of step 3 is performed and it is determined that one branch is established in this case, the operation of the branch control unit 13 causes the switch 12. Via the selector 14, the control storage address register 15 has the following information:
The address data of the information from the control field (Ll) of the second execution cycle is read and updated to address BO. This address data BO causes the next control word to be read from the control storage section 1.

In this case, in the next machine cycle 13, the execution cycle control section 4 outputs a logic 111 I+ times signal to indicate that the machine cycle 6 is the second execution cycle, but the control field to be performed in this second execution cycle is The execution control is branch control, and since the processing has already been completed, the control field C7 of the second execution cycle is sent via the selector 5.
is added to the execution unit 8, but the execution of this control field C7 is disabled.

At the end of the machine cycle 13, the control storage address register 15 has already been updated to the address BO of the branch destination address as described above, and this address data BO
The primary control word Cl0FLOLIOCIIFI
In the next machine cycle 14.15, machine cycle 3,
The same execution control operation as in step 4 will be performed.

In this way, in the microprogram control method of this embodiment, arithmetic control can be performed even when branching is performed by microinstruction execution control, and execution control that branches can also be performed when performing arithmetic control. Therefore, the efficiency of executing microinstructions does not decrease. Further, under the control of the field control circuit section 3, the F1 field is used as the T field of branch control information, and L L
Since the field is configured to be used also as the B field of branch address information, the width of the control word can be reduced.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, when performing microinstruction execution control, a decrease in execution efficiency of microinstruction execution control including branching can be minimized, and the bit width of a control storage word can be reduced. This has the effect that the system can be constructed economically.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a processing device using a microprogram control system according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a control word for explaining microinstruction execution control with one-branch control. , FIGS. 3a and 3b are time charts for explaining execution control of microinstructions accompanied by branch control, and FIG. 4 is a diagram of a conventional microprogram control method for simultaneously reading microinstructions for multiple execution cycles. It is a time chart explaining an example. In the figure, 1... Control storage unit, 2... Control storage data register, 3... Field control circuit unit, 4... Execution cycle control unit, 5-7, 14... Selector, 8- 1
0... Execution unit, 11-12... Switching device, 13
. . . Branch control unit, 15 . . . Control storage address register, 16 . . . Incrementer. Shin 1 time

Claims (1)

[Scope of Claims] 1. In a processing device that performs processing by a microprogram control method that reads control words of microinstructions stored in a control memory and controls the microinstructions, a field control unit and a plurality of control field units are provided. It is equipped with a control circuit that reads a control word provided with a control word from a control memory in one access unit and controls a plurality of execution cycles using the control word, and a plurality of execution units that can operate for each execution cycle. A microprogram control method characterized in that an execution unit to be operated on each control field section is selected based on the contents of the section, and an execution cycle instruction for each execution unit is given. 2. Equipped with a control circuit that controls two machine cycles of execution by a control word read from the control memory in one access unit, and a plurality of execution units that can operate for each execution cycle, with one field in the control word. A control section and a plurality of control field sections are provided, and the control field section is divided into one or more control fields that operate in a first execution cycle and one or more control fields that operate in a second execution cycle. Among the control fields that operate in two execution cycles, a predetermined specific field is used as branch control information and branch address information when branching is performed according to instructions from the field control unit, and when not branching. , a microprogram control method characterized by performing control used as a control field in a second execution cycle.