JPH0766032B2 - Test system - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a test system, and more particularly to a test system configured to perform a test on a test target using a plurality of test modules having a predetermined test function, and (EN) A new test system in which operating conditions can be set by using common condition setting means, changes and additions of test objects can be easily dealt with, and a predetermined test can be executed in a relatively short time. It is a thing.

[Prior art]

An analog LSI test system is one type of test system. Generally, in such a system, the operating condition of each test module is set according to the LSI to be tested, and a predetermined test operation is executed.

[Problems to be Solved by the Invention]

By the way, setting the operating conditions in the conventional system is
This must be done while reading the instruction manual that describes the functions and attributes of each test module, which requires a considerable number of man-hours for setting operating conditions. In addition, it is not possible to easily change or add a test object because not only the test module but also the program of the entire system must be changed. On the other hand, in the test execution, the set operating conditions of each test module are stored in advance in a common control unit, and the necessary setting data is sent to a predetermined test module each time. Such pre-processing requires a considerable amount of time, which is one of the factors that hinder the reduction of test execution time. The present invention has solved these conventional drawbacks, and the purpose thereof is to set the operating conditions of each test module by using a common condition setting means, and to easily change or add test objects. In addition, the present invention provides a new test system capable of executing a predetermined test in a relatively short time.

[Means for Solving the Problems]

According to the present invention, a plurality of test modules having a predetermined test function for an object to be tested are connected in parallel with a host processor via a system bus, and a plurality of sequence numbers are provided from the host processor to each test module prior to test execution. A series of data including control codes and parameters is downloaded, and in executing the test, the upper processor is a test system configured to send out a sequence number to each test module, and each test module is connected to a system bus. A bus interface connected to the bus interface, a random access memory connected to the bus interface, and a processor connected to the bus interface and the random access memory, and each test module is downloaded via the bus interface. Each sequence number of a series of data to be read is converted into an individual address by the processor for each test module and stored in each random access memory as a conversion table, and each sequence number is converted to the download data following each sequence number. The addresses are stored in respective conversion tables starting from the generated address. When executing the test, the upper processor sends out a sequence number to each test module via the system bus, and each test module is stored in the random access memory. It is characterized in that the address corresponding to each sequence number is read from the conversion table, the download data stored in the corresponding address portion of the random access memory is read, and a predetermined test operation is executed.

[Action]

Each test module has multiple sequence numbers, control codes, and
A series of data including parameters is downloaded. Each sequence number of this series of data is stored in the memory as a conversion table after being converted into an address in a code format that each test module can easily judge, and the control code and parameter following each sequence number are each sequence of the conversion table. It is stored following the area starting with the address corresponding to the number. At the time of test execution, the conversion table stored in this memory is directly accessed by the sequence number. That is, the start addresses of a plurality of data stored in the memory can be designated by using the sequence number as an external pointer. As a result, the time required for the conventional software search that does not use the conversion table can be reduced to zero.

【Example】

Hereinafter, a detailed description will be given with reference to the drawings. FIG. 1 is a block diagram showing a main part of one embodiment of the present invention, where SB is a system bus, TM is a test module, and BIF.
Is a bus interface, RAM is a random access memory, and CPU is a processor. For example, from the system bus SB to bus interface BIF
6-bit sequence number S ₁ added, processor CPU
For example, a 16-bit address S ₂ and an address switching signal S ₃ for switching the address to be added to the random access memory RAM to the system bus SB or the processor CPU are added. The 16-bit sequence number S ₁ or address S ₂ is added to the random access memory RAM from the bus interface BIF, and the detection signal S ₄ indicating the arrival of data from the system bus SB is added to the processor CPU. The random access memory RAM has a byte selection signal S ₅ for selecting upper 8 bits or lower 8 bits of the address in order to read a 16-bit address applied to the processor CPU from the random access memory RAM in 8-bit units.
Is added from the processor CPU. Then, the conversion address data S ₆ is exchanged in 8-bit units between the random access memory RAM and the processor CPU. The operation of the apparatus configured as described above will be described. First, prior to the execution of the test operation, a series of data including a plurality of sequence numbers S ₁ , control codes, and parameters is downloaded from a host processor (not shown) to each test module TM via the system bus SB. here,
The sequence number S ₁ indicates the order of the test, the control code indicates the contents of the process at the sequence number (for example, measurement condition setting, measurement, setting cancellation, etc.), and the parameter indicates, for example, specific condition setting. It represents a value. Each test module TM converts the sequence number S ₁ forming the series of data into an address S ₆ in a code format (for example, hexadecimal number) that the test module TM can easily determine by the processor CPU, and uses it as a conversion table in the random access memory RAM. To store. And each sequence number S
Downloaded data such as control codes and parameters following ₁ is stored in a portion beginning with an address corresponding to each sequence number of the conversion table stored in the random access memory RAM. Here, when storing the conversion address S ₆ and the download data in the random access memory RAM, the random access memory RAM
The address switching signal S ₃ is applied to the bus interface BIF so that the address to the processor CPU is applied. When the storage of the conversion address S ₆ and the download data in the random access memory RAM is completed in this way, the processor CPU sends an address switching signal to the bus interface BIF so that the address to the random access memory RAM is added from the bus interface BIF. Add S ₃ . When the sequence number S ₁ for test execution is sent from the upper processor to the system bus SB, the bus interface BIF of each test module TM applies the detection signal S ₄ indicating the arrival of data to the processor CPU. Each processor CPU sends the byte selection signal S ₅ to its random access memory
Add to RAM. As a result, the conversion address S ₆ corresponding to the sequence number S ₁ is directly read out from the conversion table stored in the random access memory RAM of each test module TM, and the conversion address S ₆ corresponding to the sequence number S ₁ is transferred to the processor CPU 8 bits at a time in accordance with the byte selection signal S _5. Read. Each test module T
The processor CPU of M thus reads the download data stored in the portion beginning with the corresponding address of the random access memory RAM according to the conversion address S ₆ read from the conversion table stored in the random access memory RAM in this way. , Execute a predetermined test operation. With such a configuration, the random access memory RAM of each test module TM can be directly accessed by the sequence number S ₁ to read the conversion address, so that the time required for the read is significantly larger than that when searching by software. Can be shortened to Especially, from 16-bit data to 8-bit processor CPU
Although a considerable amount of calculation time is required to search for bit data, such a structure can reduce the calculation time for search to zero. Further, at the time of test execution, it is only necessary to send out the sequence number from the upper processor CPU, and the test time can be further shortened. Further, according to such a configuration, when the test object is changed or added, the necessary operating condition of the test module TM may be changed individually by using, for example, the terminal, which can be easily dealt with. Specifically, the data of the conversion table stored in the memory of the corresponding test module TM is added, deleted or changed. For example, for a test module TM that did not respond because there was no parameter data etc. for the sequence number "100" at the time of download, add those data to the test module TM and add the sequence number to the beginning of those data. By associating with the address corresponding to "100", the operation by the sequence number "100" can be additionally executed. On the contrary, when deleting an operation with a certain sequence number in a certain test module TM, the data of the sequence number stored in the conversion table may be deleted, and when changing the operation with a certain sequence number in a certain test module TM, It suffices to change the sequence number data stored in the conversion table. This makes it possible to deal with different processing requests with the same sequence number and the same processing request with different sequence numbers.

【The invention's effect】

As described above, according to the present invention, it is possible to set operating conditions during operation of each test module in a relatively short time,
Easily adapt to changes and additions to test objects, and
A test system that uses multiple test modules that can execute tests in a short time can be realized, and it has a great practical effect as a test system for various test objects as well as LSI.

[Brief description of drawings]

The drawings are block diagrams showing an embodiment of the present invention. SB ... System bus, TM ... Test module, BIF ...
… Bus interface BIF, RAM …… Random access memory, CPU …… Processor.

Claims (1)

[Claims] 1. A plurality of test modules having a predetermined test function for a test object are connected in parallel with a host processor via a system bus, and a plurality of sequences from the host processor to each test module prior to test execution. A series of data including a number, a control code, and a parameter are downloaded, and the test processor is a test system configured to send out a sequence number to each test module in executing a test. A bus interface connected to the bus interface, a random access memory connected to the bus interface, and a processor connected to the bus interface and the random access memory are provided, and each test module is downloaded via the bus interface. Each sequence number of a series of data to be loaded is converted to an individual address by the processor for each test module and stored in each random access memory as a conversion table, and each sequence number is converted to the download data following each sequence number. The addresses are stored in respective conversion tables starting from the generated address. When executing the test, the upper processor sends out a sequence number to each test module via the system bus, and each test module is stored in the random access memory. A test characterized by reading an address corresponding to each sequence number from the conversion table, reading down-load data stored in the corresponding address portion of the random access memory, and executing a predetermined test operation. Stem.