JPS6070373A - Test system - Google Patents

Abstract

PURPOSE:To make it possible to simply conduct a predetermined test within a relatively short time so as to be capable of easily corresponding to the alteration or addition of an object to be tested, by using a common condition setting means in setting the operational condition of each module. CONSTITUTION:CPU applies an address change-over signal S3 to BIF so as to apply an address to RAM from a bus interface (BIF). When a sequence number S1 for conducting a test is sent to a sequence bus SB, BIF applies a detection signal S4 for displaying data arrival to CPU. CPU applies a bus selecting signal S5 to RAM and a conversion address S6 is directly read from RAM according to the sequence number S1 applied from SB through BIF and read by the processor CPU according to the bus selecting signal S5. CPU conducts predetermined test operation according to thus read conversion address. By this mechanism, a test can be conducted within a short time by using a plurality of test modules TM.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a destination system, in detail (↓, a test on a test object using a plurality of test modules having a predetermined destination machine OL). It relates to a test system configured to perform
How each module works! 1 can be easily set by using a common article 11 setting means, it can easily respond to the change of object 1 -)゜)) This provides a new destination system for execution-C.

One type of Death 1 System is the Analota 1-81 Death 1 System. Generally, in such a system (J,
The operating conditions 1!4 of each American 1-° system J-le are set according to the LSI to be used as the death J, and the predetermined death (-11 operation is executed. By the way, the slave)) 4 system-tsum is J3 The operating conditions ('1, 1 hit)
1 Attribute A 1 Doka Arrangement) Small 41'C While reading the explanation 〒1 Trap + J IL U % Ra - J - 1 I) Jft
Article f'l Set'tL t=1-number equivalent to required.

Also, last one against nine! When changing or adding things, you must change not only the destmodicor but also the jl-1 gram of the entire system (J, which cannot be done easily.On the other hand, for destmodicol?1, (Also, set the operating conditions of each desto module in advance in the common control unit (8
It is configured in such a way that it sends out the setting data to the Lumi constant module every time it is loaded.This kind of preprocessing takes a considerable amount of time, and it takes 7 strokes. This has become a hindrance to reducing the time to one hour.

Kokumei solved these conventional shortcomings, and in the previous system, each destomodicoll had -]2 - A series of data including multiple sequence numbers, control codes, and parameters to be coded. When executing the process, the memory of 7 joules is accessed by the sequence number.
The 14th characteristic is that (5Y-(each module, :1-le is driven and the C predetermined 17th stroke is set to row 5J,) to the J dress (sent from the C meter). be..

IS4 card, explain the C correction fence using drawings.

Drawings (J, Brochure showing essential parts of an embodiment of the present invention)
(Le) is SB (Yo system path, l-M is test module, BIF is path interface, RAM G
, 1 random access memory, and the CPU is a block.

For example, the 16-bit sheet number @S1 of 16 bits is added to the bus interface BIF from the system bus SB, and the 16-bit address S2 and the address added to the random access memory RAM are added from the processor CP jJ to the bus interface BIF. An address switching signal S3 is applied to switch the address to the system path SB or the processor CPU. From the bus interface BIF to the random access memory RAM, these 1G bits 1~ sequence? The system bus 3 B1. A detection signal S,1 indicating the arrival of data such as s r is applied.

t to random access memory R△11 Random access memory RA lvl to b] -11? 8 bits 1- +4 for 16 hits 1 to 1-areas added to the tree CPU
The high 1 to selection signal S5 selects the second 8th bit to the tenth 8 bits of the address in order to read it to the i position C'.
It is added from the CPU. Then, between the random access memory I'<A fvl and the CPU, the converted address data S6 is exchanged in 8-bit units in 4 rows 4'.

I will explain the operation of the defense that is done in this case.

, 1.2J゛, j-λ1 ~ Prior to the actual operation 1j, the -C tenth position block 1 is set via the system bus SB (V not shown)
A series of data including a plurality of sequence numbers, control I+-1, and parameters are downloaded to each iStore from I+ to I-1. Here, the sequence number indicates the order of the dest, and the control code indicates the content of the process (for example, measurement thread (q setting, measurement, setting cancellation, etc.) in the sequence number. For example, the parameters are 3, each of the 5 lines 1, and the parameters are 3 and 5, respectively.
The destination module determines the sequence number from the pond node and converts it to a 7-trace format of 1-1 to 1-1. Stored in Sumeshiri RAM.

As a result, it is possible to handle requests for the same processing due to different sheet number m with the same sequence number and requests for the same processing due to different sheet number m.Conversion address to random access memory RA~1 When storing S6, the bus interface BI is used so that the address to the random access memory RAM is added from the processor CPtJ.
Add address switching signal S3 to F. In this way, the translation address S6 to the random access memory RAM
When storage is completed, the CPU applies an address switching signal $3 to the bus interface BIF so that the address to the random access memory RAN4 is added from the path interface BIF.System bus SB When the sequence number S1 of the I (V) of the test actual I is sent, the Hass interface BIF
indicates the arrival of data and turns on the detection signal S4.
Add to P LJ. Processor reset c p u Ll, high I-selection signal Ss by random 7 [Z recommendation 1. J
IJI+ will be added to RA N-1. Then, the converted address S6 is sent from the random number 7 message RAM to the system bus S13 via the bus interface BiF according to the second synonym WfiQ31) (
C8 pin 1~ according to the selection signal S5
f [1 bit read by CPU. BLURRI-CPU reads this J, sea urchin C, and reads the binary address S.
Execute a predetermined test operation according to 6.

If J enters t!1 in this way, the sequence number can be used to directly transfer the module's random access memory [△M to j! and read the translation address. Compared to the case of retrieving with Ueno 2, the time required to retrieve C reading J) can be significantly shortened (
Wear. In particular, when analyzing 1GB of data required by an 8-bit high-performance CPU from 16 bits of data, a considerable amount of operating time is required. Search by composition J: Drips of eyes) 04
It is possible to set the interval to zero (when executing the 11th, 7th, and 7th strokes, the sequence number may be sent from the upper level CPU), making the 7th stroke even more difficult.
11 can be shortened. Also, according to the 4c depiction like this (
,■, -j -j -j -j -j -j -j -j -j -J -j -j - -j - - ( - - - j - It is possible to easily deal with changes or additions by simply changing the operation conditions + 1 of Sumy Mojikor using the terminal, for example. .

As described above, according to the present invention, the setting of the operating conditions 19 during the operation of each dest module can be easily performed in a relatively short time, and changes and additions to test objects can be easily accommodated.
Furthermore, it is possible to realize a test system using a plurality of dest modules that can be destabilized and executed in a short time, which has a great practical effect as a test system not only for LSIs but also for various types of objects.

[Brief explanation of drawings]

The drawing is a block diagram showing one embodiment of the present invention. S B... System bus, T M... Desto module, [31F... Bus interface, RAM.
... Random knock access memory, CP Ll...B[
Ruri.

Claims (1)

[Scope of Claims] In a test system designed to perform [death for one object] using a plurality of desujicols that irritate a predetermined test machine OL, each death I
・Mojikor (, 10th place) 1" sec to town low 1 ~ multiple nno 7th numbers, control ill,, J
-Do. -) Insect data occupying the Harameter -) + t sequence number -, G1-le judges] η I set up a memory to convert it to 11-res in the format and store it, - 'z
'su [・actual 1j11. 'iMILL
21-Response to C8
[Drive the seal (predetermined j strike 4-1) J, -
J and where and 1! Torimatatori <) Destosino/1
．． .