JPS5839646U - data processing equipment - Google Patents
data processing equipmentInfo
- Publication number
- JPS5839646U JPS5839646U JP13435481U JP13435481U JPS5839646U JP S5839646 U JPS5839646 U JP S5839646U JP 13435481 U JP13435481 U JP 13435481U JP 13435481 U JP13435481 U JP 13435481U JP S5839646 U JPS5839646 U JP S5839646U
- Authority
- JP
- Japan
- Prior art keywords
- microinstruction
- address
- specified
- data processing
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は一般的なＭＯＶＥ命令のマイクロプログラムフ
ローチャート、第２図はバイト位置合わせ高速化のマイ
クロプログラムのフローチャート、第３図は本考案のデ
ータ処理装置の実施例のマイ′ クロプログラムのフロ
ーチャート、第４図は本考案のデータ処理装置の実施例
の構成図、第５図は第４図の装置における″タイムチャ
ートである。−”１〜５．１１〜１４．２１〜２３・・
・マイクロ命令、１０１．．１０・２，１０８，１０４
，１０５・・・アンドゲート、１０９・・・オアゲート
、１０３・・・ＢＵＳＹラッチ、１０６・・・ＤＵＭＭ
Ｙラッチ、１０７・・・制御装置。FIG. 1 is a microprogram flowchart of a general MOVE command, FIG. 2 is a flowchart of a microprogram for accelerating byte alignment, and FIG. 3 is a flowchart of a microprogram of an embodiment of the data processing device of the present invention. FIG. 4 is a block diagram of an embodiment of the data processing apparatus of the present invention, and FIG. 5 is a time chart of the apparatus of FIG. 4.-"1~5.11~14.21~23...
・Micro instructions, 101. ．． 10・2,108,104
, 105...AND gate, 109...OR gate, 103...BUSY latch, 106...DUMM
Y latch, 107...control device.
Claims (1)
ドレスで指定する記憶装置位置へ格納子る命令において
第２のアドレスで指定したデータの読出し中であること
を示す第１の論理と、上記読出しデータが確定すると第
１のアドレスで指定 ゛する記憶装置への書込みを始め
ることを示す第２の論理とを具備するマイクロ命令制御
の処理装置において、上記第１の論理と第２の論理のア
ンド条件が成立したときに、マイクロ命令の実行を停止
し、更に上記アンドゲートの条件が不成立になったとき
、マイクロ命令の実行を再開するように構成したことを
特徴人するデータ処理装置。a first logic indicating that data specified by the second address is being read in an instruction to store data in the storage device specified by the second address to a storage device location specified by the first address; In a microinstruction-controlled processing device, the microinstruction-controlled processing device includes a second logic indicating that writing to a storage device specified by a first address is started when the read data is determined. The data processing device is characterized in that the execution of the microinstruction is stopped when the AND condition is satisfied, and the execution of the microinstruction is resumed when the AND gate condition is not satisfied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13435481U JPS5839646U (en) | 1981-09-11 | 1981-09-11 | data processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13435481U JPS5839646U (en) | 1981-09-11 | 1981-09-11 | data processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5839646U true JPS5839646U (en) | 1983-03-15 |
Family
ID=29927782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13435481U Pending JPS5839646U (en) | 1981-09-11 | 1981-09-11 | data processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839646U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6322844U (en) * | 1986-07-28 | 1988-02-15 |
-
1981
- 1981-09-11 JP JP13435481U patent/JPS5839646U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6322844U (en) * | 1986-07-28 | 1988-02-15 | ||
| JPH0243326Y2 (en) * | 1986-07-28 | 1990-11-19 |
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