JPS59165043U - Malfunction prevention circuit - Google Patents

Malfunction prevention circuit

Info

Publication number
JPS59165043U
JPS59165043U JP5616283U JP5616283U JPS59165043U JP S59165043 U JPS59165043 U JP S59165043U JP 5616283 U JP5616283 U JP 5616283U JP 5616283 U JP5616283 U JP 5616283U JP S59165043 U JPS59165043 U JP S59165043U
Authority
JP
Japan
Prior art keywords
prevention circuit
malfunction prevention
microcomputer
writing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5616283U
Other languages
Japanese (ja)
Inventor
三浦 健児
亀本 一廣
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP5616283U priority Critical patent/JPS59165043U/en
Publication of JPS59165043U publication Critical patent/JPS59165043U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はマイクロコンピュータの一例を示すシステムブ
ロック図、第2図はこの考案に係る誤動作防止回路の一
実施例を示す回路図、第3図は第2図に示す回路の要部
を具体的に示す回路図、第4図は第3図に示す回路の動
作を説明する為のタイミングチャートである。 31・・・RAM、33.34・・・端子、35.36
・・・カウンタ回路、37・・・フリップフロップ回路
、38・・・ラッチ回路、39・・・遅延回路、40・
・・ノア回路、41.42・・・インバータ回路。 ■−−−t− (a)pm’      11mWt川”u’1n(b
)P2 −「1」−1J−しj−Lj−(C) P3 
−一一一一一。−」−一一一(d) Ql     、
」1−− (e)Psr−一一一−4 (f) Ql、1       −−シーーー−(9)
 P4 −一−−−−ヤーーー]−−t1h虫し七−ド
                5忍H七−ド=8七
−−− 一一一一イ
Fig. 1 is a system block diagram showing an example of a microcomputer, Fig. 2 is a circuit diagram showing an embodiment of the malfunction prevention circuit according to this invention, and Fig. 3 is a detailed illustration of the main parts of the circuit shown in Fig. 2. FIG. 4 is a timing chart for explaining the operation of the circuit shown in FIG. 31...RAM, 33.34...Terminal, 35.36
... Counter circuit, 37... Flip-flop circuit, 38... Latch circuit, 39... Delay circuit, 40.
...Nor circuit, 41.42...Inverter circuit. ■---t- (a) pm' 11mWt river"u'1n(b
)P2 -“1”-1J-shij-Lj-(C) P3
-One, one, one. -”-111 (d) Ql,
”1-- (e) Psr-111-4 (f) Ql, 1 --C-(9)
P4 -1---Ya]--t1h Mushishi 7-do 5ninH7-do=87---1111i

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロコンピュータと、データの書き込み及び読み出
しが可能なメモリと、前記マイクロコンぎユータが初期
状態に設定されると前記メモリに所定のデータを書き込
むことが可能なデータ書込み手段と、前記メモリに書き
込まれたデータの内容が前記所定のデータの内容から変
化した場合前記マイクロコンピュータを初期状態に設定
する初期化手段とを具備した誤動作防止回路。
a microcomputer; a memory capable of writing and reading data; a data writing means capable of writing predetermined data to the memory when the microcomputer is set to an initial state; and initializing means for setting the microcomputer to an initial state when the content of the predetermined data changes from the predetermined data content.
JP5616283U 1983-04-15 1983-04-15 Malfunction prevention circuit Pending JPS59165043U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5616283U JPS59165043U (en) 1983-04-15 1983-04-15 Malfunction prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5616283U JPS59165043U (en) 1983-04-15 1983-04-15 Malfunction prevention circuit

Publications (1)

Publication Number Publication Date
JPS59165043U true JPS59165043U (en) 1984-11-06

Family

ID=30186483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5616283U Pending JPS59165043U (en) 1983-04-15 1983-04-15 Malfunction prevention circuit

Country Status (1)

Country Link
JP (1) JPS59165043U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277993A (en) * 1975-12-24 1977-06-30 Toshiba Corp Numeric controller
JPS5346237A (en) * 1976-10-08 1978-04-25 Canon Inc Electronic device having memory unit capable of write-in and readout
JPS53119637A (en) * 1977-03-28 1978-10-19 Nissin Electric Co Ltd Data checking system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5277993A (en) * 1975-12-24 1977-06-30 Toshiba Corp Numeric controller
JPS5346237A (en) * 1976-10-08 1978-04-25 Canon Inc Electronic device having memory unit capable of write-in and readout
JPS53119637A (en) * 1977-03-28 1978-10-19 Nissin Electric Co Ltd Data checking system

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