JPS58169754U - Information phase conversion circuit - Google Patents

Information phase conversion circuit

Info

Publication number
JPS58169754U
JPS58169754U JP6648582U JP6648582U JPS58169754U JP S58169754 U JPS58169754 U JP S58169754U JP 6648582 U JP6648582 U JP 6648582U JP 6648582 U JP6648582 U JP 6648582U JP S58169754 U JPS58169754 U JP S58169754U
Authority
JP
Japan
Prior art keywords
signal
conversion circuit
phase conversion
circuit
information phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6648582U
Other languages
Japanese (ja)
Inventor
宇佐美 政彦
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP6648582U priority Critical patent/JPS58169754U/en
Publication of JPS58169754U publication Critical patent/JPS58169754U/en
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例を示す構成図、第2図1−、−gは第1
図の動作を示すタイミング図、第3図は本考案の実施例
を示す回路構成図、第4図A〜■は電3図の動作を示す
タイミング図である。 □101・・・・・・エラステ
ィックメモリ、201・・・・・・シフトレジスタ、2
02・・・・・・シフトレジスタ、203・・・・・・
書き込み読み出しクロック作成回路。
Figure 1 is a configuration diagram showing a conventional example, Figure 2 1- and -g are the first
FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention, and FIGS. □101...Elastic memory, 201...Shift register, 2
02...Shift register, 203...
Write/read clock generation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周期的バースト状に発生する信号を、信号発生源におい
て、連続的な信号に変換する回路と、信号受信側では、
書き込み位相と読み出し位相の関係において、読み出し
中は書き込みを禁止して、前記連続的な信号を周期的且
つバースト状の信号に変換する回路を有することを特徴
とする情報位相変換回路。
A circuit that converts a periodic burst-like signal into a continuous signal at the signal generation source, and a circuit that converts the signal that occurs in a periodic burst shape into a continuous signal, and
An information phase conversion circuit comprising a circuit that prohibits writing during reading in the relationship between the writing phase and the reading phase and converts the continuous signal into a periodic and burst-like signal.
JP6648582U 1982-05-07 1982-05-07 Information phase conversion circuit Pending JPS58169754U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6648582U JPS58169754U (en) 1982-05-07 1982-05-07 Information phase conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6648582U JPS58169754U (en) 1982-05-07 1982-05-07 Information phase conversion circuit

Publications (1)

Publication Number Publication Date
JPS58169754U true JPS58169754U (en) 1983-11-12

Family

ID=30076353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6648582U Pending JPS58169754U (en) 1982-05-07 1982-05-07 Information phase conversion circuit

Country Status (1)

Country Link
JP (1) JPS58169754U (en)

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