JPS5917096U - Memory read control device - Google Patents

Memory read control device

Info

Publication number
JPS5917096U
JPS5917096U JP11071382U JP11071382U JPS5917096U JP S5917096 U JPS5917096 U JP S5917096U JP 11071382 U JP11071382 U JP 11071382U JP 11071382 U JP11071382 U JP 11071382U JP S5917096 U JPS5917096 U JP S5917096U
Authority
JP
Japan
Prior art keywords
control device
memory
read control
memory read
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11071382U
Other languages
Japanese (ja)
Inventor
柳瀬　秀治
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP11071382U priority Critical patent/JPS5917096U/en
Publication of JPS5917096U publication Critical patent/JPS5917096U/en
Pending legal-status Critical Current

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  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のメモリの読み出し制御装置のブロック図
、第２図ａ　”　ｅは第１図の動作説明用のタイミング
チャート、第３図ａ〜Ｃはダイナミックランダムアクセ
スメモリに供給される電源電流の説明用の波形図、第４
図はこの考案のメモリの読み出し制御装置の１実施例の
ブロック図、第５図ａ〜Ｗは第５図の動作説明用のタイ
ミングチャートである。 Ｌａ〜Ｌｄ・・・ラッチ回路、Ｍａ〜Ｍｄ・・・ダイナ
ミックランダムアクセスメモリ、ＭＰＸ・・・マルチプ
レクサ。Figure 1 is a block diagram of a conventional memory read control device, Figures 2a and 2e are timing charts for explaining the operation of Figure 1, and Figures 3a to 3C are power supply currents supplied to the dynamic random access memory. Explanatory waveform diagram, 4th
The figure is a block diagram of one embodiment of the memory read control device of this invention, and FIGS. 5a to 5W are timing charts for explaining the operation of FIG. 5. La to Ld: latch circuit, Ma to Md: dynamic random access memory, MPX: multiplexer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のダイナミックランダムアクセスメモリを遅延関係
をもたせながら読み出し駆動するメモリ駆動手段と、該
メモリ駆動手段により読み出された前記各メモリの出力
を保持する保持手段と、該保持手段により保持された前
記各メモリの出力を選択して順次に出力する出力手段と
を備えたメモリの読み出し制御装置。memory driving means for reading and driving a plurality of dynamic random access memories with a delay relationship; holding means for holding the outputs of the respective memories read by the memory driving means; and each of the above-mentioned memories held by the holding means. A memory read control device comprising an output means for selecting and sequentially outputting the output of the memory.
JP11071382U 1982-07-20 1982-07-20 Memory read control device Pending JPS5917096U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11071382U JPS5917096U (en) 1982-07-20 1982-07-20 Memory read control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11071382U JPS5917096U (en) 1982-07-20 1982-07-20 Memory read control device

Publications (1)

Publication Number Publication Date
JPS5917096U true JPS5917096U (en) 1984-02-01

Family

ID=30257364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11071382U Pending JPS5917096U (en) 1982-07-20 1982-07-20 Memory read control device

Country Status (1)

Country Link
JP (1) JPS5917096U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346238A (en) * 1976-10-08 1978-04-25 Toshiba Corp Semiconductor memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346238A (en) * 1976-10-08 1978-04-25 Toshiba Corp Semiconductor memory unit

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