GB1487750A - Memory systems - Google Patents

Abstract

1487750 Refreshing volatile memories SPERRY RAND CORP 30 Sept 1974 [1 Oct 1973] 42370/74 Heading G4C A volatile memory constructed on an LSI chip 10 and arranged to be continuously refreshed, comprises N recirculating shift register memory loops 0 to N - 1, data being clocked through the memory loops by two-phase clock signals # 1 , # 2 applied thereto at a frequency F D from an external data clock signal source 20 via 2N gates 30-31; ...; 34-35, the memory loops being addressed by signals fed to the gates 30-31; ..., 34-35 on N lines 14-18 from an address decoder 12, N refresh clock signals of sequential phases and each of frequency F R = F D /N also being fed to the gates 30-31; ...; 34 -35 from a refresh clock signal source 24 via N lines 25-57, so that in operation each non- addressed memory loop is refreshed at the frequency F R while concurrently a selected memory loop may be addressed. Data appearing at the outputs of memory loops 0 to N - 1 are recirculated to the corresponding inputs via N refresh circuits 15-19 and N lines 36-38. In use, if memory loop 0 is addressed via line 14, gates 30-31 are thereby enabled so that after 1 clock cylce the data in loop 0 is right-shifted 1 bit. In the next clock cycle, gates 32-33 are enabled by a refresh clock signal on line 26, gates 30-31 remaining enabled via line 14, so that after 2 clock cycles the respective right shifts in loops 0, 1 are 2, 1. The sequence continues until after N clock cycles loop 0 has returned to its original state and loops 1 to N - 1 are each right-shifted 1 bit. Data may be read out during the time loop 0 is addressed by a signal on a line 48 enabling a gate 50, a further gate 44 having been enabled by the address signal on line 14, the read-out data being present on a line 52. For writing, data is placed on line 52 and a write enable signal is supplied to a line WE. In a modification, Fig. 3 (not shown) the N memory loops 0 to N - 1 are divided into S subgroups where N=SÎ2<SP>n</SP>, and a separate refresh clock signal of frequency f R =F D /S is supplied in parallel to all the gates, e.g. (130)-(131); ...; (132)-(133) of a corresponding subgroup, e.g. subgroup 0, so that in operation, if loop 0 of subgroup 0 is addressed, it is refreshed at the frequency F D whereas the other loops of subgroup 0 and all the loops of subgroups 1 to N - 1 are refreshed at the frequency f R . In Fig. 5 (not shown) each subgroup, e.g. 0, has only a single pair of gates, e.g. (200)-(201), the clock signals being fed in parallel to the memory loops of each subgroup, and a particular memory loop within a subgroup being selected by a loop address decoder (214).