JPS5738995B2 - - Google Patents
Info
- Publication number
- JPS5738995B2 JPS5738995B2 JP11322974A JP11322974A JPS5738995B2 JP S5738995 B2 JPS5738995 B2 JP S5738995B2 JP 11322974 A JP11322974 A JP 11322974A JP 11322974 A JP11322974 A JP 11322974A JP S5738995 B2 JPS5738995 B2 JP S5738995B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Shift Register Type Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US402503A US3859640A (en) | 1973-10-01 | 1973-10-01 | Concurrent data address and refresh control for a volatile lsi memory system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50111943A JPS50111943A (ja) | 1975-09-03 |
| JPS5738995B2 true JPS5738995B2 (ja) | 1982-08-18 |
Family
ID=23592177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11322974A Expired JPS5738995B2 (ja) | 1973-10-01 | 1974-09-30 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3859640A (ja) |
| JP (1) | JPS5738995B2 (ja) |
| DE (1) | DE2445878C2 (ja) |
| FR (1) | FR2246936B1 (ja) |
| GB (1) | GB1487750A (ja) |
| IT (1) | IT1030618B (ja) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4322819A (en) * | 1974-07-22 | 1982-03-30 | Hyatt Gilbert P | Memory system having servo compensation |
| US4523290A (en) * | 1974-07-22 | 1985-06-11 | Hyatt Gilbert P | Data processor architecture |
| US5615142A (en) * | 1970-12-28 | 1997-03-25 | Hyatt; Gilbert P. | Analog memory system storing and communicating frequency domain information |
| US4445189A (en) * | 1978-03-23 | 1984-04-24 | Hyatt Gilbert P | Analog memory for storing digital information |
| US5339275A (en) * | 1970-12-28 | 1994-08-16 | Hyatt Gilbert P | Analog memory system |
| US5566103A (en) * | 1970-12-28 | 1996-10-15 | Hyatt; Gilbert P. | Optical system having an analog image memory, an analog refresh circuit, and analog converters |
| US5619445A (en) * | 1970-12-28 | 1997-04-08 | Hyatt; Gilbert P. | Analog memory system having a frequency domain transform processor |
| US4019174A (en) * | 1971-12-08 | 1977-04-19 | Monarch Marking Systems, Inc. | Data collecting and transmitting system |
| DE2348490C3 (de) * | 1973-09-26 | 1979-07-26 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Betreiben eines Ladungsverschiebespeichers |
| US4030080A (en) * | 1974-01-07 | 1977-06-14 | Texas Instruments Incorporated | Variable module memory |
| GB1458682A (en) * | 1974-07-10 | 1976-12-15 | Gte International Inc | Storage of informationp |
| US4084154A (en) * | 1975-05-01 | 1978-04-11 | Burroughs Corporation | Charge coupled device memory system with burst mode |
| US4024512A (en) * | 1975-06-16 | 1977-05-17 | Fairchild Camera And Instrument Corporation | Line-addressable random-access memory |
| US4032904A (en) * | 1975-07-09 | 1977-06-28 | International Business Machines Corporation | Means for refreshing ac stable storage cells |
| NL7512834A (nl) * | 1975-11-03 | 1977-05-05 | Philips Nv | Geheugen met vluchtige informatie opslag en willekeurige toegankelijkheid. |
| US4112504A (en) * | 1976-10-20 | 1978-09-05 | Burroughs Corporation | Fast access charge coupled device memory organizations for a semiconductor chip |
| US4238842A (en) * | 1978-12-26 | 1980-12-09 | Ibm Corporation | LARAM Memory with reordered selection sequence for refresh |
| US4313159A (en) * | 1979-02-21 | 1982-01-26 | Massachusetts Institute Of Technology | Data storage and access apparatus |
| US5128563A (en) * | 1990-11-28 | 1992-07-07 | Micron Technology, Inc. | CMOS bootstrapped output driver method and circuit |
| JP3018498B2 (ja) * | 1990-11-30 | 2000-03-13 | 日本電気株式会社 | 半導体記憶装置 |
| US5208779A (en) * | 1991-04-15 | 1993-05-04 | Micron Technology, Inc. | Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs |
| US5229970A (en) * | 1991-04-15 | 1993-07-20 | Micron Technology, Inc. | Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown |
| US5229969A (en) * | 1991-04-15 | 1993-07-20 | Micron Technology, Inc. | Method for synchronizing refresh cycles in self-refreshing DRAMs having timing circuit shutdown |
| JP3247377B2 (ja) * | 1992-04-13 | 2002-01-15 | セイコーエプソン株式会社 | 高密度バッファメモリアーキテクチャ及び方法 |
| WO1994003901A1 (en) * | 1992-08-10 | 1994-02-17 | Monolithic System Technology, Inc. | Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration |
| US7434761B2 (en) * | 2003-05-19 | 2008-10-14 | Commscope Properties, Llc | Cable deployment and storage system and associated methods |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1248681A (en) * | 1969-01-08 | 1971-10-06 | Int Computers Ltd | Improvements in or relating to digital electrical information processing apparatus |
| US3691534A (en) * | 1970-11-04 | 1972-09-12 | Gen Instrument Corp | Read only memory system having increased data rate with alternate data readout |
-
1973
- 1973-10-01 US US402503A patent/US3859640A/en not_active Expired - Lifetime
-
1974
- 1974-09-18 IT IT27447/74A patent/IT1030618B/it active
- 1974-09-26 DE DE2445878A patent/DE2445878C2/de not_active Expired
- 1974-09-30 GB GB42370/74A patent/GB1487750A/en not_active Expired
- 1974-09-30 JP JP11322974A patent/JPS5738995B2/ja not_active Expired
- 1974-09-30 FR FR7432846A patent/FR2246936B1/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3859640A (en) | 1975-01-07 |
| DE2445878A1 (de) | 1975-04-10 |
| FR2246936A1 (ja) | 1975-05-02 |
| JPS50111943A (ja) | 1975-09-03 |
| FR2246936B1 (ja) | 1981-05-29 |
| GB1487750A (en) | 1977-10-05 |
| DE2445878C2 (de) | 1983-01-05 |
| IT1030618B (it) | 1979-04-10 |