SU1315970A1 - Multiplying device - Google Patents

Abstract

A device for multiplying binary numbers presented in the additional code can be used / 2 "lit 15 pg 2 17 but in digital computing and measurement systems. The device contains four tabular multipliers 1-4 and seven adders 5-11, and 12, 13, 14 — the inputs of the younger, senior, and sign bits of the second factor, respectively; 15, 16, 17 — the inputs of the corresponding bits of the first factor, 18–21 — the device outputs. By combining the computational operation of the “partial products” with the preliminary partial correction of the result in tabular multipliers, it was possible to reduce the hardware costs of the device. 1 il. 18 (L SO YU 20 ate QD I 21

Description

eleven

The invention relates to computing and can be used in digital computing and measuring systems.

The purpose of the invention is to reduce hardware costs.

The drawing shows the functional diagram of the device.

The device contains the first 1, the fourth 2, the second 3 and the third 4 tabular multipliers, seven adders 5-11, the inputs 12-14 junior, senior and sign bits of the second factor, the inputs 15-17 junior, senior and sign bits of the first multiplier, outputs 18 and 19 of the first and second low-order digits of the product, outputs 20 and 21 of the first and second high-order bits of the product.

Coding of functional converters with n-bit input numbers A and B, by dividing each of them into two parts (A, B,), where the bits of A, B, -n; Aj, Bj-nj is carried out according to the following formulas:

.Bj, (mod); (1) Bj + Ef, -;

Z A B + bn-AI-2, (mod 2); (2) Z, A, - B, + a „-B ,, - A, -2. , (3)

The final result of the work realized by the device is calculated by the formula

, + () 2 + Z ,. 2 Chap- 2% -t-b -2, (mod),

(four)

where mod 2 indicates that the result is represented in the x-bit section, a, and b are sign bits of the operands.

The device works as follows.

With positive factors x (A,), the coefficients are a, b, 0, so the correction does not occur. Expression (4) takes the form

, 2n

one

,-.AT,. 2 (A, - B + Aa-B) -2 +

(five)

+ A2B, (mod 2)

Since Z7 / 0, writing it in the direct code is equivalent to writing in the additional code.

59702

If one of the factors is negative, for example, from the outputs of tabular multipliers, partial products come from a preliminary

5 correction and after summing give the following result:, -. 2. (A, B4 +

+ Aj.Bi + Bi-2MX2 + Ai-B2-2 -2 (mod),

fO

(6)

since a, 1,.

Expression (6) can be represented as the sum of two terms z, equal to the product of the codes A ,. In and the correction factor with

Z Z + C A-B + 2 (B + 1) Z + 2 (-B)

(mod) „(7)

Let us now consider the process of multiplying with the transformation of factors into a direct code and with the subsequent transformation of the product into an additional code. Since AO, therefore,

, 2n

, 2n

, () () - B

2 + A B-2 + Z + 2 - (-B), (mod). (8)

As you can see, expressions (7) and (8) are identical (the coefficient 2 goes beyond the () -size grid and therefore does not affect the result), which indicates the correctness of the performance of the production by the device.

The product is executed in the same way in the case of,. If one of the factors is equal to zero (for example, B), the expression (4) takes the form

Zn

- 2 -2 2 + Bi-2

+2

Zn-i

45

 (B + 1), (mod 2),

those. even if a negative number is multiplied by zero, the output zero result will be positive, which corresponds to the representation of numbers in 50 additional codes.

In case both factors are negative, the result of the product according to (4) is as follows:

  + (A, - B + B AJ + BI-) 2 +

+ (A, B, + BV 2 + A, 2 M-2 2 + 2% 2 A-B + 2 - (-B) +2; (- A), (mod). (9)

In the classical product, similarly to (8), taking into account the fact that, we get

 A a p i

.Vp () () 2 + AB

) +2 (-B), (mod 2). (ten)

Coincidence (9) and (10) indicates that in this case the device produces the correct result.

Numbers A and B are divided into two equal parts with the number of bits in each. Expressions (1-5), showing the operation of the device, take the form

B g Bj + a

(mod

2b;

Aj + b, -, (mod

2 ");

(11) (12)

 ,, - A, - 2, (mod 2);

 + (Z2 + Z5), -2 +

Claims (1)

.2, (mod 2). Invention Formula A multiplying device containing four tabular multipliers and seven adders, the lower order input of the first multiplier device being the first information input of the first table multiplier and connected to the first information input of the second table multiplier, the second information input of which is the second higher factor of the second multiplier arrange 45 and is connected to the first information of which is the second output input of the third tabular multiplier, the second information input of which is the input of the higher bits of the first factor of the device and connected to the first information input of the fourth tabular multiplier, the second information input of which is input the lower bits of the second device multiplier and is connected to the second information input of the first table multiplier, the output of the lower bits of which is the first output of the lower bits view products 50 for the purpose of reducing equipment costs, the output of the lower bits of the tabular multiplier is connected to the second information input of its third adder, the transfer outputs of the first and third adders are connected to the transfer inputs of the second and fourth adders, respectively , in the course of transfer of the second adder are connected with the second information input of the fifth adder, the input of the sign row of the second co-multiplier device Signs, the input of the sign bit is first connected to the input of the sign bit. device multiplier is the input of the sign bit of the first multiplier of the fourth tabular multiplier, the output of the lower order bits the first multiplier of the third tabular multiplier and the transfer input of the sixth adder, the second information input of which is connected to the input hor 3159704 which is connected to the first information input of the first adder, the second information input of which is connected to the output of the higher bits The first tabular multiplier, the sign input of the second device multiplier is the sign input of the second multiplier of the second table multiplier, vy. fO the course of the high bits of which is connected to the first information input of the second adder, the second information input of which is connected to the output of the high bits of the fourth t5 of the table multiplier; the output of the sum of the first adder is connected to the first information input of the third adder, the output of the sum of which is the second output of the lower bits 20 of the device, the output of the sum of the second adder is connected to the first information input of the fourth adder, the second information input of which is connected to the output The 25 lower bits of the third table multiplier, the output of the higher bits of which is connected to the first information input of the fifth adder, the transfer input of which is connected to the transfer output of the fourth adder, the output of which is connected to the first information input of the sixth adder, the output of which is the first output the highest divisions of product output, the sum of the sum of the fifth and the transfer of the sixth adders are connected to the information input and the transfer input, respectively, of the seventh adder, the output which is the second exit the higher output bits of the device, characterized in that, in order to reduce hardware costs, the output of the lower bits of the second table multiplier is connected to the second information input of the third adder, the transfer outputs of the first and third adders are connected to the transfer inputs of the second and fourth adders , the transfer output of the second adder is connected to the second information input of the fifth adder, the input of the sign bit of the second device factor the first multiplier of the third tabular multiplier and the transfer input of the sixth adder, the second information input of which is connected to input 513159706 the house of the sign bit of the first sum is the bit of the second multiplier of the device third-party and the input of the sign tabular s multiplier.