SU1760630A2 - Counting device with check-up provision - Google Patents

Abstract

The invention relates to a pulse technique and can be used to control the operation of binary counters with a high degree of reliability due to the formation of an independent monitoring signal. SUMMARY OF THE INVENTION: A counting device with a control contains an M-bit binary counter 1, two encoders 2.1, 2.2, two adders 3.1, 3.2, block 4 comparisons, five elements OR 5, 6, 7, 8, 22, six elements 10, 11, 12, 13, 14, 20 delays, N-2 shaper 9.1-9.N-2 pulses, additional two-bit binary counter 18, additional shaper 19 pulses, key 21. 1 Cp f-ly, 4 ill.

Description

The invention relates to automation and computing, can be used to control the operation of binary counters.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows a functional diagram of the counting device with control; in fig. 2 shows an example of key execution; in fig. 3 — table of states of an M-bit binary counter; in fig. 4 shows the timing diagram of the device.

The counting device with the control contains an N-bit binary counter 1, the first 2.1 and the second 2.2 encoders, the first 3.1 and the second 3.2 adders, block 4 comparisons, the first 5, the second 6, the third 7 and the fourth 8 elements OR, N-2 drivers 9.1 -9. N-2 pulses, first 10, second 11, third 12, fourth 13 and fifth 14 delay elements, first element 15, input 16 and output 17 of the device, additional 2-bit binary counter 18, additional driver 19 pulses, sixth the delay element 20, the key 21 and the fifth element OR 22. The device input 16 is connected to the input of the sixth delay element 20, with the counting input of the additional 2-bit binary counter 18 and with the counting input of the N-bit binary counter 1, the outputs of which , starting from the third, are connected to the inputs of the shapers 9.1- 9. N-2 pulses, the outputs of which are connected to the inputs of the encoder 2.1, as well as, starting with the third shaper, with the inputs of the second encoder 2.2. The outputs of the encoder 2.1 are connected to the inputs of the first element OR 5, and also, besides the first output, are connected to information inputs, starting with the second, the adder 3.1,

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the outputs of which are connected to the first inputs of the unit 4 of the comparison. The outputs of the encoder 2.2 are connected to the inputs of the second element OR 6, and also, besides the first output, are connected to information inputs, starting with the second, adder 3.2, the outputs of which are connected to the second inputs of the comparison unit 4, the inverse output of which is connected to the first input of the AND 15 element The first input of the element OR 7 is connected to the first output of the encoder 2.1, the second input to the input of the delay element 11 and to the output of the first discharge of counter 1, and the output to the first information input of the adder 3.1, the control input of the summation, the control input of the calculation Ani and reset input of which are connected respectively to the input of the delay element 11, to the output of the delay element 12 and to the transfer output of counter 1. The first input of the OR element 8 is connected to the first output of the encoder 2.2, the second input - to the output of the third discharge of counter 1 and to the input the delay element 13, and the output with the first information input of the adder 3.2, the control input of the summation, the control input of the subtraction and the reset input of which are connected respectively with the output of the delay element 13, with the output of the delay element 14 and with the transfer output of the counter 1. Single Output of the OR gate 5 is connected to the input of the delay element 12, which through a delay element 10 output is connected to the second input of AND gate 15, whose output is connected to a second input of the OR gate 12. The output of OR 6 is connected to the input of the delay element 14. The outputs of the first and second bits and the inverse output of the second bit of the additional counter 18 are connected respectively to the first input of the switch 21, to the third input of the switch 21 and to the input of the additional driver 19 pulses, the output of which is connected to one of the inputs of the OR element 5. Second and fourth the inputs of the key 21 are connected to the outputs of the first and second bits of the counter 1, respectively, and the information input and the output of the key 21 are connected respectively to the output of the delay element 20 and to the first input of the element OR 22, the output of which is stroke device 17.

The key 21 contains the first 23 and second 24 comparison elements, the AND 25 element and the OR 26 element, the first and second inputs of which are connected respectively to the outputs of the first 23 and second 24 comparison elements. The output of the element OR 26 is connected to the second input of the element AND 25, the first input and output of which are connected respectively to the information input and output

key. The first, second, third, fourth inputs of the key are connected respectively to the first, second inputs of the first 23 and second 24 elements of the comparison, respectively.

Key 21 transmits a signal present at its information input provided it is present at the first and second or third and fourth signal inputs.

different logical level, i.e. It is a two-bit binary code comparison scheme that allows passing from the information input to the output in case of inequality of codes.

The additional shaper 19 is designed to form short pulses on the leading edge of the signal from the inverse output of the second bit of the counter 18. It can be a normal

difcepochku.

The delay time of element 20 is determined by the transient time in the additional counter 18. A description of other devices and other features of the device are given in the description of the known invention.

The essence of the device is to determine the number of units in the binary code of the counter using two

adders on different channels and subsequent comparison of the contents of adders, which during normal operation of the device at the time of comparison should be the same. FIG. 3 shows a table which shows in column 27 the values of M of counter 1 in decimal code, in column 28 of state of counter 1 in binary code, in column 29 the number of units in binary code, in column 30 the change in the number

units from state to state (A 1) of counter 1, in column 31 the number of units in binary code for states of counter 1, for which the value of A1 is negative, in column 32 the change in the number of units

for the state of column 31 (A 2). As can be seen from the table of FIG. 3, the number of units in the binary code of counter 1 is changed according to a certain law, namely a) when determining the first digit of counter 1 in

unit A 1 + 1; b) when establishing the second discharge of counter 1 in the unit A1 0; c) when establishing the third, fourth, fifth, etc. the bits of counter 1 into units 1 are -1, -2, -3 and

etc.

In addition, as can be seen from column 32 for the states of counter 1, in which the value of A 1 is negative, the sequence of values of A 2 repeats the sequence of values of D1, but at the same time A2 1 when the third bit of the counter is set to 1, D 2 0 when establishing in the unit of the fourth bit, D2 -1, -2, -3 when setting in the unit respectively the fifth, sixth, seventh digit, etc. Thus, to control the operation of counter 1, it is sufficient to compare the values of adders 3.1 and 3.2 (respectively, columns 29 and 31 of the table in Fig. 3) at times when D 1 has a negative value. In addition, the control of the first and second bits of the counter 1 is performed using a redundant additional counter 18, and the monitoring signal is formed additionally from the input pulse intended for counting and from the second discharge of the additional counter 18.

The device works as follows.

Timing diagrams of the operation of the device elements are shown in FIG. 4, where 1-1 - outputs of counter 1, respectively, will discharge 15; hatching shows the signals from the outputs of the corresponding delay elements; for charts. 1-1, 3.1 and 3.2 circles indicate correct states, and triangles indicate incorrect ones (results of failures).

With the arrival of the first pulse, the first bit of counter 1 is set to one. The signal from the first bit of counter 1 is fed through the OR 7 element to the first information input of the adder 3.1 and through the delay element 11 to the control input of the summation of the adder 3.1. Thus, when the first bit of counter 1 is set to one, one is added to adder 3.1. Counting pulses from the device input 16 also arrive at an additional counter 18. When the states of the first or second bits of the counters 1 and 18 are unequal, the signal from the output of the delay element 20 goes through the public key 21 and through the element OR 22 to the device output 17, signaling a failure in the operation of the device.

When a third bit of counter 1 is established, a signal arrives at the output of shaper 9.1, arriving at the input of the encoder 2.1, at the output of which appears the code of the unit arriving through the OR element 7 at the information input of the adder 3.1. This signal through the OR 5 element and the delay element 12 is fed to the control input of the subtraction of the adder 3.1, subtracting the unit from its content. Similar actions produce (duplicate) the signal from the inverse output

the counter 18 through the driver 19 to the element OR 5. In addition, the signal from the third bit of the counter 1 is fed through the element OR 8 to the first information input

adder 3.2 and through the element 13 of the delay per control input of the summation of adder 3.2, increasing its content by one. Similarly to the described device works when establishing the fourth and

0 of the first bits of the counter 1 in the unit with the difference that when the next bits of the counter 1 are set to one, the information inputs of the adders 3.1 and 3.2 are received from the encoders 2.1 and 2.2

5 corresponding discharge codes. When establishing the first bit of the counter 1 in the unit in the adder 3.2, the unit is subtracted, in the case of the establishment of the sixth bit-two, and so on.

0 The signal from the output of the element OR 5 through the delay element 12 and through the delay element 10 enters the second input of the element 15, the first input of which receives a signal from the output of the comparison unit 4. With

5 equality of the contents in the adders 3.1 and 3.2 at the inverse output of block 4 of the comparison signal is absent, therefore there is no signal at the output 17 of the device, otherwise it is not

0, a signal appears that detects a failure in the operation of counter 1. When the counter is inactive, an error signal is generated in the following circuit: device input 1 b - delay element 20 - device output 17. Along the same circuit, the error signal is formed when the first two bits of counter 1 malfunction or when counter 18 is malfunctioning. In the absence of signals from the third discharge of counter 1, a control signal is generated over the circuit:

0 second digit of counter 18 —former 19 — element OR 5 — delay element 12 — delay element 10 — element AND 15 (if the contents of adders 3.1 and 3.2 are not equal) —OR element 22 — device output 17.

5 Thus, the counting device with the control counts the number of pulses arriving at its input, checking the accuracy of the counter by dynamically comparing the values

0 two adders, the contents of which are formed through different channels, as well as by comparing the work of the lower bits of the main counter with the work of the additional counter.

Claims (2)

1. The counting device with control on the author. St. No. 1660173, characterized in that, in order to increase the reliability of the control, an additional two-digit counter is added to it, an additional the pulse driver, the fifth OR element, the sixth delay element and the key; the input of the sixth delay element is connected to the input of the device and to the counting input of an additional two-digit binary counter, the direct output of the first bit of which is connected to the first input of the key, the second input of which is connected to direct output of the second bit of the additional two-bit binary counter, the inverse output of which is connected to the input of the additional pulse maker, the output of which is connected to one of the inputs of the first element LEE, an output of first and second bits of the N-discharge binary counter is connected respectively to the second and fourth input key, the information input and output of which are respectively connected to the output element of the sixth delays and the first input of the fifth OR element, the second input of which is connected to the output of the first AND element, the output of the fifth OR element is connected to the output of the device. 2. Device pop. 1, characterized in that the key contains the first and second comparison elements, the OR element and the AND element, the first input and output of which are connected respectively to the information input and the outputs of the key, the first to fourth inputs of which are connected respectively to the first and second inputs 5, respectively, of the first and second elements of the comparison, the outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is PSD to the second input of the element I. 22 17 - & with Fig f about t 20 Fig 2 "22 about with so about UD g16. 123456 7 8 9 10 11 12 13 14 15 1B 17 JprU Ik II And And And II And And II II And II II II II II mug.fi