RU2045787C1 - Associative storage - Google Patents

Abstract

FIELD: computer engineering; storage devices. SUBSTANCE: device has associative accumulator incorporating associative storage elements with inputs through, outputs and input/outputs. Device also has address selector and decoder unit, polling and masking register unit, output register response recording register multiple coincidence analyzer, encoder, associative search mode setting unit. Associative storage element has RS flip-flop, first through fifth NAND gates, AND-NOR gate. EFFECT: improved design. 2 cl, 5 dwg

Description

 The invention relates to computer technology, in particular, to storage devices, and can find application in specialized storage systems and digital image processing, in associative parallel processors for solving information and logic problems, tasks of searching and sorting data, in digital signal processing devices in real time scale.

Known associative storage device containing an associative drive, the first and second address decoders, registers of the input word, output word, mask and Boolean ratio, a matching indication circuit, an encoding device, a search control circuit [1]
The disadvantage of this device is the lack of the ability to conduct conjunctive and disjunctive associative searches.

The closest technical solution to the claimed device is an associative storage device containing an associative drive, a block of polling and masking registers, an address selector and decoder block, a register for registering reactions, a multiple-coincidence analyzer, an encryptor [2]
The disadvantage of this device is the lack of the ability to conduct conjunctive and disjunctive associative searches with bitwise task of the corresponding mode of associative search.

 The aim of the invention is to expand the scope of the device by providing the ability to conduct conjunctive and disjunctive associative search with bitwise setting the corresponding mode of associative search.

 This goal is achieved by the fact that in an associative storage device containing an associative drive, a selector block and an address decoder, a reaction register, a multiple-match analyzer, an encoder, an output register, a block of polling and masking registers, the control inputs of which are inputs of write and reset signals of this unit, mode setting signals, recording and polling of the device, information inputs are data inputs of the first device group, and outputs from the first to fourth of each group s are connected to the inputs from the first to the fourth associative memory elements of the corresponding column of the associative drive, the first outputs of the memory elements of the corresponding column of the associative drive are connected and connected to the corresponding input of the output register, the control input of which is connected to the control input of the reaction fixation register and is the polling input of the device, and outputs are data outputs of the device, fifth inputs of associative memory elements of the corresponding line of the drive are combined and connected the corresponding outputs of the selector block and the address decoder, the information outputs of which are the data inputs of the second group of the device, the address inputs are the address inputs of the device, and the control inputs are the inputs of the write, selection and reset signals, the second outputs of the memory elements of the corresponding lines of the drive are combined and connected to the corresponding the inputs of the reaction fixation register, the outputs of which are connected to the inputs of the multiple-coincidence analyzer, the status output of which is the output of the properties, and the control input is the input of the gating signal and, at the same time, the control input of the encoder sample, the inputs of which are connected to the outputs of the multiple-analyzer, and the outputs are the address outputs of the device, a block for setting associative search modes is introduced, and the inputs of this block are connected to the data inputs of the first group devices that control inputs are inputs of signals of record and reset of the block, the first and second outputs of each group of outputs are connected respectively to the sixth and seventh inputs of the associative memory elements of the corresponding column of the associative drive, and the first and second inputs / outputs of each group of the unit for setting associative search modes are connected respectively to the first and second outputs of associative memory elements of the corresponding column of the drive, the control input of the block of polling and masking registers is the input of the gating signal of the associative search by external search argument.

 In addition, the associative memory element contains a trigger, AND-NOT elements from the first to fifth, the AND-OR-NOT element 2, the trigger setting inputs to "1" and "0" are connected respectively to the outputs of the first and second AND-NOT elements, the first inputs which are connected to the second inputs of the third and fourth and with the first input of the fifth AND-NOT elements and are the fifth input of the associative memory element, the first and second inputs of which are connected respectively to the second inputs of the first and second I-NOT elements, the third input is connected to the first inputs of the third eleme that AND-AND and the AND-OR-NOT element, the fourth input is connected to the first input of the fourth AND-NOT element and the fourth input of the AND-OR-NOT element, the sixth and seventh inputs of the associative memory element are connected to the third inputs of the third and fourth AND elements, respectively -NOT, the first and second inputs / outputs of the associative memory element are connected respectively to the second and fifth inputs of the 2 AND-OR-NOT element, the third input of which is connected to the fourth input of the third and second input of the fifth AND-NOT elements and is connected to the direct output of the trigger, inver a clear output of which is connected to the fourth input of the fourth AND-NOT element and the sixth input of the 2-OR-NOT element, the output of which is the second output of the associative memory element, the first output of which is the output of the fifth AND-NOT element.

 Figure 1 presents a diagram of an associative storage device; figure 2 diagram of an associative memory element; figure 3 circuit block selector and address decoder; in FIG. 4 diagram of a block of registers of polling and masking data; 5 is a diagram of a block for setting associative search modes.

 The device (figure 1) contains an associative drive 1, which includes associative memory elements 2 with inputs from the first 3 to the seventh 9, with the first 10 and second 11 outputs, with the first 12 and second 13 inputs / outputs. The device also comprises a block 14 of an address selector and decoder, a block 15 of polling and data masking registers, an output register 16, a reaction fixing register 17, a multiple match analyzer 18, an encryptor 19, an associative search mode setting unit 20.

 The outputs from the first 21 to the fourth 24 of each group of block 15 are connected respectively to the inputs from the first 3 to the fourth 6 associative elements 2 of the memory of the corresponding column of the drive 1.

 The first 25 and second 26 outputs of each group of block 20 are connected respectively to the sixth 8 and seventh 9 inputs of associative 2 memory elements of the corresponding column of drive 1, and the first 27 and second 28 outputs of each group of this block are connected respectively to the first 12 and second 13 inputs / outputs items 2 of the corresponding drive column 1.

 29 first group of device data inputs; 30 second group of device data inputs; 31 address inputs of the device; 32 device status output, indicating the presence of a "certain number" of matches as a result of an associative search; 33 address outputs of the device; 34 device data outputs.

The following control signals are applied to the device:
35 write signal to the drive 1;
36 signal polling drive 1;
37 a sample signal of the decoder unit 14;
38 a write signal to the register of block 14;
39 reset signal to “0” of block register 14;
40 a write signal to the polling register of block 15;
41 a write signal to the masking register of block 15;
42 reset signal to “0” of the polling and masking registers of blocks 15 and 20;
43 a gating signal for the worked out and sampling of the next active line by block 18, as well as for issuing by the encoder 19 to the address outputs 33 the addresses of the active line;
44 a write signal to the register of block 20;
45 signal gating associative search for an external search argument.

 In FIG. 2 shows an example implementation of an associative memory element 2, consisting of an RS flip-flop 46, AND-NOT elements from the first 47 to 5th 51, element 2I-OR-NOT 52. FIG. 2 also shows restrictive elements, not shown in FIG. 1 from the first 53 to the fourth 56 in the form of resistors that implement the "Mounting And" function.

 Block 14 of the selector and the address decoder (figure 3) contains a register 57, an address decoder 58, a group of OR elements 59.

 Block 15 registers polling and masking data (figure 4) consists of a register 60 polling, register 61 masking, the first 62 and second 63 groups of inverters, the first 64 and second 65 groups of AND elements, element groups OR 66.

 Block 20 defining modes of associative search (figure 5) contains a register 67, OR elements of the first 68 and second 69 groups.

 In [3], examples of the implementation of a multiple-coincidence analyzer are shown in [4] of the reaction fixation register.

 The device can operate in the following modes: recording at a given address (group of addresses) with masking arbitrary bits of the recorded word (group of words); reading at a given address; associative masked search by external search argument; associative masked search using words from an associative drive as search arguments; conjunctive and disjunctive maskable associative search.

 In the recording mode at the specified address, the word being written is received from inputs 29 and, by signal 40, it is fixed in the polling register 60 of block 15. Then, a mask is entered into register 61 of this block from inputs 29 by signal 41 (units in the bits of the mask register determine the masking of the corresponding bits of the drive) . At the same time, an m-bit code for the drive line address (M = 2.m number of words in the drive) is supplied to the inputs 31 of the decoder.

 And when the signal 35 is written to the drive 1 and the address is decrypted in the decoder 58 by the signal 37 at the input 3 and 4 of the associative elements 2 of the memory, one of the following signal combinations will arrive: "10" unit write code, "01" zero record code, "00 "the code for masking the record, and the active level is supplied to the inputs of 7 memory elements 2 of the selected line of the drive. And thus, recording is made at the selected address.

 If a word is written in a group of addresses in register 57 of block 14 from inputs 30, the signal 38 is used to write an argument in which units correspond to the activated lines of drive 1.

 In the mode of reading information at a given address, the code of the address of the read line is decoded to the inputs 31 of the decoder 58 of block 14, which is decoded by signal 38, activating the inputs 7 of the memory element 2 of the read line of the associative drive. The read word in the inverse code is fixed in the output register 16 by the signal 36 of the survey drive. Register 57 of block 14 in this mode should be reset to zero.

 In the mode of associative masked search by an external search argument, the search argument is received from inputs 29 and, by signal 40, is fixed in the polling register 60 of block 15. Then, a mask by signal 41 is written to masking register 61 of this block. The logic level must be set at all outputs of block 14 zero, which eliminates the influence of the signals at the outputs of the elements And 49 and 50 on the operation of the device in this mode. And when signal 36 is sent for polling drive 1 to inputs 5 and 6 of all memory elements 2, one of the following polling attributes will come in: “01” comparison with unity, “10” comparison with zero, “00” masking the comparison. In the first two cases, the unit-level signal will be stored at the output 11 of the memory element 2 if the polling attribute coincides with the bit stored in this memory element 2, and the output 11 of this memory element 2 will be reset to zero otherwise. When masking the comparison, the output 11 of the memory element 2 will retain a single level regardless of the contents of this memory cell. The result of the associative search is recorded in the register 17 of fixing reactions on the trailing edge of the signal 36. Moreover, if words that match the search argument are detected, then the corresponding bits of register 17 will be set to a single state.

 The multiple-match analyzer 18 serves for priority selection of one of the active lines of the register 17. In this case, the argument with the zero address has the highest priority from the arguments.

 The address of the active line selected by the multiple coincidence analyzer 18 is encoded by the encoder 19 and is output to the address outputs 33 of the device by signal 43. By re-supplying this signal, the worked out initialization of the next active line by the multiple coincidence analyzer is gated.

 In the associative masked search mode using words from the associative drive as search arguments, before applying the drive polling signal 36 and the associative search gating signal 45 by an external search argument to the device, a mask is defined in the register 61 of block 15, which defines masking of drive bits in this mode. And when signals 36, 45 are sent to inputs 5 and 6 of all memory elements 2, except for those masked, the combination "11" is given, which prohibits comparison with an external search argument. At the same time, the address code of the drive string, which is the search argument, is supplied to the inputs 31 of the decoder 58. When this code is decrypted by signal 37, the logical unit level is supplied to the inputs of 7 associative elements 2 of the memory of this line of the drive. Moreover, if one is written in the memory element of the source of the bit of the search argument, then the output of element And 49 of this memory element 2 is zeroed, and therefore, the conclusions of 12 memory elements 2 of the corresponding drive column are reset, initiating the comparison process with the content unit of all other memory elements of this column drive. In the event that zero is stored in any memory element 2 of the specified drive column, then the output of element 2 AND-NOT-52, and, therefore, the output 11 of this memory element 2 will be reset to zero, indicating a mismatch; if the unit is stored in it, then at the output 11 the unit potential will be preserved. If zero is written in the memory element 2 of the source of the search argument bit, then the output of the And 50 element of this memory element 2 is zeroed, and, therefore, the conclusions of 13 memory elements 2 of the corresponding drive column are reset, initiating the process of comparing the contents of all other memory elements with zero this drive column. In the event that zero is stored in any memory element 2 of the indicated storage column, then the output of this memory element 2 will be the level of the logical unit; if a unit is stored in it, then at output 11 a zero level will appear, indicating a mismatch. When masking at inputs 5 and 6 of elements 2 of the memory of the drive column under consideration, a combination of signals “00” will be given, fixing at the outputs of 11 elements 2 of the memory of this column the level of a logical unit.

 In conjunctive associative masked search, the search argument is formed on the basis of the conjunction operation on the contents of the memory elements of the corresponding bits (columns) of those words (rows) of the drive that are involved in the formation of this search argument.

 Prior to the conjunctive associative masked search mode, register 67 of block 20 must be reset to zero, a mask is written to register 61 of block 15, and an argument is entered in register 57 of block 14, in which the units correspond to the words of the drive participating in the search argument. And when the drive signal 36 is sent to the device and the associative search gating signal 45 by an external search argument, the result of the conjunctive associative masked search is recorded in the reaction fixing register 17.

 Let us consider in more detail the operation of the device in this mode using the example of associative memory elements of a drive column. The inputs 5 and 6 of these memory elements are fed a combination of signals "11". In the initial state, inputs 8 and 9, as well as inputs / outputs 12 and 13, are supplied with the level of a logical unit. The unit level is also fed to the inputs of 7 associative memory elements of the drive column, which are the sources of bits of the search argument. Moreover, if units are recorded in all memory elements of the sources of the drive column in question, then a combination of signals “01” will be established at the inputs / outputs 12 and 13 of all column memory elements, which corresponds to a single value of the search argument bit. And the contents of all memory elements of this drive column are compared with unity (see previous mode). If, however, zero is recorded in at least one memory element, then the output of the AND-NOT element 50 of this and, therefore, the input / output 13 sets the zero potential, and the third input of AND-NOT elements 49 from the input 8 of all memory elements specified drive column from the corresponding output 25 of block 20 will receive a signal of zero level, setting at the inputs / outputs 12 of the memory elements of the column zero potential. Thus, at the inputs / outputs 12 and 13 of the memory elements of this column, a combination of signals "10" will be set, corresponding to the zero value of the bit of the search argument. And the contents of all memory elements of this drive column in this case will be compared with zero.

 In a disjunctive associative masked search, the search argument is formed on the basis of the disjunction operation on the contents of the memory elements of the corresponding bits (columns) of those words (rows) of the drive that are involved in the formation of this search argument.

 Prior to the disjunctive associative masked search mode, all digits of register 67 of block 20 must be entered in units, a mask is written in register 61 of block 15, and an argument in register 57 of block 14, in which the units correspond to the words of the drive participating in the search argument. And when the drive signal 36 is sent to the device and the associative search gating signal 45 by an external search argument, the result of the disjunctive associative masked search is recorded in the reaction fixing register 17.

 Let us consider in more detail the operation of the device in this mode using the example of associative memory elements of a drive column. The inputs 5 and 6 of these memory elements are fed a combination of signals "11". In the initial state, inputs 8 and 9, as well as inputs / outputs 12 and 13, are supplied with the level of a logical unit. The unit level is also fed to the inputs of 7 associative memory elements of the drive column, which are the sources of bits of the search argument. Moreover, if zeros are recorded in all memory elements of the sources of the drive column in question, then a combination of signals “10” will be set at the inputs / outputs 12 and 13 of all column memory elements, which corresponds to the zero value of the search argument bit. And the contents of all the memory elements of this drive column are compared with zero. If, however, a unit is recorded in at least one memory element, then the output of the AND-NOT element 49 of this and, therefore, the input / output 12 sets the zero potential, and the third input of the AND-NOT elements 50 from the input 9 of all memory elements specified the drive column from the corresponding output 26 of the block 20 will receive a signal of zero level, which sets the unit potential at the inputs / outputs 13 of the memory elements of the column. Thus, at the inputs / outputs 12 and 13 of the memory elements of this column, a combination of signals “01” will be set, corresponding to the unit value of the bit of the search argument. And the contents of all memory elements of this drive column in this case will be compared with unity.

 The device implements the possibility of performing both conjunctive and disjunctive associative searches for various bits of the associative drive by setting a specific argument in the register 67 of block 20. Moreover, the units recorded in the bits of this register initiate the mode of disjunctive associative masked search, and the zeros of the conjunctive.

 Thus, the objective of the invention is achieved, which is to expand the scope of the device, by making it possible to conduct conjunctive and disjunctive associative searches with bitwise defining the corresponding mode of associative search.

Claims (2)

 1. ASSOCIATIVE MEMORY DEVICE, containing an associative drive, an address selector and decoder unit, a reaction fixation register, a multiple-coincidence analyzer, an encoder, an output register, a block of polling and masking registers, the control inputs of which are the inputs of the write and reset signals of this block, reference signals mode, recording and polling the device, the information inputs are the data inputs of the first group of the device, and the outputs from the first to fourth of each group are connected to the inputs from the first to the fourth of associative memory elements of the corresponding column of the associative drive, the first outputs of the memory elements of the corresponding column of the associative drive are connected and connected to the corresponding input of the output register, the control input of which is connected to the control input of the reaction fixation register and is the input of the polling device, and the outputs are the outputs of the device data, the fifth inputs associative memory elements of the corresponding drive string are combined and connected to the corresponding block output with an address selector and decoder, the information outputs of which are data inputs of the second device group, the address inputs are the device address inputs, and the control inputs are device write, selection and reset signal inputs, the second memory element outputs of the corresponding drive strings are combined and connected to the corresponding inputs of the reaction fix register, the outputs of which are connected to the inputs of the multiple coincidence analyzer, the status output of which is the device status output, and the control input is the input the gating signal and the control input of the sample of the encoder, the inputs of which are connected to the outputs of the multiple-analyzer, and the outputs are the address outputs of the device, characterized in that it contains an associative search mode setting unit, the inputs of which are connected to the data inputs of the first device group, the control inputs are inputs of recording and reset signals of the block, the first and second outputs of each group of outputs are connected respectively to the sixth and seventh inputs of associative memory elements, respectively vuyuschego column associative storage, and first and second outputs of each group of block assignment modes associative search are respectively connected to first and second outputs of the associative memory element corresponding storage column control input polling register block and the masking is the input signal is sampled associative search on external search argument device.  2. The device according to claim 1, characterized in that the associative memory element contains a trigger, AND-NOT elements from the first to fifth, AND-OR-NOT element 2, the trigger setting inputs to "1" and "0" are connected respectively to the outputs of the first and the second AND-NOT elements, the first inputs of which are connected to the second inputs of the third and fourth and the first input of the fifth AND-NOT elements and are the fifth input of the associative memory element, the first and second inputs of which are connected respectively to the second inputs of the first and second elements And NOT, the third input is connected to the lane the input inputs of the third AND-NOT element and the 2 AND-OR-NOT element, the fourth input is connected to the first input of the fourth AND-NOT element and the fourth input of the 2-OR-NOT element, the sixth and seventh inputs of the associative memory element are connected to the third inputs of the third and of the fourth AND-NOT elements, the first and second outputs of the associative memory element are connected respectively to the second and fifth inputs of the 2-OR-NOT element, the third input of which is connected to the fourth input of the third and second input of the fifth AND-NOT elements and is connected to the direct output dy trigger inverse output of which is connected to a fourth input of the fourth AND-NO element and to the sixth input element 2I-OR-NO element whose output is the second output of the associative memory element, the output of the fifth AND-NO element is a first output of the associative memory element.