RU2168216C2 - Associative memory matrix - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: matrix is used for fabrication and design of dedicated system for data storage, retrieval, and sorting, for associative parallel processors, for solving information-logical problems, for real-time processing of digital signals. Matrix has memory elements and logical units whose number depends on number of matrix columns, address buses, record bit buses, polling bit buses, polling result buses. Matrix provides for associative search by arguments shaped basing on coincidence between content of memory elements of respective digits of matrix lines participating in shaping these search arguments. EFFECT: enlarged functional capabilities. 1 dwg

Description

 The invention relates to computer technology and can find application in the design and creation of specialized systems for storing, searching and sorting information, in associative parallel processors, in solving information and logic problems, in digital signal processing devices in real time.

 Known associative drive associative storage device, consisting of associative memory elements and providing the ability to conduct conjunctive and disjunctive associative search [1].

 The disadvantage is the lack of the possibility of an associative search by arguments formed on the basis of matching the contents of the associative memory elements of the corresponding bits of those rows of the drive that are involved in the formation of these search arguments.

 The closest technical solution to the claimed one is an associative storage matrix containing memory elements and logical blocks by the number of columns of the matrix, as well as address buses, write write buses, poll poll buses, output poll results buses, output comparison comparison buses [2].

 The disadvantage is the lack of the possibility of an associative search by arguments formed on the basis of matching the contents of the memory elements of the corresponding bits of those rows of the matrix that are involved in the formation of these search arguments.

 The technical problem solved in the invention is to expand the scope by providing the possibility of an associative search by arguments formed on the basis of the coincidence of the contents of the memory elements of the corresponding bits of those rows of the matrix that are involved in the formation of these search arguments.

 This goal is achieved by the fact that in the associative storage matrix containing memory elements and logical blocks according to the number of columns of the matrix, and the address inputs and outputs of the results of the polling of the memory elements of each row of the matrix are respectively combined and connected to the corresponding address buses and buses of the polling results the bit inputs of the recording of memory elements of each column of the matrix are connected to the corresponding first and second bit buses of the record, the first and second bit inputs of the polling of elements The names of each column of the matrix are connected to the corresponding first and second digit polling buses, each memory element contains AND-NOT elements from the first to the fourth, element 2 AND-OR-NOT, a trigger whose direct and inverse outputs are connected respectively to the second inputs of the third and fourth elements AND NOT, the installation inputs to "1" and "0" are connected respectively to the outputs of the first and second elements AND NOT, the second inputs of which are connected respectively to the first and second bit inputs of a memory element record, and the first inputs are connected to a the front-end input of the memory element, as well as with the first inputs of the third and fourth NAND elements, the outputs of which are connected respectively to the first and second bit conclusions of comparison by coincidence of the memory element of the corresponding column of the matrix, the first and second bit of the polling inputs of which are connected respectively to the first and fifth inputs of the element 2 AND-OR-NOT, the output of which is the output of the result of the polling of the memory element, and the fourth and eighth inputs are connected respectively to the direct and inverse outputs of the trigger, each the logical block is made on the OR elements from the first to the third, with the first and second bit buses of the matrix column polling connected to the first and second inputs of the corresponding logical block, the third input of which is the bit input of the polling mode job, the first and second outputs are connected to the first and second bit comparison conclusions on the coincidence of the memory elements of the corresponding matrix column, the associative comparison resolution inputs of which are connected to the third output of the logical block, as well as to the interconnected These are the third and seventh inputs of the 2AND-OR-NOT element, the second and sixth inputs of which are connected respectively to the outputs of the third and fourth AND-NOT elements, the first and second inputs of each logic block are connected respectively to the first inputs of the first and second OR elements, the second inputs which are interconnected and connected to the bit input of the polling mode job, and the outputs are the first and second outputs of the logic block and are connected respectively to the first and second bit outputs of the comparison by coincidence com of the corresponding column of the matrix, as well as to the first and second inputs of the third OR element, the output of which is the third output of the logical block.

 The drawing shows a diagram of an associative storage matrix, consisting of memory elements 1, logical blocks 2 by the number of columns of the matrix, as well as address buses 3, the first 4 and second 5 bit write buses, the first 6 and second 7 bit poll buses, poll results bus 8 .

 Each memory element 1 contains a trigger 9, AND-NOT elements from the first 10 to the fourth 13, element 2 AND-OR-NOT 14, as well as address input 15, the first 16 and second 17 bit recording inputs, the first 18 and second 19 bit poll inputs , the output of the survey results 20, the first 21 and second 22 bit conclusions of the comparison of the coincidence of the memory element of the corresponding column of the matrix, the input resolution of associative comparison 23.

 Each logical block 2 contains OR elements from the first 24 to the third 26, as well as the first 27 and second 28 inputs, the bit input of the job of the polling mode 29, outputs from the first 30 to the third 32.

 The drawing also shows the restrictive elements, made in the form of resistors R, and illustrating the implementation of the function "Mounting And".

 In the case of a masked record in the matrix at a given address, the first 4 and second 5-bit write buses and, therefore, one of the following signal combinations comes to the inputs 16 and 17 of all memory elements 1: "10" - recording unit; "01" - record of zero; "00" - masking the recording. Then, a high logic level is applied to the corresponding address bus 3, which initiates the recording of the corresponding values at the given address.

 When reading information at a given address, a high logic level is supplied to the corresponding address bus 3, which initiates the reading of a word in the inverse code from the first 21 bit outputs of memory elements 1 of the corresponding matrix row.

 In the mode of associative masked search by an external search argument, all address buses 3 of the matrix must be zeroed. The logic inputs 2 of the logic block 2 interrogation mode input 29 are supplied with a high logic level, and from the first 6 and second 7 bit interrogation buses, the first 18 and second 19 bit interrogation inputs of the memory element 1 receive one of the following signal combinations (sign of comparison): "10 "- comparison with zero; "01" - comparison with unit; "00" - masking the comparison, initiating a comparison with the contents of the trigger of the corresponding memory element 1.

 If it matches (or when masking the comparison), the output 20 of memory element 1 will retain the level of the logical unit. If a mismatch occurs, then a low logic level will appear at the output 20 of this memory element, resetting the corresponding bus 8 of the polling results.

 The mode of associative masked search by arguments formed on the basis of the coincidence of the contents of the memory elements of the corresponding rows of the matrix, which participate in the formation of this search argument, is initiated by the supply of the following signals to the matrix. Firstly, the logic unit level must be set at the inputs of 29 logical blocks 2, and secondly, the logical unit level is supplied to the address lines 3 of the words involved in the formation of the search argument.

 Moreover, if only 0 zeros (units) are stored in triggers of 9 selected memory elements 1 of any matrix column, then at the terminals 21 and 22 of all memory elements 1 of this matrix column a combination of signals “10” (“01”) will be established sign of comparison with zero (unit). In this case, the contents of all the memory elements of this column of the matrix will be compared with unity.

 If the triggers 9 of the selected memory elements 1 of any column of the matrix store both zeros and ones, then the conclusions of 21 and 22 of all memory elements 1 of this column of the matrix will establish a combination of signals "00". At the same time, the third output 32 of the corresponding logical block 2 will be set to a logical zero level, firstly, blocking (masking) the comparison in elements 2I-OR-NOT 14 of all memory elements 1 of the given column of the matrix and, secondly, indicating the mismatch of the contents of the memory elements 1 column of the matrix involved in the formation of the value of the corresponding category of the search argument.

 The mode of associative masked search by an external search argument can be combined with the one considered below. In this case, the external search argument, along with the selected rows of the matrix, is involved in the formation of the argument based on the match operation.

 To implement this mode, all other previous conditions, the logic zero level must be set at inputs 29 of logic blocks 2, and one of the signal combinations: “10”, “01”, “00”, must be applied to the bit lines of the polling 6 and 7.

 By applying the combination of signals “00” to the bit lines of the polling 6, 7 (with “O” at inputs 29), the external masking of the comparison is performed in elements 2I-OR-NOT 14 of all memory elements 1 of the corresponding matrix columns.

 When performing a combined associative search for each column, it is possible to individually specify the mode: either a combined associative search or an associative search only by an external search argument.

 Thus, the goal is achieved to expand the scope by providing the possibility of an associative search on the arguments formed on the basis of the coincidence of the contents of the memory elements of the corresponding bits of those rows of the matrix that are involved in the formation of these search arguments.

Sources of information
1. Associative storage device. RF patent N 2045787, cl. G 11 C 15/00, 1995.

 2. Associative storage matrix. RF patent N 2065207, cl. G 11 C 15/00, 1996 (prototype).

Claims (1)

 An associative storage matrix containing memory elements and logical blocks according to the number of matrix columns, with the address inputs and outputs of the results of the polling of the memory elements of each row of the matrix, respectively, combined and connected to the corresponding address buses and buses of the polling results, the first and second bit inputs of writing the memory elements of each column matrices are connected to the corresponding first and second bit write buses, the first and second bit inputs of the interrogation of memory elements of each column of the matrix are connected s to the corresponding first and second bit of the poll bus, each memory element contains AND-NOT elements from the first to the fourth, element 2 AND-OR-NOT, a trigger whose direct and inverse outputs are connected respectively to the second inputs of the third and fourth AND-NOT elements, the installation inputs to "1" and "0" are connected respectively to the outputs of the first and second NAND elements, the second inputs of which are connected respectively to the first and second bit inputs of the memory element, and the first inputs are connected to the address input of the memory element, as well asthe first inputs of the third and fourth AND-NOT elements, the outputs of which are connected respectively to the first and second bit outputs of comparison by coincidence of the memory element of the corresponding column of the matrix, the first and second bit inputs of the polling of which are connected respectively to the first and fifth inputs of the 2AND-OR-NOT element, the output of which is the output of the result of polling a memory element, and the fourth and eighth inputs are connected respectively to the direct and inverse outputs of the trigger, characterized in that each logical block is is executed on the OR elements from the first to the third, the first and second bit lines of the polling of the matrix column are connected to the first and second inputs of the corresponding logical block, the third input of which is the bit input of the job of the poll mode, the first and second outputs are connected to the first and second bit of the comparison conclusions by coincidence of the memory elements of the corresponding matrix column, the associative comparison resolution inputs of which are connected to the third output of the logical block, as well as to the third and interconnected the seventh inputs of the element 2 AND-OR-NOT, the second and sixth inputs of which are connected respectively to the outputs of the third and fourth elements AND, the first and second inputs of each logic block are connected respectively to the first inputs of the first and second elements OR, the second inputs of which are interconnected and are connected to the bit input of the polling mode job, and the outputs are the first and second outputs of the logic block and are connected respectively to the first and second bit terminals of the comparison by coincidence of memory elements, respectively the column of the matrix, as well as to the first and second inputs of the third OR element, the output of which is the third output of the logical block.