SU898502A1 - Storage device - Google Patents

Description

I

The image is relative to a memory device.

A random access memory is known that contains even and odd byte registers, a generation unit, even and odd byte switches, a memory unit tl.

However, if you need to work with variable word formats from the byte. and to a length greater than two bytes, the hardware costs become large.

The closest in technical essence to the present invention is a memory device with simultaneous sampling of a variable array of words, containing neck memory modules, an address register divided into parts — upper and lower, input and output information switches (ring shifters), encoders and decoders, block add one (address code converter) 2J.

However, if it is necessary to use the memory in systems that imply a change in the format of the memory in the process of working for a long time or constant work with words of different formats when solving a task, most of the switching equipment is used unproductively.

The aim of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the analysis unit is entered into the memory containing the address register, one of the outputs of which is connected to one of the inputs of the memory modules, the other inputs of which are connected to the outputs of the input word register of the word format, one of the inputs of which is connected to other outputs of the address register, other inputs of the word format analysis block are connected to the control bus, and the outputs are connected to the corresponding inputs of memory Odule and word format analysis block containing 389 I-NES elements, first and second inputs of the first, second, third and seventh ILE elements and second and third inputs of the fourth, fifth and sixth I-NOT elements are connected to one of the block inputs. analysis of the format, and the first inputs of the fourth, fifth, sixth elements AND-NOT are connected to the output of the second element AND-NOT, the outputs of the first and seventh elements are connected to the inputs of the eighth, ninth, tenth and eleventh elements, AND-NOT, the second inputs which are connected to the outputs of tr Next, the fourth, fifth, and sixth elements are NAND, and the third to the other input of the format analysis block, the outputs of the eighth, ninth, tenth and eleventh elements are connected to the outputs of the word format analysis block. FIG. I shows the block diagram of the device; FIG. 2 shows the structural scheme of the block for analyzing the format of the word. The scheme contains the locked modules of the I memory, the address register 2 divided into parts — the younger 3 and the older 4, and the outputs of the younger part 3 of the address register 2 are connected to the inputs of the memory modules, the register input spruce 5, the outputs of which are connected to the other inputs of the modules t, the output word register 6, the inputs of which are connected to the outputs of the modules I, the switch of the word format 7, the outputs 8 of which are connected to the third inputs of the memory modules I, the inputs 9 are control buses changing pho memory word storage, and inputs 10 are connected with the senior part 4 of the register 2. The device operates as follows. Before accessing the memory with a record or reading, the control potentials code B, depending on the code and

AT 2

IN 1

ABOUT

ABOUT

ABOUT

ABOUT

Drive organization

496 x 4 bytes

4,096 X 4 bytes

16.384 X I byte

8.192 X 2 bytes 2 upper order bits of the input to the inputs 10 of the block of analysis of the format of the word 7 from the upper part 4 of the address register 2, at the output 8, potentials are generated that allow access to the module or group of modules. From the lower part 3 of the address register 4, the lower bits of the address code come in for a module or group of modules whose memory is selected. One module intervenes P words of one byte length. If the number of modules is equal to T, then the storage organization may from itself represent modifications: n words with a length of f bytes; 2 n, words in length of i bytes, etc. by and. G words are one byte in length, with the multiplicity of the change in the capacity of the memory and the format of the word equal to two. You can build a block of analysis of the format of the word 7 and so that the change is capacious-,. These memories will occur with multiplicities not equal to two. On fet. Figure 2 shows an example of constructing a block of word format analysis that modifies the organization of accumulators from 16K x I bytes to 4K x 4 bytes with a multiplicity of 2 and which contains eleven I-NOT 11-21 elements. In tab. I shows the dependence of the organization of the memory on the code of the control signals for the reorganization of the word format B {, the block of analysis of the word format on the two- and three-input AND-NES elements and generates the signals yi-V4. The address bits are A12, A13, and the organization of the storage unit. Capacity of one modout is Oh, 5Kx1 bytes. There are 32 modules in total. They are organized into columns. У I-У4; Potential signals UCH-V4 arrive at the appropriate columns of the drive. In the proposed device, the hardware costs in the hardware are reduced by about ten times. Table I

table 2

The form of the invention 1. A memory that contains an address register, one of the outputs of which is connected to one of the inputs of the memory modules, the other inputs are connected to the outputs of the second word register, and the output modules of the memory module are connected to in order to increase the reliability of the device, it contains a block of analysis of the format of the word. One of the inputs of the cat connector: H0Ay with other outputs of the P Addressra, other inputs of the block of analysis of the format of the word are connected to the control bus , And - to the corresponding inputs of memory modules. 2. The device according to claim 1. This is so that the anagahs block of forms and words contains the AND-NOT elements, the first and second inputs of the first, second, third and seventh elements of the IS-NOT and the second and The third inputs of the fourth, five, and sixth elements of the NAND are connected to one of the inputs of the format analysis block, and the first inputs of the fourth, n to- the first and sixth elements are NOT connected to the output of the second element, the outputs iepioro and the seventh element ILE are connected to the first inputs of the eighth, ninth, tenth, and eleventh elements of the IS-NOT, respectively, the second inputs of which are connected to the outputs of the third and fourth, This and the sixth elements are NAND, and the third to the other input of the format analysis block, the outputs of the eighth, ninth, tenth and eleventh elements of the NAND are connected to the outputs of the Word format analysis block. Sources of information taken into account in examination I, USSR Author's Certificate No. 483705, cl. Q II С 7 / ОО, 1972. 2. USSR author's certificate N 367456, cl. 6 II С 9 / ОО, 1971 (prototype).

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Claims (2)

Claim 1. A memory device comprising an address register, one of outputs which are connected to one of the inputs of the memory modules, the other inputs koto- cerned ₂₅ connected to the outputs of the input word register and the outputs of memory modules connected to the inputs of the register output word, characterized heme that to improve the reliability _star device, it comprises analyzing unit format words, one of the inputs of which are connected to other outputs of the address register, the other inputs of the word format analysis unit connected to the control bus, and outputs - to soot etstvuyuschim inputs za- ³⁵ remembers modules. 2. The device according to π. 1. The answer is that the word format analysis unit contains AND-NOT elements, the first and second inputs of the first, second, third and seventh AND-NOT elements and the second and third inputs of the fourth, fifth and of the sixth element AND NOT connected to one of the inputs of the format analysis unit, and the first inputs of the fourth, fifth. • the sixth and sixth AND elements are NOT connected to the output of the second CLE element, the outputs of the first and seventh OR elements are connected to the first inputs of the eighth, ninth, tenth and eleventh elements of the ILE, the second inputs of which are connected to the outputs of the third> fourth, fifth and sixth elements; ILE, and the third - to another input of the format analysis unit, the outputs of the eighth, ninth, tenth and eleventh elements are NOT connected to the outputs of the Word format Analysis unit.