SU526881A1 - Device for interfacing processors with I / O channels - Google Patents

Description

one

The invention relates to the field of computer technology, in particular, to the interface devices of processors and channels, and can be used in the construction of multiprocessor computer systems with a common channel pool.

A device for interfacing an I / O channel and a processor is known, comprising a request and priority processing unit, a command receiving and interrupting unit, a situation latching unit and fault localization tests 1.

A disadvantage of the known device is the impossibility of operating the I / O channels with more than one processor, which leads to a reduction in the functionality of the device.

The closest to the invention to the technical essence and the achieved result is a device containing a communication unit with channels, a first and second communication unit with processors, the first, second and third group of device inputs-outputs connected respectively to the group of input-outputs of the device communication with channels, with groups of inputs and outputs corresponding to the first and second communication blocks with processors, the first, second and third inputs of the first and second communication blocks with processors are connected to the first, second and third outputs respectively mi block

communication with channels, the fourth and fifth outputs of which are connected to the fourth inputs of the first and second communication blocks with processors, respectively, the first and second inputs of the communication block with channels are connected to the first outputs of the first and second communication blocks with processors, respectively, and the third and The fourth inputs of the communication unit with the channels are connected to the second outputs of the first and second communication units, respectively, with the processors 2.

A disadvantage of the known device is the limited functionality due to the fact that the device does not provide the possibility of simultaneous operation of several I / O channels with several central processing units.

The purpose of the invention is to expand the functionality of the device without introducing additional commands.

The goal is achieved by the fact that the device contains additional communication units with processors, with the fifth inputs of all communication units with processors connected to the other output of the communication unit with channels, the first, second, third outputs of which are connected correspondingly with the first, second, third inputs of additional communication units with processors, the first and second outputs of which are connected respectively with the first and second groups of inputs of the communication unit

with channels, output groups of which are connected i; -i with fourth additional chipsets (; and with processors, and input / output groups of these blocks are connected with cooler groups of device inputs.

In the device, the communication unit with the channels contains the address register, the information register, the synchronization and priority unit, instructions, interrupt signals, condition code generation and associative memory nodes, with the first to fifth inputs of the group of inputs and outputs of the block connected to the first inputs respectively, the interrupt signal node, the instruction output node, the synchronization and priority node, the information registers and the address, the first and second outputs of the group of inputs and outputs of the block are connected to the first outputs, respectively, of the issuing node information and register, the address register outputs, the instruction output node, the interrupt signal node, the condition code generating node are connected to the first, second, third and sixth outputs of the block, the fourth and fifth outputs, and the group of outputs, respectively, are connected to the outputs of the synchronization node and priority, the first, second inputs and the first group of inputs of the block are connected to a group of inputs of the information register, the third, fourth inputs and the second group of inputs are connected to a group of inputs of the instruction issuing node, the second input, the first and second the outputs of the synchronization and priority node are connected respectively to the second output of the information register, to the second inputs of the information register and address register, the second input and output of the instruction output node are connected to the first outputs and the input of the associative memory, the second input and output of which are connected respectively to the first and the second inputs of the interrupt signal node.

The drawing shows the block diagram of the device.

A device for interfacing processors with I / O channels contains a communication unit 1 with channels, a communication unit with processors, address register 3, information register 4, synchronization and priority node 5, instruction node 6, interrupt signal node 7, node 8 condition code generation, associative memory 9, address processor register 10, processor information AND register, exchange synchronization node 12, instruction receiving node 13, device I / O group interrupt signal output node 14, inputs 16-20 (first to fifth respectively) p The first group of device I / O, the first 21 and second 22 outputs of the first group of device inputs / outputs, outputs 23i-23 ", 24i-24", 25i-25 ", 26i-26n, corresponding groups of device inputs-outputs, inputs 28i- 1 p, 29i-29 corresponding groups of inputs and outputs of the device.

A device for interfacing processors with

I / O channels works as follows oopaacjM.

To the remote 15 IB moves-outputs with I / O I / O channels (multiplex and selector) are connected. The parallel operation of these channels is provided by the standard hardware (priority scheme) available in the channels.

The units 2) -2 „, the number of which corresponds to the number of central processors, through groups 152-157i are connected central processors with their own operational to us. The operation of several central processors with the interface device is provided by means of switching and priorities embedded in the interface device.

Received at input 29 from the central processor, the instructions are recorded by the instruction receiving unit 13. In the absence of instructions at the nodes 13 d; other 1h-In blocks with a higher priority, the instructions are transmitted to the node 6 for issuing instructions of the communication block 1 with the channels. The address of the channel and the external device contained in the manual should be

5 recalculation into memory 9. If memory 9 contains a sign recorded when using the previous instruction that the required external device is busy, the central processor sending the instruction is issued

0, the catch code is located through the node 8 of the formation of the condition code and the node 13 on the ROCKET 26i. Memory 9 records the sign of accessing this external device. In case memory 9 does not contain an indication that the address is

5 external device, instructions from node b are sent to output 21 and further to the channel. The condition code received from the channel at input 17 through node 6 and zzel 13 of the corresponding block 2 |.-2 and communication with the processor that sent the instruction is transmitted to output 26i and then to this processor.

If it is necessary to read information from the central operative memory, the address of the cell from the input 20 enters the register 3 addresses

5 cells of the central RAM, and the request from input 18 goes to the synchronization node 5 and issues a request to access the central RAM. Depending on the value of the higher bits of the cell address, this address is sent to the output register 10 of the address of the central random access memory cell, and the request to the node 12 for synchronizing the exchange with the central operational memory of the corresponding communication unit 2i-2n with the processor. Then the address is given on output 23. The selected information from the input is received to the register P, then to the channel register 4 and the output 22 of the information.

If necessary, record information in

0, the central operative memory of the address of the cell from input 20 goes to register 3, information from input 19 to register 4, the request from input 18 to node 5. Depending on the value of the higher bits of the address, the address of the cell, information and request are sent respectively, registers 10, 11 and node 12 of block 2i and further to exits 23i, 24b and 25i. After fixing the address information registers 3, 4 and node 5 are ready to receive the next request.

If an external device has the ability to issue initiative interrupts, you must first follow the instructions, for example, "check the I / O in memory 9, fix the sign of access to this external device from this processor. The interrupt signals issued by this external device will be sent to those processors for which such a sign is fixed in memory 9.

Signs are erased in us, TI 9, according to the instruction "Stop I / O. The interrupt output signal from input 16 arrives at interrupt signal node 7 and memory 9. In us 9 it is determined but the address of the external device to which (which) processor it should be assigned. By the signal from memory 9, the interrupt from node 7 is transmitted to node 14 for outputting interrupt signals. Node 14 outputs an interrupt signal to output 27i.

The interface device greatly expands the functionality of the computing system in which it is included. The device allows you to connect I / O channels (multinlex and selector) single-processor computing systems to several central processors. This ensures the possibility of "simultaneous (multiplexed) operation of several central processors with several input / output channels and, accordingly, through them with any external devices connected to these channels. This achieves the possibility of obtaining the general field of external devices for several central processors, increased characteristics of the computer system, optimization of its structure and the possibility of a better distribution of both external devices and the efficiency of the central computers and the system as a whole. The above capabilities are implemented without modifying the hardware and introducing special commands (modifying mathematical software) into standard input-output channels and central processors of uniprocessor computing systems (for example, EC computers), which is the most significant advantage of the proposed technical solution.

And so, the proposed device expands the functionality and allows designing multiprocessor computing systems (in terms of connecting I / O channels to several central processors and creating a common field of devices) from the technical means of uniprocessor computing systems without modifying their (existing) mathematical hardware.

6 Formula is invented and

Claims (2)

1. Device for interfacing processors with I / O channels, containing a block connection with channels, the first and second communication blocks with processors, first, second and third groups of device inputs-outputs are connected respectively to the ground inputs / outputs of the communication unit with channels, with groups the inputs and outputs, respectively, of the first and second communication units with the processors, the first, second and third inputs of the first and second communication units with processors are connected respectively with the first, second and third outputs; the communication unit with the channels, the fourth and fifth outputs of which connected to the fourth inputs corresponding to the first and second communication blocks with processors, the first and second inputs of the communication unit with channels are connected to the first outputs of the first and second communication units with processors, the third and fourth inputs of the communication unit The channels are connected to the second outputs, respectively, of the nerve and second units, associated with the processors, characterized in that, in order to expand the functionality of the device, it contains additional communication units with processors, and the fifth inputs of all communication units with the processors are connected to sixth the output of the communication unit with channels, nerve, second n tert); and the outputs of which are connected respectively with the first, second and third 1 moves of the additional 11 communication blocks with processors, the first and second outputs of which connected respectively to the first and BTOpoii groups of inputs of the communication unit with channels, the output group of which is connected to the fourth inputs of additional communication units with processors, and the input-output groups of these blocks are connected to the corresponding groups of inputs of the device. 2. Device pop. 1, characterized in that the communication unit with the channels contains the address register, the information register, the synchronization and priority node, instructions, interrupt signal nodes, code generation are associated with an associative memory, and from the first to the fifth inputs of the group of inputs and outputs of the block are connected to the first inputs of the interrupt signal node, the issuing node, respectively , node snn.hronizatsin and prpor1gget. the information registers of the address, the first and BTOpoii outputs of the group of inputs and outputs of the block are connected to the first outputs of the instruction and information register, respectively, the outputs of the address register, instruction output node, interrupt signal node, and the LESS code generation node, connected to the first, second, third and the sixth outputs of the block, the fourth and fifth outputs on the ground of the outputs of which are connected to the outputs of the synchronization and priority node, the first, second inputs and the first group of block inputs are connected to the group of inputs of the information register, the third, fourth inputs and the second group of inputs are connected to the input group of the instruction output unit, the second input, the first and second outputs of the synchronization and priority node are connected respectively to the second output of the information register, to the second inputs of the information register and the address register, the second the input and output of the instruction output unit are connected to the first output and the input of the associative memory, the second input and output of which connected respectively with the first and with the second inputs of the interrupt signal node. Sources of information taken into account in the examination: 1. Issues of radio electronics, a series of "Electronic computer technology; issue 1, 1973, p. 89, fig. five. 2.Specialized computing complex. Technical description. 1ЦК1.700.010. T01, ed. 2--73 (prototype). 2 ,,