SU1076947A1 - Semiconductor storage - Google Patents

Abstract

A semiconductor memory device containing the first and second drives, the inputs of the first groups of which are the SiH inputs of the first and second groups of the device, the inputs of the second groups of the first and second drives, respectively, the inputs of the first decoder are the inputs of the third group devices, and the inputs of the first group of the second decoder are the inputs of the fourth group of the device, characterized in that, in order to simplify the device, the outputs of the first decoder connected to the inputs of the second group of the second decoder.

Description

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4 to The invention relates to computing and can be used in the design of integrated semiconductor memory devices, microprocessors, microcomputers, microcalculators, etc. The semiconductor memory device is known that contains one drive, row and column decoders that allow you to store unchanged information I . The disadvantage of this device is the inability to change information in the device. Closest to the present invention is a semiconductor integral memory device containing a RAM with a capacity of 128 8-bit numbers and a ROM with a capacity of 2048 8-bit numbers. Each of these memories has an in- tip; formations, row decoders ,, post decoders, address buses. The RAM and ROM are included in the general memory field of the microcomputer, and simultaneous access to them is impossible. The inputs of the row decoder are connected to the corresponding address buses, and the outputs are connected to the buses of the RAM drive and ROM. The inputs of the decoder columns of the RAM drives and the ROM are also connected to the corresponding address buses, their control inputs are from the control one, the outputs, the outputs. with the corresponding tire columns on the RAM and ROM devices with a correspondingly f2. However, the known technical solution is redundant and leads to high hardware costs due to the presence of two complete line decoders. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in a semiconductor memory device containing first and second drives, the inputs of the first groups of which are respectively the inputs of the first and second groups of the device, the inputs of the second groups of the first and second drives, respectively, the inputs of the first and second decoders. the first decoder are inputs to the third group of the device, the inputs of the first group of the second decoder are the inputs of the fourth group of the device, the outputs of the first decoder are connected to the input and a second group of the second decoder. The drawing shows a block diagram of a semiconductor storage device. The semiconductor coupler contains the first 1 and second 2 drives, the inputs of the first groups of which are, respectively, the inputs of the first 3 and second 4 groups of the device. The inputs of the second groups of the first I and second 2 accumulators are connected to the outputs of the first 5 and second 6 decoders, the inputs of the first 5 decoder are the inputs of the third device group 7, the inputs of the first group of the second decoder are the outputs of the first 5. The pyrethra is connected to the inputs of the second group of the second decoder, One of the drives can be an operative drive, and the other can be a drive of the same type. In this case, the drive with a large information capacity should be the second. The binary code of the row (column) number is input to inputs 7 and B, the column number (s) is input to inputs 3 and 4, as well as the control signals for selecting the corresponding storage device. If drives have the same number of address buses arriving at inputs 3 and 4, then they can be combined. Semiconductor memory device operates as follows. If it is necessary to access one of the accumulators I or 2, the corresponding inputs 3 and 7 or 4, 7 and 8 are given address and control signals. In this case, when accessing the accumulator 2 using the first decoder 5, the first decryption stage is performed, and then. Considering that drive 2 is larger than drive}, the selection of the desired row (column) is already performed in decoder 6. A technical and economic advantage is to reduce the hardware costs of decrypting information collection from drive 2. For these purposes, a decoder is used.

Claims (1)

SEMICONDUCTOR MEMORY DEVICE containing the first and second drives, the inputs of the first groups of which are respectively the inputs of the first and second groups of the device, the inputs of the second groups of the first and second drives are connected respectively to the outputs of the first and second decoders. the inputs of the first decoder are the inputs of the third group of the device, and the inputs of the first group of the second decoder are the inputs of the fourth group of the device, characterized in that, in order to simplify the device, the outputs of the first decoder are connected to the inputs of the second group of the second decoder.