SU907587A1 - Information-correcting storage device - Google Patents

Description

one

This invention relates to memory devices.

A memory device with information correction is known, which contains a number register, an address register, a decoder, a multi-bit drive, and an information block 1 block.

A disadvantage of this device is the complexity of the information correction block.

The closest to the proposed technical solution is a memory device with information correction, which contains a block for storing codes for faulty addresses and an address register, which is connected via a descrambler to a multi-digit ferrite core storage core consisting of main and additional fields, inputs / outputs which are connected to the register number 2.

The disadvantage of this device is low reliability, due to its complexity and the need to have a polydischarge additional drive field to completely re-switch a defective word, regardless of the number of defects in a word.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved in that a memory device with information correction containing a main drive, an address register, an address decoder, a number register, and a first additional drive whose inputs are connected to the inputs of the address register and are inputs to the device, where the addresses of the address decoder are connected with the outputs of the register of the address, and Bbixoj i with the address inputs of the main storage device, the outputs of the register of the number are connected to one

15 of the I1 {formational inputs of the main accumulator, the second additional accumulator, the groups of AND elements and the OR elements are introduced, and the inputs of the second additional accumulator are connected to the terminals of the first

Claims (2)

20 additional accumulators, direct outputs of the second additional accumulator are connected respectively to the first inputs of elements AND of the first group, and inverse outputs 3809 to the first inputs of elements AND of the second and third groups, the second inputs of elements AND of the first group are connected respectively to one of the outputs of the main accumulator, and the second inputs of the elements AND the second soil are with the other outputs of the main accumulator, the outputs of the elements AND of the first and second groups are connected to the corresponding inputs of the elements OR, the outputs of which are connected according to venno from the register number input, a second input of the AND of the third group are connected respectively to the outputs of the register, and outputs - to the corresponding inputs of the AND of the fourth group, KOTOjHjx outputs respectively connected to other information inputs osisdanogo accumulator. The drawing shows a functional diagram of the proposed device. The device contains an address register, an address decoder 2, a main drive 3, a first additional drive 4 intended for storing address codes of faulty words, a second additional drive 5 intended for numbers of un-equal digits, register 6 tsla, first 7, second 8, third 9 and the fourth 10 of the AND group of elements and the OR 11 elements. The drawing also indicates corrective digits 12 of the main accumulator. The inputs of the scooper 5 are connected to the outputs of the accumulator d 4. The direct outputs of the accumulator 5 are connected to the first inputs of the input 1 and 7, respectively, and the inverse outputs to the first inputs of the elements 8 and 9. The second inputs of the elements 7 7 are connected respectively to one of the outputs drive 3, and the second inputs of elements AND 8 - with each other outputs of storage device 3. The outputs of elements AND 7 and 8 are connected respectively to the inputs of the elements OR P, the outputs of which are connected respectively to the inputs of register 6. The second inputs of elements AND 9 are output: exits reg tra 6, and outputs - to the corresponding inputs of AND gates 10, whose outputs are respectively soedaneny with other data inputs of the accumulator 3. Additional drives 4 and 5 may be formed on programmable chips semitraile Vodnikova. The number of correction bits 12 corresponds to the maximum number of defects in a word recorded in the main accumulator 3, and the capacity of each of the correction bits 12 is equal to the number of defective elements in the corresponding word bits. The device works as follows. Writing a number is performed by transferring information from register 6 to one of the information inputs of the main accumulator 3. In the absence of defective elements in accumulator 3, signals from the direct outputs of accumulator 5 allow operation of the And 7 elements, with the result that the address selected in the register 1 , the number is transferred from one of the outputs of accumulator 3 to register 6. If there are defective elements in one or several bits of the word, accumulator 3, whose address is stored in accumulator 4, and the numbers of faulty bits are in accumulator 5, signals with the inverse outputs of the accumulator 5 allow the operation of the corresponding elements B and 9. As a result, simultaneously with the word read from the accumulator 3, from its corrective bits 12, information is selected that should be contained in the defective elements of this word. In this way, the readable word is corrected. In this case, information is read from defective bits of accumulator 3 is blocked with the help of the corresponding elements AND 7. Recording information in the correction bits 12 of storage 3 with the outputs of register 6 is carried out through elements 9 and 10. The technical and economic advantage of the proposed device lies in its more high compared with the known reliability. Claims A memory device with information correction containing a main drive, an address register, an address decryptor, a number register, and a first additional drive whose inputs are connected to the inputs of the address register and are inputs to the device, the addresses of the address decoder being connected to the outputs of the address register, and the output - with address inputs of the main drive; the number register outputs are connected to one of the informational inputs of the main storage device, characterized in that, in order to increase the reliability of the devices .., it contains the second additional storage device, the groups of AND elements and the OR elements, and the inputs of the second additional storage device are connected to the outputs of the first additional storage device, My outputs of the second additional storage device are connected respectively to the first inputs of the elements AND the first group. and the inverse outputs to the first inputs of the elements of the second and third groups, the second inputs of the elements of the first group and are connected respectively to one of the outputs of the main terminal. and the second inputs of the AND elements of the second group are with other outputs of the main storage unit, the outputs of the AND elements of the first and second groups are connected respectively to the inputs of the OR elements, the outputs of which are connected respectively to the number register inputs, the second inputs of the AND elements of the third group are connected respectively to the number register outputs, and the outputs to the corresponding inputs of the elements of the fourth group, the outputs of which are connected respectively with the other information inputs of the main storage unit. Sources of information taken into account when zspertnz, 1. USSR Author's certificate number 492935, cl. G 11 C 29/00, 1976. 2. Chakho L.M. Capacity of an additional floor of a storage device of an operational memory device with blocking faulty addresses. - Issues of radio electronics, ser. EVT, vol. 6, 1969 (prototype).