JP3265993B2 - Sorting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sort processing device for performing a sort process for rearranging a large amount of sort data in a specified order.

[0002]

2. Description of the Related Art As a conventional example of a sort processing apparatus, there is a sort processing apparatus disclosed in JP-A-5-274117.
This is shown in FIG. In FIG. 8, reference numerals 1-1 to 1-n denote comparison processing units (SE) which compare the magnitudes of the values of the two input sort data. Note that the comparison processing unit 1-1 corresponds to a first comparison unit, and the comparison processing unit 1-2 corresponds to a second comparison unit.

[0003] Also, the sort data means the comparison processing unit 1-
1 to 1-n indicate data to be compared. A data group including a plurality of sort data is input to the comparison processing units 1-1 to 1-n, and a comparison process is performed on two sort data in the input data group. Change the order of the sort data that constitutes.

Reference numerals 2-1 to 2-n denote storage units.
-1 and comparison processing unit 1-1, storage unit 2-2 and comparison processing unit 1
-2 is connected to each of the storage units 2-1 to 2-n and each of the comparison processing units 1-1 to 1-n.

Reference numerals 4-1 to 4-n denote internal storage units. The comparison processing unit 1-1 stores the internal storage unit 4-1 in the comparison processing unit 1-2.
Has an internal storage unit 4-2 so that each comparison processing unit 1-
1 to 1-n have respective internal storage units 4-1 to 4-n. 3
-1 to 3-n are sorting processing basic units, and the comparison processing unit 1
-1 to 1-n, storage units 2-1 to 2-n, and internal storage units 4-1 to 4-n. Reference numeral 5 denotes a sort processing device, which includes a plurality of sort processing basic units 3-1 to 3-n.

Next, a sorting process as an operation of the sorting device 5 shown in FIG. 8 will be described with reference to FIG. Note that the sort processing refers to a processing operation in which the sort processing device 5 rearranges the sort data constituting the input data group in a required order. A data group composed of a plurality of sort data is input to the sort processing device 5. The plurality of sort data forming the data group are first input to the sort processing basic unit 3-1 of the sort processing device 5 in order.

While the plurality of sort data constituting the data group input to the sort processing device 3-1 are sequentially sent from the sort processing basic unit 3-1 to the sort processing basic unit 3-n, each sort data is sorted. The order in the data group is changed by each of the comparison processing units 1-1 to 1-n included in the processing basic units 3-1 to 3-n. Then, the sort data constituting the input data group is sorted in a predetermined order by passing through the respective sort processing basic units 3-1 to 3-n.

In FIG. 9, the sort data constituting the data group input to the sort processing device 5 is rearranged in a predetermined order, for example, in descending order, through a plurality of comparison processing units 1-1 to 1-n. It shows how it is being done.

For example, the data group input to the sort processing device 5 is 14, 9, 10, 7, 3, 2, 6, 1
1, 1, 13, 4, 9, 12, 5, 15, and 8, respectively. These sort data are sorted in the indicated order in the sort processing device 5.
Is input to the comparison processing unit 1-1. The descending order is
The order in which numbers go from large to small.

The sort processing device 5 includes a sort processing basic unit 3-
1 to 3-n, and the comparison processing unit 1-1 of the sort processing basic unit 3-1 in the sort processing apparatus 5 first stores the data groups (14, 9, 10, 7, 3, 2). , 6, 11,
1, 13, 4, 9, 12, 5, 15, 8) are input. This is the part of the comparison processing unit 1-1 in FIG.

When a data group is input to the comparison processing unit 1-1, the comparison processing unit 1-1 combines the sorted data constituting the data group two by two in the order in which they were input, and creates double data. . Then, the comparison processing unit 1-1 compares the size of the two sort data constituting the two-piece data with respect to each two-piece data, and compares each sort data based on the result of the comparison processing. Output to the unit 1-2.

The processing operation from the input of the sort data constituting the data group to the output of the comparison processing unit 1-1 to the output thereof will be further described. Is entered. Then, the sort data “14” input to the comparison processing unit 1-1 is recorded in the storage unit 2-1 connected to the comparison processing unit 1-1.

Next, the sort data "9" is input to the comparison processing unit 1-1. The sort data “14” recorded in the storage unit 2-1 and the sort data “9” input to the comparison processing unit 1-1 after the sort data “14” are compared by the comparison processing unit 1-1. A comparison process for comparing the magnitudes of the values is performed.

In the comparison processing unit 1-1, the sort data "14"
As a result of comparison processing between the data and the sort data “9”, 2
Among the two sort data, the sort data “14” having a larger value is first compared with the comparison processor 1-1 to the comparison processor 1
2 is output. On the other hand, the sort data “10” is subsequently input to the comparison processing unit 1-1. Comparison processing unit 1-1
The sort data “10” newly input to the storage unit 2
-1 is recorded.

After the sort data "14", the sort data "9" is output from the comparison processing unit 1-1. At this time, the sort data “7” is input to the comparison processing unit 1-1. The sort data “7” input to the comparison processing unit 1-1 is compared with the sort data “10” recorded in the storage unit 2-1 by the comparison processing unit 1-1. Then, the comparison processing unit 1-1 outputs the sort data “10” and “7” to the comparison processing unit 1-2 in the order described, based on the result of the comparison processing in the comparison processing unit 1-1. .

When such comparison processing is repeated for each pair of data constituting the data group, the comparison processing section 1-1
, The descending two-piece data (14,...) Sorted in descending order between the two sorted data constituting the two-piece data
9), (10, 7), (3, 2), (11, 6), (1
3, 1), (9, 4), (12, 5), (15, 8)
Are output to the comparison processing unit 1-2 in the order described. This is the part of the comparison processing unit 1-2 in FIG.

The comparison processing unit 1-2, which is connected to the comparison processing unit 1-1 and receives the descending double data output from the comparison processing unit 1-1, receives the two descending double data sets. Then, a comparison process is further performed to create four sets of descending data in which the four sort data items are arranged in descending order and are combined into one set, and output to the comparison processing unit 1-3.

The operation of the comparison processing unit 1-2 for converting two sets of data in descending order into one set of four data in descending order will be described below. First, the comparison processing unit 1-2 records the input first descending double data (14, 9) in the storage unit 2-2 connected to the comparison processing unit 1-2 in order. continue,
In the comparison processing unit 1-2, the second set of descending double data (1
0, 7) are input in order.

Therefore, in the comparison processing unit 1-2, the storage unit 2
-2, the sort data "14" which is the first data having a large value in the first descending double data recorded in the second descending data, and the first sort data of the second descending data (10, 7). "10" is compared. As a result of comparison processing between the first sort data “14” of the first descending double data set and the first sort data “10” of the second descending double data set in the comparison processing unit 1-2, a comparison is made. The processing unit 1-2 outputs the sort data “14”.

Subsequently, in the comparison processing unit 1-2, the sort data "9" which is the remaining data of the first descending double data and the sort data which is the first data of the second descending double data are sorted. A comparison process with the data “10” is performed. As a result of the comparison processing between the sort data “9” and the sort data “10”, the comparison processing unit 1-2 outputs the sort data “10” to the comparison processing unit 1-3.

The sort data "10" is stored in the comparison processing unit 1-2.
, The sort data “2” that is the remaining data of the third set of descending data is input to the comparison processing unit 1-2. Then, the sort data “2” input to the comparison processing unit 1-2 is recorded in the storage unit 2-2 connected to the comparison processing unit 1-2.

Subsequently, in the comparison processing unit 1-2, the sort data "9", which is the remaining data of the first descending double data, and the remaining data of the second descending double data. A comparison process with the sort data “7” is performed.

Sort data "9" and sort data "7"
As a result of the comparison processing, the comparison processing unit 1-2 outputs the sort data “9” and “7” in the order described. When the sort data “7” is output from the comparison processing unit 1-2,
The first sort data “11” of the fourth data set in descending order is input to the comparison processing unit 1-2. Comparison processing unit 1-2
Is input to the comparison processing unit 1-
2 is stored in the storage unit 2-2 connected to the storage unit 2.

As described above, when the data group input to the sort processing device 5 is output from the comparison processing unit 1-2, the four descending quadruple data (14, 10, 9, 7),
(11, 6, 3, 2), (13, 9, 4, 1), (1
5, 12, 8, 5), and output to the comparison processing unit 1-3 in the order described. This is the part of the comparison processing unit 1-3 in FIG.

Each of the comparison processing units 1-3 to 1-n performs the same comparison processing as that of the comparison processing units 1-1 to 1-2 described above. Becomes larger by 1, the number of sort data items constituting the set of descending n data output from the comparison processing unit 1-n becomes
The number of sorted data output from (n-1) in descending order (n-1) sets is twice the number of sorted data. That is, the comparison processing unit 1-n outputs 2 ⁿ sets of data in descending order. For this reason,
When the number of sort data constituting the data group input to the sort processing device 5 is 2 ⁿ or less, a predetermined descending sort process is realized.

However, when the number of sort data constituting the data group input to the sort processing device 5 is larger than 2 ⁿ , the comparison processing portions 1-1 to 1-1 of the sort processing device 5 are provided.
It is necessary to increase the number of 1-n. When increasing the number of comparison processing units 1-1 to 1-n, a new storage unit is connected to the newly provided comparison processing unit.

In the comparison processing unit 1-n, as the value of ⁿ increases, the number of sort data constituting the set of descending 2 ⁿ data output from the comparison processing unit 1-n increases. Since all sort data input to each comparison processing unit is recorded in each storage unit connected thereto, it is necessary to increase the storage capacity of the storage unit 2-n connected to the comparison processing unit 1-n. is there. The n-th comparison processing unit 1-n outputs a set of 2 ⁿ pieces of data in descending order composed of 2 ⁿ pieces of sort data.
At this time, the capacity of each sort data is L.

From these, the n-th comparison processing unit 1-n
The storage capacity that the storage unit 2-n connected to
ⁿ × L or more. In the comparison processing unit 1-n, as the value of n increases by 1, the number of sort data constituting the set of 2 ⁿ pieces of data in descending order output from the comparison processing unit 1-n doubles. For 2-n, the storage capacity must be doubled or more as the value of n increases by one.

In FIG. 8, in the storage units 2-1 to 2-n, as the value of n increases by 1, the storage capacity of the storage units 2-1 to 2-n doubles by two. Is shown. As shown in FIG. 8, the sort processing device 5 has internal storage units 4-1 to 4-n.
Sort data recorded in the storage units 2-1 to 2-n are recorded in -1 to 4-n. Then, the comparison processing unit 1-1
1 to 1-n perform a comparison process on sorted data in a predetermined range recorded in the internal storage units 4-1 to 4-n. Note that the internal storage units 4-1 to 4-n include a storage unit 2-1.
The storage capacity for storing the sort data is smaller than that of 〜2-n.

However, the internal storage units 4-1 to 4-n have a higher writing and reading processing speed than the storage units 2-1 to 2-n. In the description so far, the sort data to be sorted is a simple integer “14”,
Although the case of “9” was used, the sort data to be actually subjected to the sort processing is, for example, personnel data,
In many cases, the capacity is large enough to indicate first and last names, addresses, ages, and other contents.

The storage capacity required by a data group constituted by a plurality of sort data to be actually subjected to sort processing may be several hundred bytes to several tens Mbytes. When the storage capacity of the sort data to be sorted is large, the comparison process performed by the comparison processing units 1-1 to 1-n is to sort the sort data recorded in the storage units 2-1 to 2-n into a plurality of ranges. And each range is sequentially stored in the internal storage unit 4.
-1 to 4-n, and the internal storage units 4-1 to 4-n
The comparison process is performed on a predetermined range of the sort data recorded in n. If no difference is found as a result of the comparison processing, the next predetermined range is divided from the storage units 2-1 to 2-n to the internal storage units 4-1 to 4-n.
n, and the next comparison process is performed.

[0032]

The comparison processing units 1-1 to 1-n of the conventional sorting apparatus 5 perform comparison processing of input sort data, temporary storage of input sort data, and comparison processing. Simple processing such as outputting a comparison result based on the result is performed. Therefore, the comparison processing units 1-1 to 1-n where these simple processes are performed are integrated in one integrated circuit,
It has been considered that the sort processing apparatus 5 should be downsized.

However, in the conventional sort processing device 5, a plurality of comparison processing units 1-1 such as the comparison processing unit 1-1 and the storage unit 2-1 and the comparison processing unit 1-2 and the storage unit 2-2. ~ 1-n
Each of the storage units 2-1 to 2-n is connected to each of them. These storage units 2-1 to 2-n
Often records a relatively large amount of sort data such as corporate personnel data and bank account data, so that the storage capacity of the storage units 2-1 to 2-n also becomes large, and the comparison processing unit 1-1-2. It has been difficult to integrate them together with 1-n on the same integrated circuit.

Therefore, it has been considered that only the comparison processing units 1-1 to 1-n are integrated in one integrated circuit, and the storage units 2-1 to 2-n are provided separately. In this case, the number of comparison processing units 1-1 to 1-n connected to each of the comparison processing units 1-1 to 1-n and each of the storage units 2-1 to 2-n is equal to that of the comparison processing units 1-1 to 1-n. External signal lines are required, and pins of the integrated circuit connected to the signal lines need to be provided corresponding to the number of the respective comparison processing units.

However, the number of pins used for a signal line in one integrated circuit is limited, and a single integrated circuit having a large number of comparison processing units 1-1 to 1-n may be integrated into one integrated circuit. Was difficult. At the same time, it was difficult to reduce the size of the sort processing device 5.

Each of the storage units 2-1 to 2-n connected to each of the comparison processing units 1-1 to 1-n of the conventional sort processing device 5
The storage capacity of n needs to be increased as the value of n of the storage unit 2-n increases. However, the storage unit 2
The storage capacity of -1 to 2-n often becomes an integral multiple of the storage capacity of a predetermined unit, and it is difficult to freely set the storage capacity. For this reason, as the value of n of the storage unit 2-n is smaller, the storage unit often has useless storage capacity, which causes a decrease in the use efficiency of the storage units 2-1 to 2-n.

In the conventional sorting apparatus 5, since the storage capacity differs for each of the plurality of storage units 2-1 to 2-n,
Even if an attempt is made to serve also as a storage unit of a plurality of processing devices as a storage unit of a device that performs another process different from the sort process, a storage unit having a large value of n in the storage unit 2-n and a large storage capacity, for example, It was difficult to use only the storage unit 2-n. For this reason, since many storage units that cannot be used except for the sort processing device are provided, it is difficult to realize the downsizing of the sort processing device by combining the devices. The present invention has been made in view of these problems, and has as its object to obtain a sort processing device 5 that can easily integrate a large number of comparison processing units 1-1 to 1-n on the same integrated circuit. And

Further, the present invention is applicable to a plurality of comparison processing units 1-
By integrating 1-1-n on the same integrated circuit,
It is an object to reduce the size of the sort processing device 5. A further object of the present invention is to provide a sort processing device 5 that can efficiently use the storage unit without giving the storage unit an extra storage capacity.

[0039]

According to the present invention, there is provided a sort processing apparatus in which a predetermined number of sort data to be sorted is input, a first access signal, and a first access signal and a predetermined number of input sort data. A first comparison unit that outputs a first predetermined number of sort data in a predetermined order, and is connected to the first comparison unit and receives a predetermined order of sort data output from the first comparison unit, A second access signal, a second comparison unit that outputs a second predetermined number of sort data larger than the first predetermined number in the input sort data in a predetermined order, and a first and a second comparison unit. An interface commonly connected to the comparing unit, receiving the first and second access signals output from the first and second comparing units, and outputting a processed signal based on the input first and second access signals Section and interface section Is continued, the recording or reading operation based on the output processed signal from the interface unit is one that comprises a storage unit to be performed.

Also, in the sorting apparatus according to the present invention, the second comparing section may sort the second predetermined number of sort data twice as large as the first predetermined number in the input sort data in a predetermined order. Is output.

Further, the interface unit of the sorting apparatus according to the present invention records the sort data input to the first comparing unit in the storage unit based on the first access signal output from the first comparing unit. Or, the sort data recorded in the storage unit is read out to the first comparison unit, and based on the second access signal output from the second comparison unit, the sort data input to the second comparison unit is recorded. Recorded in the department,
Alternatively, the sort data recorded in the storage unit is read out to the second comparison unit.

Further, the sort processing device according to the present invention is arranged such that the sort data input to the first and second comparison units are stored in different storage units in correspondence with the first comparison unit or the second comparison unit. This is recorded in the address.

Further, the interface unit of the sorting apparatus according to the present invention inputs the signals to the first and second comparison units based on the first and second access signals output from the first and second comparison units. A second storage unit in which the sorted data is recorded and the speed of the recording and reading processing is higher than that of the storage unit.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 of the Invention FIG. 1 shows an embodiment of the sorting apparatus according to the present invention. In FIG. 1, reference numeral 2 denotes a storage unit. Reference numeral 6 denotes a memory access interface unit serving as an interface unit, which is connected to the storage unit 2.

The memory access interface unit 6
Is commonly connected to each of the comparison processing units 1-1 to 1-n, and performs a process of writing or reading sort data to or from the storage unit 2 according to an access signal output from each of the comparison processing units 1-1 to 1-n. Output a signal.

In the conventional sort processing device 5, each of the comparison processing units 1-1 to 1-n has an interface device (not shown), and each of the comparison processing units 1-1 to 1-n ,
Storage units 2-1 to 2-n connected to each of the comparison processing units 1-1 to 1-n via an interface device (not shown).
An access, which is a processing operation such as writing or reading of sort data, is performed on n.

The access signal output from each of the comparison processing units 1-1 to 1-n includes a number for identifying the comparison processing unit 1-1 to 1-n which has output the access signal, and each comparison such as writing and reading. The access contents which are the processing objects of the processing units 1-1 to 1-n, the access source indicating the location of the sort data to be processed, the access destination indicating the recording destination of the sort data to be processed, and the access indicating the data length of the sort data It consists of data such as size.

The comparison processing units 1-1 to 1-1 of the first embodiment
n are stored in the internal storage unit 4-1 by the comparison processing unit 1-1.
And internal storage units 4-1 to 4-n such that the comparison processing unit 1-2 has the internal storage unit 4-2. Also, the sort processing basic units 3-1 to 3-n according to the first embodiment.
Are the comparison processing units 1-1 to 1-n and the internal storage units 4-1 to
4-n.

Further, the sort processing device 5 of the first embodiment includes a storage unit 2, a memory access interface unit 6,
And the sorting basic units 3-1 to 3-n.
The storage unit 2 records the sort data input to the comparison processing units 1-1 to 1-n at different addresses based on the input memory access signals output from the comparison processing units 1-1 to 1-n. Is done.

The storage unit 2 of the first embodiment corresponds to a combination of the storage units 2-1 to 2-n of the conventional example, and FIG. 2 shows this. As shown in FIG. 2, the inside of the storage unit 2 stores addresses 7-1 to 7- according to the storage capacity required by the comparison processing units 1-1 to 1-n.
It is divided into n regions.

When the sort data is input, each of the comparison processors 1-1 to 1-n outputs an access signal, and outputs the input sort data to the memory access interface unit 6.
Are recorded in areas 7-1 to 7-n allocated to the respective comparison processing units 1-1 to 1-n.

That is, the storage areas 7-1 to 7-n divided by the addresses in the storage section 2 correspond to the storage areas 7-1 and 2-1 and the storage areas 7-2 and 2-2. Thus, it corresponds to the storage units 2-1 to 2-n of the conventional example.

The storage capacity of the storage unit 2 must be equal to or greater than the sum of the storage capacities of the storage units 2-1 to 2-n of the conventional example. In FIG. 1, the same or corresponding parts as those of the conventional example shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted, and parts different from FIG. 8 will be described.

Next, the operation of the first embodiment shown in FIG. 1 will be described with reference to FIGS. By providing the memory access interface unit 6, the sort processing device 5 of the present invention controls access to the storage unit 2 based on the access signals output from each of the comparison processing units 1-1 to 1-n.

The access signal output from the comparison processing unit 1-1 corresponds to a first access signal, and the access signal output from the comparison processing unit 1-2 corresponds to a second access signal.

First, at time f in FIG. 4, the access signal output from the comparison processing unit 1-3 to the memory access interface unit 6 includes “the comparison processing unit 1-3, the write and the internal storage unit 4-3. Address A, address A 'of storage unit 2, data length] and [Comparison unit 1-3, readout, address B of storage unit 2, address B' of internal storage unit 4-3, data length].

The memory access interface unit 6 includes:
The access signal output from each of the comparison processing units 1-1 to 1-n is input. Further, the memory access interface unit 6 to which the access signal is input, based on the input access signal, compares each of the comparison processing units 1-1 to 1-n and the storage unit 2.
, Processing such as reading and writing of sort data.

FIG. 3 shows processing operations performed on the storage unit 2 by the comparison processing units 1-1 to 1-3, and the time which is the timing of the processing operation. Comparison processing unit 1-
The processing operations of 1-1 to 1-3 refer to comparison processing units 1-1 to 1-3
Is stored in the storage unit 2 via the memory access interface unit 6.
The operation of writing and reading sort data to and from the memory will be described. In the figure, “W” indicates writing to the storage device 2 and “R” indicates reading from the storage device.

FIG. 4 shows the comparison processing units 1-1 to 1-1 shown in FIG.
FIG. 5 shows the processing operation of the comparison processing unit 1-2 from among the processing operations of 1-3. FIG. 4 showing the processing operation of the comparison processing unit 1-2 includes sort data input to the comparison processing unit 1-2, sort data recorded in the storage unit 2, and memory access by the comparison processing unit 1-2. The processing operation performed on the storage unit 2 via the interface unit 6 is shown.

FIG. 4 shows two sorts of data to be compared by the comparison processing unit 1-2 and sort data output from the comparison processing unit 1-2. Further, these facts are shown every time c to u.

The comparison processing unit 1-2 receives the descending two-piece data output from the comparison processing part 1-1, and creates one descending four-piece data from the input two descending two-piece data. Is done. The descending quadruple data generated by the comparison processing unit 1-2 is output to the comparison processing unit 1-3.

At each time in FIG. 4, the operation processing of the comparison processing unit 1-2 until two sets of descending data are created from two sets of data in descending order will be described. At time c, the comparison processing unit 1-2 receives the sort data “14”, which is the first data of the first data set in descending order. Then, the sort data “14” input to the comparison processing unit 1-2 is recorded in the storage unit 2 via the memory access interface unit 6.

At time d, the comparison processing unit 1-2 includes:
Sort data “9”, which is the second data of the first descending data set, is input. Then, the input sort data “9” is also recorded in the storage unit 2 via the memory access interface unit 6.

At time e, the comparison processing unit 1-2 includes:
Sort data “10”, which is the first data of the second set of descending data, is input. Then, the input sort data “10” is recorded in the storage unit 2 via the memory access interface unit 6.

When the sort data “10”, which is the first data of the second set of data in descending order, is input to the comparison processing unit 1-2, the comparison processing unit 1-2 The sort data “14”, which is the first data of the first set of data in descending order, is read through the access interface unit 6.

Then, the sort data "10" and the sort data "14" input to the comparison processing unit 1-2 are compared by the comparison processing unit 1-2 in terms of the magnitudes of the numerical values. In the column of the operation of the storage unit at the time e in FIG. 4, the description “read sort data '10'” together with “write sort data '10'” means that the data capacity of the sort data is This is a processing operation in the case of being large.

At time f, the comparison processing unit 1-2 outputs the sort data “14” based on the result of the comparison processing performed at time e. Further, the comparison processing unit 1-2 transfers the sort data “9”, which is the remaining data of the first set of data in descending order, from the storage unit 2 to the comparison processing unit 1-3 via the memory access interface unit 6. read out.

Then, the comparison processing section 1-2 performs a comparison process on the sort data "9" and the sort data "10". At this time, the comparison processing unit 1-2 stores the sort data “1”, which is the first data of the second data set in descending order.
Subsequent to “0”, the sort data “7”, which is the remaining data of the second set of data in descending order, is input.

The input sort data “7” is recorded in the storage unit 2 via the memory access interface unit 6. At time g, the comparison processing unit 1-2 sorts data “1” based on the result of the comparison processing performed at time f.
"0" is output.

Further, the comparison processing unit 1-2 performs the second descending order 2
Sort data "7" which is the remaining data of the individual set data
From the storage unit 2 to the comparison processing unit 1-3 via the memory access interface unit 6. Then, the comparison processing unit 1-2 performs a comparison process on the sort data “7” and the sort data “9”.

At this time, the sort data “3”, which is the first data of the third data set in descending order, is input to the comparison processing unit 1-2. Input sort data "3"
Is recorded in the storage unit 2 via the memory access interface unit 6.

At time h, the comparison processing unit 1-2 outputs the sort data “9” based on the result of the comparison processing performed at time g. At this time, the comparison processing unit 1-2 stores the remaining data of the third descending double data following the sort data "3" which is the first data of the third descending double data. Sort data “2” is input. The input sort data “2” is recorded in the storage unit 2 via the memory access interface unit 6.

At time i, the sort data which has not yet been output from the comparison processing unit 1-2 among the first descending two-piece data and the second descending two-piece data constituting the descending four-piece data. "7" is output. Also, the comparison processing unit 1-2
, Sort data “11”, which is the first data of the fourth data set in descending order, is input.

The input sort data “11” is recorded in the storage unit 2 via the memory access interface unit 6. Further, the comparison processing unit 1-2 reads the sort data “3”, which is the first data of the third set of descending data recorded in the storage unit 2. Then, the comparison processing unit 1-2 performs a comparison process on the sort data “3” and the sort data “11”.

In the comparison processing unit 1-2, the processing operation shown in time c to time i is repeated, and one set of four descending data is output from two sets of data in descending order input to the comparison processing unit 1-3. Is created. The descending quadruple data created by the comparison processing unit 1-2 is output to the sort processing basic unit 3-3 including the comparison processing unit 1-4.

In the above description, the case where the sort data is a simple integer has been described. However, generally used sort data has a certain capacity such as corporate personnel data and bank account data. When the comparison processing units 1-1 to 1-n perform a comparison process on the sort data having a certain capacity, the target sort data is divided into a plurality of pieces, and the sorted data is sorted within a predetermined range. Comparison processing is performed on the data.

If no difference appears even if the comparison processing is performed within this predetermined range, the comparison processing sections 1-1 to 1-n
Performs the comparison process again on the next predetermined range for the sort data.

Even if the comparison processing units 1-1 to 1-n perform comparison processing on a predetermined range of sorted data having a large capacity, there is a difference between the values of the two sorted data to be compared. If not, first, the sorted data in the predetermined range subjected to the comparison processing is stored in the comparison processing units 1-1 to 1-n, and the predetermined range next to the sorted data is stored in the memory access interface unit 6. Via the storage unit 2 via the memory.

Then, comparison processing is performed again on the newly read sort data in the predetermined range. As a result of the comparison processing performed by the comparison processing units 1-1 to 1-n, if no difference appears again in the comparison result, the next predetermined range of sorted data is stored in the storage unit via the memory access interface unit 6. 2 and perform a similar comparison process. If no difference appears in the comparison result, this series of processing is repeated.

For example, if sort data requiring a larger storage capacity than the internal storage units 4-1 to 4-n of the comparison processing units 1-1 to 1-n is to be compared, this sort Data is recorded in the internal storage units 4-1 to 4-n within a recordable range. The internal storage units 4-1 to 4-1
The comparison processing units 1-1 to 1-n perform comparison processing on the sort data in the range recorded in 4-n.

If no difference is found even after the comparison processing is performed, the comparison processing is performed on the remaining sorted data not recorded in the internal storage units 4-1 to 4-n. The sort data of the corresponding portion is read from the section 2 via the memory access interface section 6.

As described above, in the memory access interface unit 6 of the sort processing device 5 of the first embodiment, the comparison processing units 1-1 to 1-n of the conventional sort processing device 5 A plurality of interface units (not shown) provided to access 2-n are integrated into one.

The comparison processing units 1-1 to 1-n included in the sort processing device 5 according to the first embodiment are based on comparison processing for two input sort data, temporary storage of the input sort data, and comparison processing. Simple processing such as output of the comparison result is performed.

In the memory access interface section 6 of the sorting apparatus 5 of the first embodiment, the memory access interface section 6 accesses based on the access signals output from the respective comparison processing sections 1-1 to 1-n. Simple processes such as a process of generating an access address as a destination of the storage unit 2 and a process of transferring sort data between each of the comparison processing units 1-1 to 1-n and the storage unit 2 are performed.

As described above, since the comparison processing units 1-1 to 1-n and the memory access interface unit 6 perform simple processing, they can be easily integrated on the same integrated circuit. Then, the storage units 2-1 to 2-n divided into a plurality in the conventional sort processing device 5 are combined into one storage unit 2 in the sort processing device 5 of the first embodiment.

In the integrated storage unit 2, when the sort data output from each of the comparison processing units 1-1 to 1-n is recorded, the address where the sort data is recorded is stored in each of the comparison processing units 1. By changing according to -1 to 1-n,
It corresponds to a plurality of comparison processing units 1-1 to 1-n.

As described above, the sort processing device 5 of the first embodiment includes one storage unit 2 that can be shared by each of the comparison processing units 1-1 to 1-n, and the conventional sort processing device 5 includes. The plurality of storage units 2-1 to 2-n are integrated into one, and corresponded to each of the storage units 2-1 to 2-n by an address. For this reason, a storage unit of a predetermined unit included in each of the storage elements constituting each of the storage units 2-1 to 2-n has an appropriate storage capacity for each of the storage units 2-1 to 2-n having an extra storage capacity. The storage capacity can be provided, and the extra storage capacity can be reduced from the storage unit of the sort processing device.

Further, in the sort processing device 5 of the first embodiment, one memory access interface unit 6 that can be shared by each of the comparison processing units 1-1 to 1-n, and each of the comparison processing units 1-1 to 1-n n, the number of signal lines connecting the integrated circuit and the storage unit 2 can be reduced from only the number of integrated comparison processing units 1-1 to 1-n. It is possible to integrate them into one, and it is easy to integrate the plurality of comparison processing units 1-1 to 1-n into one integrated circuit without being restricted by the number of input / output pins of the integrated circuit. .

Further, since it is easy to integrate the plurality of comparison processing units 1-1 to 1-n included in the sort processing device 5 of the first embodiment, the size of the sort processing device 5 can be easily reduced.

The difference in the degree of integration of the comparison processing units 1-1 to 1-n between the conventional sort processing device 5 and the sort processing device 5 of the first embodiment, which is caused by the restriction due to the number of input / output pins of the integrated circuit, is as follows. This will be specifically described below. For example, in the conventional sorting device 5, two integrated processing units 1-
Assume that integration of 1 to 1-2 is possible. At this time, two signal lines provided between each of the comparison processing units 1-1 and 1-2 and each of the storage units 2-1 and 2-2 are assigned to input / output pins of the integrated circuit. Shall be. That is, in the conventional sort processing apparatus 5, each of the comparison processing units 1-1 to 1-2 uses one input / output pin.

However, in the sort processing device 5 of the first embodiment, the common memory access interface unit 6 is connected to each of the comparison processing units 1-1 to 1-2, so that the comparison processing units 1-1 to 1-1 are connected. Since each of the two can share two input / output pins, the data transfer capability of the sort processing device 5 of the first embodiment is twice that of the conventional sort processing device 5. In addition, by providing the memory access interface unit 6 in the sort processing device 5 of the first embodiment, the sort processing device 5 of the first embodiment can include the storage unit 2 having a high processing capability.

It is assumed that the processing capacity of the storage unit 2 provided in the sorting apparatus 5 of the first embodiment is twice the processing capacity of the storage units 2-1 to 2-n provided in the conventional sorting apparatus 5. . Then, the sort processing device 5 of the first embodiment is four times as large as the conventional sort processing device 5 due to the improvement of the data transfer capability by the memory access interface unit 6 and the improvement of the processing capability of the storage unit 2 by the storage unit 2. Comparison processing unit 1-
1 to 1-n can be integrated in one integrated circuit.

The memory access interface unit 6 of the sort processing device 5 of the first embodiment is different from the conventional sort processing device 5 in that each of the comparison processing units 1-1 to 1-n is replaced by each of the storage units 2-1 to 2-n. In this example, a plurality of interface units (not shown) provided for accessing n are integrated into one. That is, in the conventional sort processing device 5, for example, eight comparison processing units 1-1 to 1-8 are provided in one integrated circuit.
In the case where ICs are integrated, it is necessary to provide eight small-capacity interface units (not shown).

Therefore, the sort processing device 5 of the first embodiment
The memory access interface section 6 of the conventional sort processing apparatus 5 has a scale equivalent to eight interface sections (not shown) of the conventional sort processing apparatus 5, as long as the functions such as the processing speed are equivalent. Part (not shown)
Eight and the memory access interface unit 6 of the first embodiment
Means that there is no substantial change in the circuit scale in the integrated circuit.

However, the memory access interface unit 6 of the first embodiment, which has a circuit size of eight interface units (not shown) of the conventional device, has a complicated structure, but has a high-speed memory access such as a memory interleave. Techniques can be used, and processing operations can be performed at a higher speed than before. If the memory access interface unit 6 providing this high-speed processing operation is obtained, even if the access signals output from each of the comparison processing units 1-1 to 1-n are concentrated on the memory access interface unit 6, the sorting is performed. A decrease in the processing capacity of the processing is suppressed.

When the sort processing device of the first embodiment is provided with the memory access interface unit 6 and can access the storage unit 2 at a higher speed than the conventional sort processing device 5, it is often used for the storage unit 2. The DRAM device can be changed to a synchronous DRAM or the like that performs processing at a higher speed than the DRAM device.

The storage element used for the storage unit 2 is a DRAM
By changing from a device to a synchronous DRAM device, a memory access cycle, which is an interval for accessing the storage unit 2 as a memory, is improved from about 60 ns to about 10 ns. For this reason, the sort processing device of the first embodiment can transfer about six times the data amount of the conventional device.

The unit of data such as writing to the storage unit 2 and reading from the storage unit 2 performed by the memory access interface unit 6 included in the sort processing apparatus 5 of the first embodiment is n in the sort data unit in descending order. The data may be in units of set data (n is an integer). However, the fact that the memory access interface unit 6 accesses the storage unit 2 such as writing or reading every time an access signal is input to the memory access interface unit 6 prevents the efficiency of the processing operation of the sort processing device 5 from being improved. .

In the access processing such as writing and reading, the time required for the processing can be shortened as the data amount of data as a unit becomes larger. Therefore, if the memory access interface unit 6 is controlled to unify the data size for accessing the storage unit 2, efficient data transfer processing between the memory access interface unit 6 and the storage unit 2 can be performed. Thus, the sort processing capability of the sort processing device 5 is improved.

If the data length of the sort data input to the sort processing device 5 of the first embodiment is constant, each of the comparison processing units 1 is added to the memory access interface unit 6 of the sort processing device 5 of the first embodiment. By registering information on the data size of the access signal output from -1 to 1-n, each of the comparison processing units 1-1 to 1-n
The information about the data size can be deleted from the access signal output from the access signal, thereby simplifying the configuration of the access signal.

Further, when the data length of the sort data input to the sort processing device 5 of the first embodiment is constant,
The information about the data size of the access signal output from each of the comparison processing units 1-1 to 1-n is registered in the memory access interface unit 6 included in the sort processing device 5 of the first embodiment, whereby the storage unit 2 is registered. , First storage unit 4
−1 to 4-n and the second internal storage unit 8 can be divided into data size units registered in the memory access interface unit 6 to perform the sort data recording process. The storage units 4-1 to 4-n and the second internal storage unit 8 can be used efficiently.

Embodiment 2 of the Invention FIG. 5 shows another embodiment of the sorting apparatus 5 according to the present invention. In FIG. 5, reference numeral 8 denotes a second internal storage unit, which is provided in the memory access interface unit 6. In FIG. 5, the same or corresponding parts as those in the conventional example shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted, and the parts different from FIG.

Next, a second embodiment of the present invention shown in FIG.
Will be described. This second internal storage unit 8
It is assumed that the processing speed for reading and writing is faster than the storage unit 2. The second internal storage unit 8 has a larger storage capacity than the internal storage units 4-1 to 4-n, and has a larger data capacity than is stored in the internal storage units 4-1 to 4-n. Sort data is recorded.

The sort data subjected to the comparison processing by the comparison processing units 1-1 to 1-n is read from the storage unit 2 to the second internal storage unit 8 within a predetermined range. Then, the sorted data read into the second internal storage unit 8 is stored in the second internal storage unit 8.
Each of the comparison processing units 1-1 to 1-n in another predetermined range.
Are read into the internal storage units 4-1 to 4-n included in.

When the comparison processing units 1-1 to 1-n perform comparison processing on input sort data, the comparison processing is performed by the sort data stored in the internal storage units 4-1 to 4-n. Done for Then, only part of the sort data to be compared is stored in the internal storage units 4-1 to 4-n.
And the comparison processing is performed on the sorted data in the range recorded in the internal storage units 4-1 to 4-n, but no difference appears in the result of the comparison processing,
The comparison processing units 1-1 to 1-n perform a comparison process on the sorted data recorded in the second internal storage unit 8.

Note that only a part of the sort data to be compared is recorded in the second internal storage unit 8, and the sort data in the range recorded in the second internal storage unit 8 is subjected to comparison processing. Was performed, but no difference appeared in the result of the comparison processing, the comparison processing units 1-1 to 1-n
Performs a comparison process on the sort data recorded in the storage unit 2.

As described above, the sort processing device 5 according to the second embodiment has a larger storage capacity than the internal storage units 4-1 to 4-n, and performs processing such as writing and reading faster than the storage unit 2. Since the second internal storage unit 8 is provided, the sort processing can be performed at high speed even if the data volume of the sort data input to the sort processing device 5 is large.

Embodiment 3 of the Invention FIG. 6 shows another embodiment of the sorting apparatus according to the present invention. 9-1 to 9-m
Denotes an internal memory interface unit. Each of the internal memory interface units 9-1 to 9-m includes a comparison processing unit 1-1 to
1-n and the memory access interface unit 6.

8-1 to 8-m are second internal storage units. The internal memory interface unit 9-1 has a second internal storage unit 8-1, and the internal memory interface unit 9-2
Has the second internal storage unit 8-2, the second internal storage units 8-1 to 8-m are provided in the internal memory interface units 9-1 to 9-m. In FIG. 6,
The same or corresponding portions as those in the conventional example shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted, and portions different from FIG. 1 are described.

Next, a third embodiment of the present invention shown in FIG.
Will be described. When the comparison processing units 1-1 to 1-n perform comparison processing, the comparison processing units 1-1 to 1-n store the sorted data from the storage unit 2 in the internal storage units 4-1 to 4-n and the second internal storage unit. The data is read out to the storage units 8-1 to 8-m. And
The comparison processing units 1-1 to 1-n include internal storage units 4-1 to 4-n
The sort processing is performed on the sort data recorded in n.

Note that only a part of the sort data to be sorted is recorded in the internal storage units 4-1 to 4-n, and the sorted data is recorded in the internal storage units 4-1 to 4-n. Comparison processing was performed on the sorted data of
If no difference appears in the result of the comparison processing, the comparison processing units 1-1 to 1-n perform operations in the second internal storage units 8-1 to 8-n.
The comparison processing is performed on the sort data recorded in m.

Further, only a part of the sort data to be sorted is recorded in the second internal storage unit 8, and the sort data in the range recorded in the second internal storage unit 8 is If the comparison processing is performed but no difference appears in the result of the comparison processing, the comparison processing unit 1-1
1 to n perform a comparison process on the sort data recorded in the storage unit 2.

Since the sort processing device 5 of the third embodiment has a plurality of second internal storage units 8-1 to 8-m, each of the comparison processing units 1-1 to 1-n has a second internal storage unit. 8-1 to 8
The concentration of accesses to -m can be reduced. Since some of the comparison processing units 1-1 to 1-n are connected to the second internal storage units 8-1 to 8-m, each of the comparison processing units 1-1 to 1-n It is necessary to control the memory access signal output from the CPU.

The portions that control the memory access signals for the respective second internal storage units 8-1 to 8-m are the internal memory interface units 9-1 to 9-m. Note that a plurality of comparison processing units 1-1 to 1-n may be connected to each of the internal memory interfaces 9-1 to 9-m, so that m is an integer smaller than n.

The storage capacity of the second internal storage units 8-1 to 8-m is adjusted according to the data length of the descending n-piece data output from each of the comparison processing units 1-1 to 1-n. In this case, the second internal storage units 8-1 to 8-m can be used more efficiently.

As described above, the sort processing device 5 of the third embodiment
Has a plurality of second internal storage units 8-1 to 8-m, so that processing operations based on access signals output from each of the comparison processing units 1-1 to 1-n can be performed in a distributed manner. As a result, the processing capacity of the sorting device 5 is improved.

Embodiment 4 of the Invention FIG. 7 shows another embodiment of the sorting apparatus according to the present invention. In FIG.
The storage unit 2 has two access buses, which are signal lines that connect the storage unit 2 and other parts.

The first access bus 20 is a signal line connecting the storage unit 2 and the memory access interface unit 6. The second access bus 10 is a signal line that connects the storage unit 2 to another device. In FIG. 7, FIG.
The same or corresponding parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted, and the parts different from FIG. 1 are described.

In the storage unit 2 included in the sort processing device 5 of the fourth embodiment, the sort processing device 5 does not perform the sort processing, and does not perform the processing such as the writing and reading of the sort data on the storage unit 2. In this case, data output from another device connected via the second access path 10 is recorded in the storage unit 2.

The operation of the fourth embodiment shown in FIG. 7 is the same as the operation of the first embodiment shown in FIG.
The part different from the operation of the first embodiment has been described. The storage unit 2 according to the fourth embodiment operates as the storage unit 2 of the sort processing device 5, while the second access bus 1 operates when the storage unit 2 of the sort processing device 5 does not operate.
The processing operation is performed as a storage unit of another device connected via the “0”.

As described above, the storage unit 2 included in the fourth embodiment
Is a large-scale device having a plurality of devices including the sort processing device 5, which is efficiently used because one of the two devices is used by the other device when it is not used. Can be reduced in size.

The sort processing device 5 according to the fourth embodiment controls the storage unit 2 to control the recording position by the address so that the plurality of storage units 7 respectively corresponding to the plurality of comparison processing units 1-1 to 1-n. -1 to 7-n. In addition, the sort processing device 5 according to the fourth embodiment does not control the recording position by the address for the storage unit 2,
It can be used as a storage unit having one large storage capacity.

[0123]

As described above, the sort processing device according to the present invention receives a predetermined number of sort data items to be sorted, and outputs a first access signal and a predetermined number of sort data items among the input predetermined number of sort data items. A first comparison unit that outputs a first predetermined number of sort data in a predetermined order, and is connected to the first comparison unit and receives a predetermined order of sort data output from the first comparison unit, A second access signal, a second comparison unit that outputs a second predetermined number of sort data larger than the first predetermined number in the input sort data in a predetermined order, and a first and a second comparison unit. An interface commonly connected to the comparing unit, receiving first and second access signals output from the first and second comparing units, and outputting a processing signal based on the input first and second access signals Section and the interface section. And a storage unit for performing a recording or readout operation based on the processing signal output from the interface unit, and each of the plurality of comparison units is commonly connected to the interface unit so that Since the one signal line is connected to the storage unit, it is easy to integrate a plurality of comparison units into one integrated circuit, and the size of the sort processing device can be reduced.

Further, the second comparing section of the sort processing device according to the present invention, in the input sort data, sorts the second predetermined number of sort data twice as large as the first predetermined number in a predetermined order. The plurality of comparators are connected to the interface unit so as to be integrated into one signal line, and the plurality of comparators are connected to the storage unit. Can be easily integrated into one integrated circuit, and the size of the sort processing device can be reduced.

Further, based on the first access signal output from the first comparing section, the interface section of the sorting apparatus according to the present invention records the sort data input to the first comparing section in the storage section, Alternatively, the sort data recorded in the storage unit is read out to the first comparison unit, and based on the second access signal output from the second comparison unit, the sort data input to the second comparison unit is stored in the recording unit. Or read the sort data recorded in the storage unit to the second comparison unit, and record and read the sort data based on the first and second access signals output from the first and second comparison units. Since the processing is controlled collectively via one signal line, it is easy to combine a plurality of comparison units into one integrated circuit, and the size of the sort processing device can be reduced.

Further, the sorting apparatus according to the present invention
Since the sort data input to the first and second comparison units are recorded at different addresses of one storage unit in correspondence with the first comparison unit or the second comparison unit, the storage unit has an unnecessary storage. Provision of a capacity can be suppressed.

Further, the interface unit of the sorting apparatus according to the present invention is input to the first and second comparison units based on the first and second access signals output from the first and second comparison units. Sorted data is recorded, and has a second storage unit that is faster in recording and reading processing than the storage unit, and the second storage unit is the first comparison unit or the second comparison unit recorded in the storage unit. The sort data used for the comparison processing by the comparison unit is recorded. The first comparison unit and the second comparison unit perform a comparison process on the sorted data recorded in the second storage unit, which has a higher recording and reading processing speed than the storage unit. Recording and reading processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sort processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a situation in which an area of a storage unit of the sort processing apparatus according to the first embodiment is divided.

FIG. 3 is a diagram showing a processing method of a sort process in the sort processing device of the present invention.

FIG. 4 is a diagram illustrating a processing method of a sort process in a comparison processing unit 1-3 included in the sort processing device of the present invention.

FIG. 5 is a block diagram illustrating a sort processing device according to a second embodiment.

FIG. 6 is a block diagram illustrating a sort processing device according to a third embodiment.

FIG. 7 is a block diagram illustrating a sort processing device according to a fourth embodiment.

FIG. 8 is a block diagram of a conventional sort processing device.

FIG. 9 is a diagram illustrating a processing method of a sort process in a conventional sort processing device.

[Explanation of symbols]

1-1 to 1-n Comparison processing unit 2 Storage unit in the present invention 2-1 to 2-n Storage unit in conventional example 3-1 to 3-n Sort processing basic unit 4-1 to 4-n Internal storage unit 5 Sort processing device 6 Memory interface unit 8 Second internal storage unit 8-1 to 8-m The second provided for each of several comparison processing units
Internal storage units 9-1 to 9-m Internal memory interface units provided for several comparison processing units 10 Second access path of storage unit 2

Claims (5)

(57) [Claims] A first access signal and a first predetermined number of sort data among the input predetermined number of sort data are input in a predetermined order. The first comparison unit that is output in the, connected to the first comparison unit, the sort data of a predetermined order output from the first comparison unit is input, a second access signal, and the input A second comparison unit that outputs a second predetermined number of sorted data larger than the first predetermined number in the sorted data in a predetermined order, and is commonly connected to the first and second comparison units; The first and second access signals output from the first and second comparison units are input,
An interface unit for outputting a processing signal based on the input first and second access signals, and a storage unit connected to the interface unit for performing a recording or reading operation based on the processing signal output from the interface unit And a sort processing device. 2. The apparatus according to claim 1, wherein the second comparing section outputs a second predetermined number of sort data twice as large as the first predetermined number in the input sort data in a predetermined order. The sort processing device according to claim 1. 3. An interface unit records the sort data input to the first comparison unit in the storage unit or records the sort data in the storage unit based on the first access signal output from the first comparison unit. The read sort data is read out to the first comparison unit, and the sort data input to the second comparison unit is recorded in the recording unit based on the second access signal output from the second comparison unit. 3. The sort processing device according to claim 1, wherein the sort data recorded in the storage unit is read out to the second comparison unit. 4. The method according to claim 1, wherein the sorting data input to the first and second comparing sections are recorded at different addresses in the storage section in correspondence with the first comparing section or the second comparing section. The sort processing device according to claim 1, wherein 5. The interface unit according to claim 1, wherein the sort data input to the first and second comparison units is recorded based on the first and second access signals output from the first and second comparison units. And a second storage unit having a higher recording and reading speed than the storage unit.
5. The sort processing device according to any one of items 1 to 4.