JP3459495B2 - Microprocessor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor equipped with a wait control circuit necessary for inputting / outputting data from / to its memory.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration example of a conventional general microprocessor operating with a multi-phase clock (here, two-phase clock). In FIG. 6, reference numeral 1 indicates a program memory, which stores a plurality of instructions constituting a program for operating this microprocessor. The program memory 1 is connected to a program counter 2 via a program address bus PAB and an instruction register 3 via a program bus PB.

The program counter (PC) 2 indicates the address (PC value) in the program memory 1 of the next instruction to be executed by this microprocessor. If the instruction of the microprocessor is, for example, a word unit, and the address in the program memory 1 is a word address, then normally the program counter 2 sets the PC value to "
Increment by 1 ", and when a jump, branch, subroutine call, etc. occur, designated addresses are set in the program counter 2.

The instruction register 3 temporarily holds the instruction code (instruction code) output from the program memory 1 and outputs it to the instruction decoder 4. The instruction decoder 4 decodes the instruction code output from the instruction register 3 to specify an operation code to be actually executed, the data itself used for the operation, or the data in the data memory 7 of the data. A data address or the like designating an address (data memory address) is generated and output to the wait control unit 5.

The weight control section 5 mainly comprises a control circuit 51.
And a weight circuit 52. The control circuit 51 is
When it is necessary to input / output data to / from a data memory 7 described later when executing the instruction based on the content of the operation code given from the instruction decoder 4, the microprocessor is temporarily stopped until the processing is completed. Control to stop state (wait state). The details will be described later. The control circuit 51 outputs the n-bit address ADD to the data address register 6 and the memory read signal MR to the data memory 7, and at the same time, outputs the most significant m-bits of the n-bit address ADD and the register write. Signal RW is output to wait circuit 52. The wait circuit 52 outputs a control signal CS to the data register 8, which will be described in detail later.

The data address ADD output from the wait controller 5 to the data address register 6 is given to the data memory 7 via the data address bus DAB.
It is also given to the weight controller 5.

When the wait controller 5 supplies the memory read signal MR to the data memory 7, the data address ADD output from the data address register 6 is output.
Is the address of the data memory 7, that is, the data memory address, the corresponding data is read from the data memory 7 and output to the data bus DB.

When the control signal CS is applied from the wait controller 5 to the data register 8, the data output from the data memory 7 to the data bus DB is written (written) in the data register 8.

The data memory 7 stores various data required when the microprocessor executes an instruction, and also stores data obtained as a result of executing the instruction. By the way, generally, when the address of the microprocessor is n bits, the address allocation is determined by some bits on the most significant side of the address. Therefore, in this microprocessor, it is assumed that the address is assigned to the data memory 7 when the most significant m bits of the n-bit address are all "1". In other words, when the n-bit address is the data memory address, the most significant m bits are all "1".

Reference numeral 9 indicates an arithmetic unit,
While inputting / outputting data to / from the data register 8, the operation specified by the operation code of the instruction code is executed. The data required at that time is input from the data address register 6, and the data of the operation result is output to the data address register 6 and temporarily held.

FIG. 7 shows an example of the configuration of the weight circuit 52 and the one-bit configuration of the data register 8 which are provided in the weight control section 5 of the conventional microprocessor and function when weight control is performed. It is a logic circuit diagram shown. In FIG. 7, reference numeral 521 is a 3-input AND gate, 522 is an m-input NAND gate, and reference numerals 81 and 82 are both latches. It should be noted that the latches 81 and 82 form a portion corresponding to 1 bit of the data register 8.

The three inputs to the AND gate 521 are CK1 which is one of the two-phase non-overlap clocks, which is the basic clock of this microprocessor, and the register write signal RW generated in the control circuit 51. And the output signal (wait signal WT) of the NAND gate 522. NAND gate 522
The m input to is the most significant m bits of the n-bit address ADD.

The AND gate 52 is connected to the clock terminal of the latch 81.
The 1 output signal, that is, the control signal CS, is also input to the D-input terminal of 1 bit of the data D (IN) output from the data memory 7 to the data bus DB. CK0, which is the other of the two-phase basic clocks of the microprocessor, is input to the clock terminal of the latch 82, and the output signal from the Q-output terminal of the latch 81 is input to the D-input terminal. Then, the output signal from the Q-output terminal of the latch 82 is output to the arithmetic unit 9 as one bit of the output signal D (OUT) of the data register 8.

FIG. 8 is a timing chart showing the operation of one configuration example of the wait circuit 52 of the conventional microprocessor as shown in FIG. 7, particularly the operation at the time of wait control by the wait controller 5. Will be described with reference to. The two-phase basic clocks CK0 and CK1 of this microprocessor are non-overlap clocks in which the high level sections of both do not overlap. Also, FIG.
In the timing chart of, the reference symbols P01, P02, P03 are assigned in order from the first high-level pulse of the clock CK0.
, Are added as reference symbols in order from the first high-level pulse of the clock CK1, P11, P12, P13, ...

The wait signal WT and the memory read signal MR are both low active in this example, and the register write signal RW is high active in this example. The memory read signal MR has a phase opposite to that of the clock CK1 and becomes significant (low level) in synchronization with one cycle of the clock CK1 in the wait control period. In addition, the register write signal RW has the same phase as the clock CK1, and the clock for the wait control period
It becomes significant (high level) in synchronization with one cycle of CK1. In this example, the memory read signal MR and the register write signal RW are generated in the same cycle of the clock CK1.

Further, the wait signal WT is an output signal of the NAND gate 522, but when the wait controller 5 performs the wait control, it is one of the cycles from the cycle of the clock CK0 at the start of the wait control to the end of the wait control. Until the immediately preceding cycle, NAND gate 522 is provided with the most significant m bits of address ADD. However, the wait control unit 5 delays from the rising edge of the clock CK0 for a slight time while the wait control unit 5 determines the wait control period based on the instruction decoding result. In this example, the wait control period is clock CK
Since it is 2 cycles of 0, the most significant side m of the data address ADD is stored in the NAND gate 522 only in one cycle of the first CK0.
Bits are given. Therefore, when the wait control is started, the wait signal WT becomes significant (low level) with a slight delay from the rising edge of the clock CK0 and becomes insignificant (high level) in synchronization with the next rising edge of the clock CK0.
become.

First, the first pulse P01 of the clock CK0
The program address (N) is set as the PC value in the program counter 2 in synchronization with the rising edge of the, and is given to the program memory 1 via the program address bus PAB. As a result, the instruction code of the instruction (N) corresponding to the address (N) is output from the program memory 1 to the program bus PB. The instruction code of the instruction (N) output to the program bus PB is fetched and held in the instruction register 3 in synchronization with the rising edge of the second pulse P02 of the clock CK0, and further fetched by the instruction decoder 4. Is decoded. In the following description, as a result of the instruction (N) being decoded by the instruction decoder 4, the data memory 7
Suppose that it is necessary to read the data of the data memory address (N) from.

As a result of decoding the instruction code of the instruction (N) by the instruction decoder 4, the data memory address (N) is the third pulse P03 of the clock CK0 as the data address ADD.
Is output from the instruction decoder 4 in synchronization with the rising edge of
It is given to the weight controller 5 and further given to the data address register 6 and held therein. Data memory address (N) held in this data address register 6
Is given to the data memory 7 via the data address bus DAB and is also given to the wait controller 5 again.

When an instruction for reading data from the data memory 7 is executed, the clock CK0 is used for inputting / outputting (reading / writing) data to / from the data memory 7.
2 cycles or more times are required, and the wait control unit 5 performs control for that.
That is, weight control is performed. In other words, clock CK0
Even if the instruction decoder 4 outputs the data memory address (N) from the rising edge of the third pulse P03, the data memory 7 can actually output the data corresponding to the data memory address (N) to the data bus DB. It takes some delay time to reach. Therefore, the wait control unit 5 determines the number of wait control cycles according to the instruction to be executed, that is, according to the decoding result by the instruction decoder 4, and gives the memory read signal MR at an appropriate timing to store the data in the data memory. It is controlled to output from 7 to the data bus DB. In the following description, the number of cycles required for weight control is two.

The control circuit 51 of the wait controller 5 uses the data memory address (N) as the address ADD in the clock CK0.
4th pulse from the rising edge of P03
Output for 2 cycles until P04 rises. This data memory address (N) is held in the data address register 6 and given to the data memory 7 via the data address bus DAB. Further, the control circuit 51
Is a significant (low level) level for the memory read signal MR in synchronization with the period of the fourth pulse P14 of the clock CK1.
Then, the register write signal RW is made significant (high level).

When the control circuit 51 of the weight controller 5 performs the above control, the wait circuit 52 shown in FIG. 7 operates as follows. Weight circuit 52
The n-bit data address ADD, in this case the uppermost m bits of the data memory address, is input to the NAND gate 522, but as described above, these are all "1".
Therefore, the output signal of the NAND gate 522 becomes "0". In other words, the weight signal WT is low level (significant)
become.

The wait signal WT is given to the AND gate 521. The other two inputs of the AND gate 521 are the clock CK1 and the register write signal RW, but the significant (low level) wait signal WT is output from the NAND gate 522, regardless of the other two inputs. In addition, the control signal CS, which is the output signal of the AND gate 521, becomes low level. After that, the third pulse P13 of the clock CK1 rises, but falls to the low level immediately before the wait signal WT goes to the high level. Immediately after that, clock CK0
The wait signal WT changes to insignificant (high level) in synchronization with the rising edge of the fourth pulse P04 of.

After this, the fourth pulse P1 of the clock CK1
Since the memory read signal MR becomes significant (low level) and the register write signal RW becomes significant (high level) in synchronization from the rising edge to the falling edge of 4, the data memory held in the data address register 6 Data (data) is output from the data memory 7 to the data bus DB corresponding to the address (N). At the same time, as described above, the wait signal WT is already insignificant (high level) and the register write signal RW is also significant (high level) at this point. Therefore, at this point, the AND gate
The control signal CS, which is the output signal of the 521, turns to high level,
Since this is given to the clock terminal of the latch 81, one bit of data (data) is fetched and latched from the data bus DB to the D-input terminal of the latch 81 and the latch 81
It is output from the Q-output terminal of.

Then, the fifth pulse P0 of the clock CK0
This pulse P05 is applied to the clock terminal at the rising edge of 5, and the latch 82 outputs the data (data) which is the output signal from the Q-output terminal of the latch 81 to its D-input terminal.
Take in 1 bit of and latch. The signal latched by the latch 82 is output from the Q-output terminal of the latch 82 as one bit of the output signal D (OUT) of the data register 8.

[0025]

As described above, the conventional wait circuit of the microprocessor has the first high level of the clock CK1 within the period of two cycles of the clock CK0 controlled by the wait controller. It was necessary to keep the weight signal WT significant by the time of rising. Therefore, the wait control unit has no time margin, and it is impossible to perform more complicated control. Further, the margin with respect to the clock frequency is small, and more accurate operation cannot be guaranteed.

The present invention has been made in view of the above circumstances, and employs a simpler circuit configuration so that there is a time margin in the weight control unit and if the same processing as the conventional one is sufficient. On the other hand, an object of the present invention is to provide a microprocessor capable of performing complicated control without downsizing the circuit scale and further increasing the margin with respect to the clock frequency.

[0027]

A microprocessor according to the present invention operates with an n-phase (n is a natural number of 2 or more) non-overlap clock and temporarily holds data read from a memory. When accessing the memory, set a wait period of 2 clock cycles or more,
A wait control unit for controlling the data output from the memory to be stored in the register in the last cycle of the wait period, and the register further includes a latch unit at a previous stage for latching the data output from the memory, and a latch unit at the previous stage. And a latch unit at a subsequent stage for latching the data latched by the wait controller. A second means for performing the latch operation of the latch means in synchronization with the first phase of the n-phase clock
And the operation of the second timing means,
It is characterized in that it has a prohibition means for prohibiting in each cycle other than the last cycle of the wait period.

[0028]

In the microprocessor according to the present invention, in the wait control section, the first timing means causes the latch operation of the preceding latch means to be performed in synchronization with the n-th phase of the n-phase clock, and the second timing means. The latching operation of the latter latching means is performed in synchronization with the first phase of the n-phase clock, and the inhibiting means further inhibits the operation of the second timing means in each cycle other than the last cycle of the wait period.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 2 is a block diagram showing an example of the overall configuration of a microprocessor according to the present invention which operates with a multi-phase clock. In this embodiment, it operates with a two-phase clock.

In FIG. 2, reference numeral 1 designates a program memory, which stores a plurality of instructions constituting a program for operating this microprocessor.
The program memory 1 is connected to a program counter 2 via a program address bus PAB and to an instruction register 3 via a program bus PB.

The program counter (PC) 2 indicates the address (PC value) in the program memory 1 of the instruction to be executed next by this microprocessor. If the instruction of the microprocessor is, for example, a word unit, and the address in the program memory 1 is a word address, then normally the program counter 2 sets the PC value to "
Increment by 1 ", and when a jump, branch, subroutine call, etc. occur, designated addresses are set in the program counter 2.

The instruction register 3 temporarily holds the instruction code (instruction code) output from the program memory 1 and outputs it to the instruction decoder 4. The instruction decoder 4 decodes the instruction code output from the instruction register 3 to specify an operation code to be actually executed, the data itself used for the operation, or the data in the data memory 7 of the data. A data address or the like designating an address (data memory address) is generated and output to the wait control unit 50.

The weight controller 50 is mainly composed of the control circuit 50.
It is composed of 1 and a weight circuit 502. Control circuit 50
1 is used for executing the instruction based on the content of the operation code given from the instruction decoder 4, when data needs to be input / output to / from a data memory 7 which will be described later, until the processing is completed. Controls the processor to the suspend state (wait state). The details will be described later. The control circuit 501 outputs the n-bit data address ADD to the data address register 6 and the memory read signal MR to the data memory 7, and also outputs the n-bit data address AD.
The most significant bit of D and register write signal RW
Is output to the wait circuit 502. The wait circuit 502 outputs control signals CS1 and CS2 to the data register 8, which will be described in detail later.

The data address ADD output from the wait controller 50 to the data address register 6 is given to the data memory 7 via the data address bus DAB.
It is also given to the weight controller 50.

When the memory control signal MR is given from the wait controller 50 to the data memory 7, the data address ADD output from the data address register 6 is output.
Is the address of the data memory 7, that is, the data memory address, the corresponding data is read from the data memory 7 and output to the data bus DB.

When the control signals CS1 and CS2 are applied from the wait controller 50 to the data register 8, the data output from the data memory 7 to the data bus DB is written (written) in the data register 8.

The data memory 7 stores various data required when the microprocessor executes an instruction, and also stores data obtained as a result of executing the instruction. By the way, generally, when the address of the microprocessor is n bits, the address allocation is determined by some bits on the most significant side of the address. Therefore, in this microprocessor, it is assumed that the address is assigned to the data memory 7 when the most significant m bits of the n-bit address are all "1". In other words, when the n-bit address is the data memory address, the most significant m bits are all "1".

Reference numeral 9 indicates an arithmetic unit,
While inputting / outputting data to / from the data register 8, the operation specified by the operation code of the instruction code is executed. The data required at that time is input from the data address register 6, and the data of the operation result is output to the data address register 6 and temporarily held.

FIG. 1 shows an example of the configuration of a wait circuit 502 which is provided in the weight control unit 50 of the microprocessor of the present invention and which functions when weight control is performed, and an example of the configuration of one bit of the data register 8. It is a logic circuit diagram showing.

In FIG. 1, reference numeral 5021 designates a 2-input AND gate which functions as a first timing means 5022.
5023 is an m-input NAND gate that functions as a prohibition means.
Indicates a 2-input AND gate functioning as a second timing means, and reference numerals 81 and 82 both indicate a latch. It should be noted that the latch 8 functioning as the latch means in the previous stage
1, 82 corresponding to one bit of the data register 8 is constituted by 82 which functions as a latch unit in the subsequent stage.

Two inputs to the AND gate 5021 are the CK1 which is one of the two-phase non-overlap clocks which is the basic clock of this microprocessor and the register write signal RW which is generated in the control circuit 501. is there. Note that A
The output signal of the ND gate 5021 is output to the data register 8 as the control signal CS1. The m input to the NAND gate 5022 is the most significant m bits of the n-bit data address ADD, and its output signal is the wait signal WT as described later. The two inputs to the AND gate 5023 are the weight signal WT which is the output signal of the NAND gate 5022 described above,
CK0, which is the other of the two-phase basic clocks of the microprocessor. The output signal of the AND gate 5023 is output to the data register 8 as the control signal CS2.

The AND gate 50 is connected to the clock terminal of the latch 81.
The control signal CS1, which is the output signal of 21, is also input to the D-input terminal of 1 bit of the data D (IN) from the data bus DB. The control signal CS2, which is the output signal of the AND gate 5023, is input to the clock terminal of the latch 82, and the output signal from the Q-output terminal of the latch 81 is input to the D-input terminal. Then, the output signal from the Q-output terminal of the latch 82 is output to the arithmetic unit 9 as the output signal D (OUT) of the data register 8.

The operation of the configuration example of the wait circuit 502 of the microprocessor of the present invention as shown in FIG.
In particular, the operation during weight control by the weight controller 50 will be described with reference to the timing chart shown in FIG. The two-phase basic clocks CK0 and CK1 of this microprocessor are non-overlap clocks in which the high level sections of both do not overlap. Further, in the timing chart of FIG. 3, the reference symbols P01, P02,
.. are denoted by P11, P12, P13, ... As reference symbols in order from the first high-level pulse of the clock CK1.

The wait signal WT and the memory read signal MR are both low active in this example, and the register write signal RW is high active in this example. The memory read signal MR has a phase opposite to that of the clock CK1 and becomes significant (low level) in synchronization with each cycle of the clock CK1 in the wait control period. In addition, the register write signal RW has the same phase as the clock CK1, and the clock for the wait control period
It becomes significant (high level) in synchronization with each cycle of CK1. In this example, the memory read signal MR and the register write signal RW are generated in the same cycle of the clock CK1.

Further, the wait signal WT is an output signal of the NAND gate 5022, but when the wait controller 50 performs the wait control, the cycle in which the wait control ends from the cycle next to the clock CK0 at the start of the wait control. Until the clock CK0 of the last cycle falls until the clock CK0 of the last cycle falls until the clock CK0 of each cycle rises.
The most significant m bits of ADD are provided. In this example, since the wait control period is two cycles of the clock CK0, the NAND gate 5022 is provided with the address ADD in the period from the time before the rising of one cycle of the last CK0 to the falling of the clock CK0 of the last cycle. The most significant m bits are provided. Therefore, the weight signal WT is
When the wait control is started, it becomes significant (low level) in the period from the time before the second and subsequent rises of the clock CK0 to the fall of the clock CK0 in the last cycle.

First, the first pulse P01 of the clock CK0
The program address (N) is set in the program counter 2 in synchronism with the rising edge of and is given to the program memory 1 via the program address bus PAB. As a result, the program bus PB from the program memory 1
The instruction (N) corresponding to the address (N) is output to. The instruction (N) output to this program bus PB is the clock
It is taken into the instruction register 3 in synchronization with the rising edge of the second pulse P02 of CK0, and further taken into the instruction decoder 4 and decoded. In the following description, it is assumed that, as a result of the instruction decoder 4 decoding the instruction (N), it is necessary to read the data of the data memory address (N) from the data memory 7.

As a result of decoding the instruction code of the instruction (N) by the instruction decoder 4, the data memory address (N) is the third pulse P03 of the clock CK0 as the data address ADD.
Is output from the instruction decoder 4 in synchronization with the rising edge of
It is given to the weight control unit 50 and further given to the data address register 6 and held therein. Data memory address (N) held in this data address register 6
Is given to the data memory 7 via the data address bus DAB and is also given to the wait controller 50.

When an instruction to read data from the data memory 7 is executed, the clock CK0 is used for inputting / outputting (reading / writing) data to / from the data memory 7.
2 cycles or more cycles are required, so the wait controller 50 controls for that.
That is, weight control is performed. In other words, clock CK0
Even if the instruction decoder 4 outputs the data memory address (N) from the rising edge of the third pulse P03, the data memory 7 can actually output the data corresponding to the data memory address (N) to the data bus DB. It takes some delay time to reach. Therefore, the wait control unit 50 determines the number of cycles of wait control according to the instruction to be executed, that is, according to the decoding result by the instruction decoder 4, and gives the memory read signal MR at an appropriate timing to store data in the data memory. It is controlled to output from 7 to the data bus DB. In the following description, the number of cycles required for weight control is two.

The control circuit 501 of the wait control unit 50 uses the data memory address (N) as the data address ADD for two cycles from the rising of the third pulse P03 of the clock CK0 to the falling of the fourth pulse P04. Output over a period. This data memory address (N) is held in the data address register 6 and the data address bus DA
It is given to the data memory 7 via B.

After that, the third pulse P1 of the clock CK1
The control circuit 501 sets the memory read signal MR to the significant level (low level) in synchronization with the period from the rising edge to the falling edge of 3 and the period from the rising edge to the falling edge of the fourth pulse P14 of the clock CK1. Then, the register write signal RW is made significant (high level). At this time, the control circuit 501 shifts the memory read signal MR and the register write signal RW from the significant to the abrupt in the first time, that is, from the time before the fourth pulse P04 of the clock CK0 rises. Fourth pulse of clock CK0
Data address AD during the period until P04 falls
D, but in this case, the most significant m bits are all "1"
The wait signal WT is significant (low level) by supplying the NAND gate 5022 with the data memory address (N)
To

By the control circuit 501 performing the above control, the wait circuit 502 shown in FIG. 1 operates as follows. Wait circuit 502 AND gate 50
2 inputs to 21 are clock CK1 and register write signal RW
Therefore, when the third pulse P13 of the clock CK1 rises, its output signal becomes "1". Therefore,
At this point, the latch 81 takes in and latches the input signal to the D-input terminal and starts outputting from the Q-output terminal.

By the way, there is no guarantee that the signal (X) latched by the latch 81 in this state is the signal of data (data) corresponding to the data memory address (N) requested at that time. Therefore, it is necessary to prevent the signal latched by the latch 81 from being latched by the latch 82 and output as the output signal D (OUT) of the data register 8. Therefore, in the period from the time point before the rising edge of the fourth pulse P04 of the clock CK0 immediately after this to the falling time point of the fourth pulse P04 of the clock CK0, the control circuit 501 sets the n-bit data. The most significant m bits of the address ADD are output to the NAND gate 5022. As described above, the most significant m bits of this data memory address are all "1". This allows NA
The output signal of the ND gate 5022 becomes "0", in other words, the wait signal WT becomes low level (significant).
The output signal of 5023 maintains "0" regardless of the clock CK0 which is the other input signal. Therefore, this clock CK
Before and after the fourth pulse P04 of 0 rises, the latch 82 does not capture the output signal from the Q-output terminal of the latch 81.

When the fourth pulse P14 of the next clock CK1 rises, the output signal of the AND gate 5021 becomes "1" again. Therefore, at this point, the latch 81 takes in and latches the input signal to the D-input terminal and starts to output it from its own Q-output terminal. By the way, at this time, since the data (data) corresponding to the data address (N) requested from the data memory 7 has already been output to the data bus DB, the signal latched by the latch 81 is data) is a 1-bit signal.

Then, the fifth pulse P0 of the clock CK0
At the rising edge of 5, the latch 82 outputs to its D-input terminal the data that is the output signal from the Q-output terminal of the latch 81.
Take in 1 bit of (data) and latch it. This latch
The signal latched by 82 is output as the output signal D (OUT) of the data register 8 from the Q-output terminal of the latch 82.

Next, the case where the microprocessor of the present invention operates with a four-phase clock will be described. FIG. 4 shows an example of the configuration of the wait circuit 502 and the data register 8 which are provided in the wait control unit 50 when the microprocessor of the present invention operates with a four-phase clock and which functions when the wait control is performed. It is a logic circuit diagram which shows the structural example for bit. In addition, in FIG. 4, in FIG.
The same reference numerals as those of the configuration example in the case of operating with the two-phase clock shown in FIG.

The structure of the wait circuit for the four-phase clock shown in FIG. 4 and the two shown in FIG.
The difference from the configuration of the wait circuit in the case of the phase clock is that one input to the AND gate 5021 operates in the two-phase clock shown in FIG.
The only difference is that the clock CK3 is used in the example of operating with the four-phase clock shown in FIG.

The operation of the configuration example of the wait circuit 502 of the microprocessor of the present invention which operates with a four-phase clock as shown in FIG. 4, particularly the operation at the time of wait control by the weight controller 50, is shown in FIG. It is shown in the timing chart. In addition, 4 of this microprocessor
The basic clocks CK0, CK1, CK2, and CK3 of the phases are non-overlap clocks in which the high-level sections do not overlap. Further, in the timing chart of FIG. 5, P01, P02, P03, ... As reference symbols in order from the first high-level pulse of the clock CK0, and P11 as reference symbols in order from the first high-level pulse of the clock CK1. , P1
P21, P22, P23, ... as reference symbols in order from the first high-level pulse of the clock CK2, and P31, P32, as reference symbols in order from the first high-level pulse of the clock CK3. P33 ... are attached respectively.

The difference between the timing chart of the wait circuit for the four-phase clock shown in FIG. 5 and the timing chart of the wait circuit for the two-phase clock shown in FIG. The clock CK0 from the falling edge of the clock CK1 for one cycle of the memory read signal MR
Is significant (low level) during the rising edge of, the register write signal RW is in phase with the clock CK3,
Is. Other operations are the same as in the case of the two-phase clock described above.

[0059]

As described in detail above, according to the microprocessor of the present invention, conventionally, in the case of a two-phase clock, it was necessary to make the wait signal significant until the second phase rises. However, in the present invention, it may be significant until the next first phase rises. For this reason, since there is a time margin in the wait control unit, it is possible to adopt a simpler circuit configuration if the same processing as the conventional one is sufficient, and it is possible to reduce the circuit scale. It is also possible to perform complicated control without downsizing the circuit scale. Further, since the margin for the clock frequency becomes large, more accurate operation becomes possible.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram showing a configuration example of a wait circuit and a 1-bit configuration example of a data register provided in a wait control unit of a microprocessor of the present invention operating with a two-phase clock.

FIG. 2 is a block diagram showing a configuration example of a microprocessor of the present invention which operates with a two-phase clock.

FIG. 3 is a timing chart showing an operation during wait control of the microprocessor of the present invention which operates with a two-phase clock.

FIG. 4 is a logic circuit diagram showing a configuration example of a wait circuit and a 1-bit configuration example of a data register provided in a wait control unit of a microprocessor of the present invention which operates with a four-phase clock.

FIG. 5 is a timing chart showing an operation during wait control of the microprocessor of the present invention which operates with a four-phase clock.

FIG. 6 is a block diagram showing a configuration example of a conventional general microprocessor that operates with a multiphase clock.

FIG. 7 is a logic circuit diagram showing a configuration example of a wait circuit and a 1-bit configuration example of a data register provided in a weight control unit of a conventional general microprocessor that operates with a multiphase clock.

FIG. 8 is a timing chart showing an operation during wait control of a conventional general microprocessor that operates with a multi-phase clock.

[Explanation of symbols]

7 Data memory 8 data registers 50 weight controller 81 latch 82 latch 502 wait circuit 5021 AND gate 5022 NAND gate 5023 AND gate CK0, CK1, CK2, CK3 clock

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/00 G06F 9/30-9/36 G06F 12/00-12/06 G06F 13/16-13/18 G06F 15 / 78

Claims (2)

(57) [Claims] 1. A register which operates with an n-phase (n is a natural number of 2 or more) non-overlap clock and temporarily holds data read from a memory, and a wait of 2 clock cycles or more when accessing the memory. A microprocessor provided with a wait control unit for setting a period and controlling the data output from the memory to be loaded into the register in the last cycle of the wait period, wherein the register is the data output from the memory. A wait control unit for latching the data latched by the latch unit in the front stage, and the wait control unit controls the latch operation of the latch unit in the front stage for the n-phase clock a first timing means for synchronizing with the n-phase and a latch means for the latter stage. Second timing means for performing a latch operation in synchronization with the first phase of the n-phase clock; and prohibiting means for inhibiting the operation of the second timing means in each cycle other than the last cycle of the wait period. Microprocessor characterized by having. 2. The prohibiting means is adapted to prohibit the operation of the second timing means when an address signal for accessing the memory is output. Microprocessor.