JP4021590B2 - Floating point arithmetic unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a floating point arithmetic unit.
[0002]
[Prior art]
When a floating-point arithmetic unit conforming to IEEE754 is configured, it is specified to have exception factor information that is a floating-point operation result and flag information thereof.
FIG. 3 is a diagram showing a configuration of a conventional floating point arithmetic unit. The floating point arithmetic unit is composed of three arithmetic units, for example, an adder / subtracter 10, a multiplier 12, and a divider / square root 14, and each arithmetic unit operates independently. The exception factor information and the flag information output from each of the arithmetic units 10, 12, and 14 are stored in one state register 20 via the OR gates 16 and 18, respectively. In addition, an output obtained by ORing signals output from the M stages of the arithmetic units 10, 12, and 14 by the OR gate 22 is input to the status register 20 as an enable signal.
In this case, the flag information of the status register 20 may be updated out of order, but there is a restriction that the exception factor information must be the exception information of the last executed instruction. For this reason, if there is a possibility that one of the exception factor information is updated if it is updated in register units, there is a problem that the next instruction cannot be executed until the previous instruction is completed. In order to solve this, it was necessary to wait for a later execution instruction.
[0003]
FIGS. 4 and 5 show the above-described conventional operation. FIG. 4 shows an example of overlapping, and FIG. 5 shows a case of waiting. 4 and 5, D represents an instruction decode stage, E1 represents a first operation stage, E2 represents a second operation stage, M represents an exception detection stage, and W represents an operation result write back stage.
For example, in the example of FIG. 4, when a division instruction and an addition instruction are executed in parallel, if the last instruction is an addition instruction, both instructions are executed simultaneously by the divider 14 and the adder / subtractor 10. The processing speed of the above instruction is completed earlier in the adder / subtracter 10, and exception factor information output at the M stage is input to the state register 20 via the OR gate 16, and the state register 20 is also received by the enable signal of the M stage. The exception cause information for is updated.
Thereafter, the division instruction processing of the divider 14 is completed, and the exception information output at the M stage is stored in the status register 20 in the same procedure. In this case, the exception factor information of the division instruction is overwritten on the exception factor information of the addition instruction due to a difference in processing speed of the arithmetic unit. For this reason, there is a problem that exception factor information is not correctly stored despite the addition instruction being executed last.
[0004]
In order to solve this, in the example shown in FIG. 5, a wait (STALL) is inserted in the E1 stage of the addition instruction. Then, after the E2 stage of the division instruction is completed, the E1 stage of the addition instruction is executed, and exception information is stored in the status register 20 in the M stage as well. As a result, the exception factor information output by the division instruction shown in FIG. 4 is not overwritten, but there is a disadvantage that processing of the addition instruction is delayed.
[0005]
[Problems to be solved by the invention]
As described above, the conventional floating point arithmetic unit has a drawback that an unnecessary waiting time occurs when a plurality of pieces of information are mixed in the status register.
The present invention has been made to solve the above-described drawbacks. When a plurality of pieces of information are mixed in the status register, a plurality of instructions are overlapped and executed by giving each instruction the right to update information. An object of the present invention is to provide a floating point arithmetic unit that can be used.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the floating point arithmetic unit of the present invention has a plurality of different arithmetic units that execute instructions independently, and when the arithmetic unit instructions are issued for each of the arithmetic units, An exception information update right bit that is set and reset when an instruction of another arithmetic unit is issued, and exception information can be updated only by the arithmetic unit in which the exception information update right bit is set It is characterized by.
Further, the floating point arithmetic unit of the present invention includes a plurality of different arithmetic units, each of which includes a floating point arithmetic unit that executes an instruction independently, and each arithmetic unit of the floating point arithmetic unit. A storage means for an exception information update right bit that is set when an instruction of a calculator is issued and reset when an instruction of another calculator is issued, and exception information output from each calculator is stored in the storage means And an exception information register in which exception information selected by the exception information update right bit is stored.
With this configuration, when a plurality of pieces of information are mixed in the status register, a plurality of instructions can be overlapped and executed by giving each instruction the right to update information. As a result, in the floating point arithmetic unit, it is possible to prevent performance degradation by eliminating unnecessary waiting time.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the floating point arithmetic unit of the present invention. In the figure, the floating point arithmetic unit is composed of three arithmetic units, for example, an adder / subtractor 30, a multiplier 32, and a divider / square root 34, and each arithmetic unit operates independently.
Each of the arithmetic units 30, 32, and 34 is a memory that stores an exception factor update right bit that is set when an instruction of the arithmetic unit is issued and reset when an instruction of another arithmetic unit is issued. For example, flip-flops, registers, etc.) 31, 33, 35 are provided. The status register is divided into an exception factor information register 44 and a flag information register 38.
The flag information output from each of the arithmetic units 30, 32, 34 is stored in the flag information register 38 via the OR gate 36. In addition, an output signal obtained by ORing signals output from the M stages of the arithmetic units 30, 32, and 34 by the OR gate 40 is input to the flag information register 38 as an enable signal for storage. In this way, in the flag information register 38, for all executed instructions, exception flags (those that have been masked with an exception mask among exception factors generated as a result of processing of the operation instruction) obtained when each instruction is executed are stored. The ORed value is memorized.
[0008]
On the other hand, exception factor information output from each of the arithmetic units 30, 32, and 34 is stored in the exception factor information register 44 via the selector 42. The exception factor information register 44 receives, as an enable signal, an output obtained by ORing the signals output from the memories 31, 33, 35 storing the update right bits of the respective arithmetic units 30, 32, 34 by the OR gate 46. . The signals output from the memories 31, 33, and 35 storing the update right bits are also input as selection signals for the selector 42.
FIG. 2 is a timing chart showing the operation of the floating point arithmetic unit of the present invention. The operation of the floating point arithmetic unit according to the present invention will be described with reference to FIG.
As an example of the operation of the present invention, a case where an addition instruction is issued following a division instruction will be described as in the description of FIG. 4 or FIG.
In the present invention, when a division instruction is issued, the update right bit memory 35 of the divider 34 is set. Next, when the addition instruction is issued, the update right bit memory 35 of the previously set divider 34 is reset, and the update right bit memory 31 of the adder / subtractor 30 is set.
In this state, the divider 34 and the adder / subtracter 30 process the respective instructions in parallel, and the exception factor information output at the M stage of the adder / subtractor 30 is output to the selector 42. The selector 42 selects and outputs the exception factor information output from the adder / subtractor 30 by the signal output from the memory 31 of the update right bit of the adder / subtractor 30, and the signal output from the memory 31 is also input to the register 44. Exception information is set in the exception factor information register 44 as an enable signal.
[0009]
Thereafter, in the divider 34, the contents of the memory 35 of the update right bit of the divider 34 are already reset even when the division instruction is completed and the M stage is reached, so the contents of the exception factor information register 44 are updated. It will never be done.
[0010]
【The invention's effect】
According to the above-described invention, the conventional status register is divided into the flag information register and the exception factor information register, and the update right bit is stored in each of the various arithmetic units constituting the floating point arithmetic unit. Since the exception factor information of the last issued instruction can always be stored in the exception factor information register, unnecessary waiting time can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a floating point arithmetic unit according to the present invention.
FIG. 2 is a timing chart showing the operation of the floating point arithmetic unit of the present invention.
FIG. 3 is a block diagram showing the configuration of a conventional floating point arithmetic unit.
FIG. 4 is a timing chart showing the operation of a conventional floating point arithmetic unit.
FIG. 5 is a timing chart showing the operation of a conventional floating point arithmetic unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 30 ... Adder / Subtractor, 32 ... Multiplier, 34 ... Divider 31, 33, 35 ... Memory 36, 40, 46 of update right bit ... OR gate 42 ... Selector 38 ... Frac information register 46 ... Exception factor information register

Claims (2)

It has a plurality of different arithmetic units that execute instructions independently, and is set when an instruction of the arithmetic unit is issued for each of the arithmetic units, and is reset when an instruction is issued to other arithmetic units. A floating-point arithmetic unit characterized by having an exception factor update right bit that can be updated only by the arithmetic unit in which the exception factor update right bit is set. A floating point arithmetic unit having a plurality of different arithmetic units and executing instructions independently of each other;
Means for storing exception factor update right bits that are built in each arithmetic unit of the floating-point arithmetic unit, set when an instruction of the arithmetic unit is issued, and reset when an instruction of another arithmetic unit is issued; ,
An exception factor information register for storing exception factor information selected by the storage means in which the exception factor update right bit is set as exception factor information output from the arithmetic unit;
A floating point arithmetic unit comprising:

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