KR100863541B1 - Synchronization Control Device, Dual Port Memory Having Synchornization Control Device and Method for Controlling Synchonization in Dual Port Memory - Google Patents

Abstract

A dual port memory having a synchronous control device capable of ensuring synchronized work between each task in a multitask environment is disclosed. And a memory array having a plurality of shared memory regions, wherein the first memory interface performs a read or write operation on the plurality of shared memory regions based on an address and a control signal provided through the first port from the first processor. The second memory interface performs a read or write operation on the plurality of shared memory areas based on an address and a control signal provided from the second processor through the second port. The synchronous access controller includes a plurality of semaphore cells that control mutually exclusive access to a plurality of shared memory regions, and each of at least one task executed in any one processor of the first processor and the second processor attempts to access each other. The input / output of the access request signal and the access permission signal may be independently performed on the semaphore cell corresponding to the shared memory area. Therefore, even in a multi-task environment in which at least one task is executed in one processor, continuous synchronization between tasks may be guaranteed even when a context switch between tasks occurs.

Description

Synchronization Control Device, Dual Port Memory Having Synchornization Control Device and Method for Controlling Synchonization in Dual Port Memory}

1A is a block diagram showing the configuration of a hardware semaphore in a conventional dual port memory system.

FIG. 1B is a truth table showing the operation of the conventional hardware semaphore shown in FIG. 1A.

2 is a block diagram illustrating a configuration of a dual port memory system having a synchronous control device according to an embodiment of the present invention.

FIG. 3A is a block diagram illustrating a detailed configuration of the semaphore cell shown in FIG. 2.

FIG. 3B is a state table illustrating the operation of the semaphore cell shown in FIG. 3A.

4A is a circuit diagram showing a detailed configuration of the synchronization control device shown in FIG.

4B is a truth table showing the operation of the synchronization control device shown in FIG. 4A.

5 is a state table for explaining a synchronous control method of a dual port memory system according to an embodiment of the present invention.

6 is a flowchart illustrating a shared memory access procedure in a dual port memory system according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: first processor 120: second processor

150: first port 160: second port

200: dual port memory 210: memory cell array

211: first shared memory area 213: second shared memory area

215: third shared memory area 217: fourth shared memory area

240: synchronous control unit 250: hardware semaphore

260: first semaphore cell 270: second semaphore cell

280: third semaphore cell 290: fourth semaphore cell

The present invention relates to a dual port memory system, and more particularly, a dual port memory having a synchronous control device applicable to a portable terminal having a dual port memory, a dual port memory system having a synchronous control device, and a dual port memory. It relates to a synchronous control method of the system.

Recently, portable terminals such as mobile phones and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video phones, and multimedia data playback in addition to mobile communication functions such as voice calls.

The portable terminal is provided with a modem processor for processing the original functions of the mobile communication and an application processor for processing various applications.

In general, in a portable terminal having two processors, dual port memory is used to improve the processing performance of the system and to reduce the mounting area of the memory by performing data transmission and reception between the two processors at high speed.

In other words, when two processors use dual-port memory, each processor can access its memory area using its own port to read and write data, so that the two processors are connected to different memory to interface between host processors. Data transfer and processing is faster than processing data sent and received via Host Porcessor Interface (HPI), which improves the overall performance of the system.

The dual port memory includes a dedicated memory area in which two processors each independently perform a read or write operation, and a shared memory area in which the two processors jointly access a read or write operation.

In the dual port memory system, hardware semaphores are used to ensure mutual exclusive access of each processor to the shared memory area and to ensure synchronized operations between the processors.

Hardware semaphores are mutually exclusive to each processor using binary logic values (e.g., '0' or '1') depending on the current access state of the given shared memory area to determine if the given shared memory area is accessible. By providing each processor with mutual access to a given shared memory area.

That is, when a predetermined processor requests an access to a predetermined shared memory area at any time, the hardware semaphore sends a request to the predetermined processor when there is no processor currently accessing the requested shared memory area. If there is a processor allowing access and accessing the predetermined shared memory area, the access of the predetermined processor is blocked until the accessing processor terminates the access.

When a plurality of shared memory regions exist in a dual port memory system, semaphore cells having the same number of shared memory regions as the number of shared memory regions are provided in the hardware semaphores to ensure mutually exclusive access to each shared memory region.

FIG. 1A is a block diagram illustrating the configuration of a hardware semaphore in a conventional dual port memory system, and FIG. 1B is a truth table illustrating the operation of the conventional hardware semaphore shown in FIG. 1A, in which four shared memory regions exist in the dual port memory. The case is shown. In addition, FIG. 1A illustrates a connection relationship between a first processor and a hardware semaphore among two processors included in the dual port memory system.

1A and 1B, since a dual port memory system is assumed to have four shared memory regions, four semaphore cells 20 to 50 are provided in a hardware semaphore.

Each semaphore cell 20 to 50 controls mutually exclusive access of two processors to a shared memory region corresponding to and corresponding to each shared memory region among four shared memory regions provided in the dual port memory.

Each semaphore cell 20 to 50 receives an access request signal REQ1 to REQ4 for accessing each shared memory area from the first processor 10 and receives an access permission signal RDY1 according to a current access state of the shared memory area. To RDY4).

For example, each semaphore cell 20 to 50 receives a logical value '0' from the first processor 10 as an access request signal REQ1 to REQ4 for the shared memory area, and the shared memory area is provided to another processor. By the access permission signals RDY1 to RDY4 if the processor is approaching, and if there is no processor accessing the shared memory area, the logic value '1' is supplied to the access permission signals RDY1 to RDY4. 1 to the processor 10 so that the first processor 10 can access the shared memory area.

Each semaphore cell 20 to 50 may access a processor waiting for access to the shared memory area when the processor accessing the shared memory area terminates the access and provides a logic value '1 through the access request signals REQ1 to REQ4. By providing the logic value '0' as the access permission signals RDY1 to RDY4, the shared memory area can be accessed.

The first processor 10 provides the address of the hardware semaphore to the address decoder 80 through the address bus 60 to access a predetermined shared memory area, and the access request signal REQ1 through the data bus 70. To REQ4), the write control signal / WE is activated to provide the semaphore cells 20 to 50 with access request signals REQ1 to REQ4 for a predetermined shared memory area.

Here, the address provided through the address bus 60 by the first processor 10 is decoded by the address decoder 80 to activate the enable signal / EN so that all semaphore cells 20 to 20 included in the hardware semaphore are activated. Activate the input / output line of 50).

The first processor 10 also addresses the data bus 70 from all semaphore cells 20-50 by addressing the hardware semaphore and deactivating the write control signal / WE (ie, the read control signal is active). Upon receiving the access permission signals RDY1 to RDY4, the access permission signals RDY1 to RDY4 are determined based on the received access permission signals RDY1 to RDY4.

In a conventional hardware semaphore as shown in FIG. 1A, an address of a hardware semaphore is configured in bytes, and the addresses of each semaphore cell 20 to 50 included in the hardware semaphore are divided into bits.

In addition, when the processor performs a write operation of the access request signals REQ1 to REQ4 or a read operation of the access permission signals RDY1 to RDY4 to the semaphore cells 20 to 50 corresponding to the predetermined shared memory area, a byte is used. Since the unit uses the hardware semaphore address, the processor cannot individually designate only the addresses of the semaphore cells 20 to 50 to be accessed to perform read or write operations on the designated semaphore cells 20 to 50.

Accordingly, in a multi-task environment in which a plurality of tasks are executed by any one of two processors included in a dual port memory system, a predetermined task may request an access request signal for a predetermined shared memory area from the predetermined shared memory. If a context switch occurs to another task before transmitting to the semaphore cell corresponding to the region and the access permission signal is received from the semaphore cell, and the other task transmits an access request signal to the other shared memory region, the predetermined previously The access request signal transmitted from the task of the task is replaced with a new value, so that the predetermined task is in a dead lock state.

For example, in a dual port memory system having a first processor, a second processor, and first to fourth shared memory regions, the first task and the second task are executed by the first processor, and the second shared memory region may be Assuming that the first task attempts to access the second shared memory region while the second processor is accessing, first the first task addresses the hardware semaphore and activates the read control signal (ie, the write control signal). Disable) to read the access permission signal stored in the hardware semaphore via the data bus.

If the access permission signal read from the hardware semaphore is a logic value '0', '1', '0', or '1', the first task may access the second shared memory area. 1 ′ is determined, and it is recognized that the second shared memory area is currently being accessed by the second processor.

In this case, since the hardware semaphore has an address in bytes, the semaphore cell corresponding to the second shared memory area is separately selected, and only the access permission signal of the second shared memory area stored in the second semaphore cell cannot be read separately. Read access permission signals stored in all semaphore cells in the gun.

The first task activates the addressing and writing control signals of the hardware semaphores to transmit the access request signals for the second shared memory areas to the hardware semaphores, and the logic values' 0 ',' 0 ',' 0 'and' 1 'are provided to the hardware semaphore via the data bus. Here, since the hardware semaphore has a byte address, the access request signal cannot be separately input to the second semaphore cell, but the access request signal is simultaneously input to all semaphore cells included in the hardware semaphore.

In this case, context switching occurs when the second shared memory area is accessed by the second processor and the access request signal provided from the first task is not reflected by the hardware semaphore as an access permission signal indicating access permission. The work is switched from the first task to the second task.

The second task performs a read operation of an access permission signal from a fourth semaphore cell corresponding to the fourth shared memory area to attempt to access the fourth shared memory area, thereby providing a logical value 'from the hardware semaphore to the access permission signal. 0 ',' 1 ',' 0 ',' 1 'are read.

Here, since the logical value '0', '0', '0', and '1', which are the access request signals output by the first task, are changed by the hardware semaphore before the state transition occurs to the access permission signal, the context switch occurs. The access permission signal is still the logic values '0', '1', '0' and '1'.

The second task determines a logic value '1' corresponding to an access permission signal of the fourth semaphore cell among the access permission signals, and inputs a logic value '0' as the access request signal to input an access request signal to the fourth semaphore cell. Provide ',' 1 ',' 0 ', and' 0 'to the hardware semaphore.

The second processor then terminates access to the second shared memory area. However, the logical value '0', which is the access request signal input to the second semaphore cell by the first task to access the second shared memory region, is changed to '1' by the second task after the context switch occurs. Even when the 2 processor terminates the access, the first task does not receive the logic value '0' as the access permission signal from the second semaphore cell. Therefore, the first task enters the deadlock state, which is an infinite waiting state.

As described above, in the conventional dual port memory having a plurality of shared memory regions, a plurality of semaphore cells corresponding to each shared memory region and controlling mutually exclusive access to each shared memory region are individually accessed and read and Since the write operation cannot be performed, the access request signal input by any one of the plurality of tasks is erased to a new value by another task after the context switch, and thus, the synchronized operation between the plurality of tasks cannot be performed.

Accordingly, a first object of the present invention is to provide a dual port memory having a synchronous control device capable of ensuring synchronized work between tasks in a multitask environment.

A second object of the present invention is to provide a dual port memory system having the synchronous control device.

In addition, a third object of the present invention is to provide a synchronous control method of a dual port memory system capable of guaranteeing synchronized tasks between tasks in a multitask environment.

A dual port memory having a synchronization control device according to an aspect of the present invention for achieving the first object of the present invention described above comprises a memory array having a plurality of shared memory regions, and an address provided through a first port from a first processor. And a first memory interface performing a read or write operation on the plurality of shared memory areas based on a control signal, and the plurality of shared memory areas based on an address and a control signal provided through a second port from a second processor. And a plurality of semaphore cells for controlling mutually exclusive access to the plurality of shared memory regions, the second memory interface performing a read or write operation on the at least one processor of the first processor and the second processor. Each of at least one task being executed And a synchronous access controller configured to independently perform input / output of the access request signal and the access permission signal to the semaphore cell corresponding to the shared memory region. Each of the plurality of semaphore cells may be assigned an independent address.

The synchronous access controller includes a hardware semaphore having the same number as the plurality of shared memory regions, the plurality of semaphore cells corresponding to each of the plurality of shared memory regions, and controlling mutually exclusive access to the corresponding shared memory region. And selecting one semaphore cell among the plurality of semaphore cells based on an address of a semaphore cell provided from each of the at least one task, and performing input / output of the access request signal and the access permission signal with respect to the selected semaphore cell. It may include a synchronization control unit.

Each of the plurality of semaphore cells includes a first input latch for storing a first access request signal provided from one of the first processor and the at least one task, and from any one of the second processor and the at least one task. A second input latch for storing a provided second access request signal, the first access request signal and the second access request signal being received from the first input latch and the second input latch and receiving a first access permission signal and a first access latch signal; A state control unit exclusively providing a second access permission signal, a first state latch storing the first access permission signal provided from the state control unit, and a second state latch storing the second access permission signal provided from the state control unit It may include.

The first input latch, the second input latch, and the state controller may be configured as S-R latches. The first state latch and the second state latch may be configured as a D-flip flop. The synchronization controller is configured to decode an address of the semaphore cell and to select a semaphore cell among the plurality of semaphore cells, and to receive an address of the semaphore cell as a selection input, and to select the semaphore based on the selection input. A multiplexer for connecting an output line of the cell and a data bus, a demultiplexer for receiving an address of the semaphore cell as a selection input and for connecting the data bus and an input line of the selected semaphore cell based on the selection input and an activated write And a tri-state buffer for writing the access request signal to the selected semaphore cell based on a control signal. The decoder may input as many address bits as the number of the plurality of semaphore cells from the least significant bit (LSB) among the addresses of the semaphore cells. The memory array may have a DRAM cell structure. The first memory interface and the second memory interface may be SDRAM memory interfaces.

In addition, a dual-port memory system having a synchronous control apparatus according to an embodiment of the present invention for achieving the above-described second object of the present invention is a memory array having a first processor, a second processor and a plurality of shared memory areas. A first memory interface configured to perform a read or write operation on the plurality of shared memory regions based on an address and a control signal provided from a first processor through a first port, and provided through a second port from a second processor; A second memory interface performing a read or write operation on the plurality of shared memory regions based on an address and a control signal, and a plurality of semaphore cells controlling mutually exclusive access to the plurality of shared memory regions; At least running on any one of a processor and the second processor Each of the one or more tasks includes a dual port memory having a synchronous access control unit to perform input and output of the access request signal and the access permission signal independently of the semaphore cell corresponding to the shared memory region to be accessed. The first processor may be a modem processor, and the second processor may be an application processor for executing an application program.

In addition, the synchronization control method of the dual-port memory system according to an embodiment of the present invention for achieving the third object of the present invention includes the steps of providing the address of the semaphore cell corresponding to the shared memory region to be accessed; Decoding the address of the provided semaphore cell to select the semaphore cell, and inputting an access request signal or outputting an access permission signal to the selected semaphore cell. The address of the semaphore cell may be allocated in byte units. Decoding the address of the provided semaphore cell and selecting the semaphore cell may include activating an input / output line of the selected semaphore cell by performing multiplexing and demultiplexing using the address of the provided semaphore cell as a selection input. Can be. The step of inputting an access request signal or outputting an access permission signal to the selected semaphore cell may include inputting an access request signal to the selected semaphore cell if a write control signal is activated, and from the selected semaphore cell if the write control signal is deactivated. An access permission signal may be output.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In describing the drawings, similar reference numerals are used for similar components.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

2 is a block diagram illustrating a configuration of a dual port memory system having a synchronous control device according to an embodiment of the present invention.

2, a dual port memory system according to an embodiment of the present invention may include a first processor 110, a second processor 120, a first external bus interface 130 (EBI), and a first processor 110. 2 includes an external bus interface 140 and a dual port memory 200.

The dual port memory 200 includes a memory cell array 210, a first memory interface 220, a second memory interface 230, and a synchronous access controller 295. The memory cell array 210 may include first to fourth shared memory areas 211 to 217.

The first processor 110 may be a modem processor used in a portable terminal such as a mobile phone, and the second processor 120 may be an application processor for executing an application program such as a video processor or a multimedia processor used in the portable terminal. Can be.

The first external bus interface 130 and the second external bus interface 140 serve as a kind of memory controller, and an external bus interface of a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) may be used. Hereinafter, in an embodiment of the present invention, it is assumed that the first external bus interface 130 and the second external bus interface 140 are SDRAM external bus interfaces.

The dual port memory 200 is connected to the first processor 110 having the first external bus interface 130 through the first port 150, and the second external bus interface 140 through the second port 160. It is connected to the second processor 120 having a).

The first processor 110 provides the address ADD1, the plurality of control signals CTR1 and the clock CLK1 to the dual port memory 200 through the first port 150 of the dual port memory 200. The dual port memory 200 performs input / output of the first processor 110 and the data DQ1 using the first port 150 and the first external bus interface 130.

In addition, the second processor 120 transmits the address ADD2, the plurality of control signals CTR2, and the clock CLK2 to the dual port memory 200 through the second port 160 of the dual port memory 200. The dual port memory 200 performs input / output of the second processor 120 and the data DQ2 using the second port 160 and the second external bus interface 140.

The memory cell array 210 has a unit memory cell structure of a DRAM and includes first to fourth shared memory regions 211 to 217. Each of the first to fourth shared memory areas 211 to 217 may be formed in a bank unit having a predetermined size. In addition, each shared memory area may be configured in units of blocks having a predetermined size in one bank.

In addition, in the dual port memory system according to another exemplary embodiment, the plurality of first processors 110 to which the first processor 110 and the second processor 120 independently access the memory cell array 210 may be provided. A dedicated memory area (not shown) and a plurality of dedicated memory areas (not shown) of the plurality of second processors 120 may be included.

In the dual port memory system according to the exemplary embodiment of the present invention illustrated in FIG. 2, the first to fourth shared memory regions 211 to 217 are present. However, in another exemplary embodiment, a greater number of shares are provided. Memory areas may be provided, or fewer shared memory areas may be provided.

The first memory interface 220 is configured as an SDRAM memory interface, and has an address ADD1, a control signal CTR1, a clock CLK1, and data DQ1 from the first processor 110 through the first port 150. , Decodes the address ADD1 into a row address and a column address, outputs the decoded address I_AD1 to the memory cell array 210, and reads, writes, and refreshes an operation timing of the memory cell array 210. The data DQ1 is read from the memory cell array 210 or written to the memory cell array 210.

To this end, the first memory interface 220 includes a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and input / output used in a general SDRAM interface. A buffer (not shown) may be included.

The second memory interface 230 is configured as an SDRAM memory interface, and includes an address ADD2, a control signal CTR2, a clock CLK2, and data DQ2 from the second processor 120 through the second port 160. After inputting the signal, the address ADD2 is decoded into a row address and a column address, and then the decoded address I_AD2 is output to the memory cell array 210, and operations such as reading, writing, and refreshing the memory cell array 210 are performed. The data DQ2 is read from or written to the memory cell array 210 according to the timing.

To this end, the second memory interface 230 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), an input / output buffer (not shown) used in a general SDRAM interface, and the like.

The synchronous access control unit 295 includes a plurality of semaphore cells 260 to 290 for controlling mutually exclusive access to a plurality of shared memory areas 211 to 217, and the first processor 110 or the second processor. When a plurality of tasks are executed at 120, each task may perform input / output of an access request signal and an access permission signal independently of a semaphore cell corresponding to a shared memory area to which each task is to be accessed.

The synchronous access controller 295 may include a synchronous controller 240 and a hardware semaphore 250.

The synchronization controller 240 receives respective addresses of the semaphore cells 260 to 290 included in the hardware semaphore 250 from the first processor 110 and the second processor 120, decodes the received address, and then decodes the semaphore. The input / output lines of the cells 260 to 290 are individually activated, and data DQ1 and DQ2 are input or output to the semaphore cells 260 to 290 where the input / output lines are activated according to the write control signal / WE.

Herein, the data DQ1 and DQ2 input to each semaphore cell 260 through 290 are access request signals REQ1 for the shared memory areas 211 through 217 provided from the first processor 110 or the second processor 120. And REQ2) and the data DQ1 and DQ2 output from the semaphore cells 260 to 290 are access permission signals RDY1 and RDY2 to the shared memory areas 211 to 217.

In addition, the synchronization controller 240 may include the semaphore cells 260 to 260 included in the hardware semaphore 250 from each task when a plurality of tasks are executed in any one of the first processor 110 and the second processor 120. Each address of 290 is input, the inputted address is decoded to individually activate the input / output lines of the semaphore cells 260 to 290, and the semaphore cell 260 on which the input / output line is activated according to the write control signal / WE. 290 to 290 to input or output data DQ1 and DQ2.

Here, the data DQ1 and DQ2 input to each semaphore cell 260 to 290 are shared memory regions provided from respective tasks executed in any one of the first processor 110 and the second processor 120. The access request signals REQ1 and REQ2 to the 211 to 217 and the data DQ1 and DQ2 output from the semaphore cells 260 to 290 are access permission signals RDY1 to the shared memory areas 211 to 217. , RDY2).

For example, the access request signals REQ1 and REQ2 may have a logic value of '0' when the first processor 110 and the second processor 120 or the task attempt to access a predetermined shared memory area 211 to 217. When the processor or task that has accessed the predetermined shared memory areas 211 to 217 intends to terminate the access, the logical value is '1'.

In addition, the access permission signals RDY1 and RDY2 output from the semaphore cells 260 to 290 may access a shared memory area 211 to 217 corresponding to each semaphore cell 260 to 290. If it is not, the logical value '0' indicating access is possible, and if the shared memory areas 211 to 217 are accessed by another processor or task, the logical value '1' indicates that access is impossible.

The hardware semaphore 250 includes the same number of semaphore cells 260-290 as the number of shared memory areas 211-217, and each semaphore cell 260-290 has each shared memory area 211-217. ) And one-to-one correspondence.

That is, the first shared memory area 211 corresponds to the first semaphore cell 260, and the second shared memory area 213 corresponds to the second semaphore cell 270. In addition, the third shared memory area 215 and the fourth shared memory area 217 correspond to the third semaphore cell 280 and the fourth semaphore cell 290, respectively.

In the dual port memory and the dual port memory system according to an embodiment of the present invention, each of the first to fourth semaphore cells 260 to 290 is assigned an individual address in units of bytes, and under the control of the synchronization controller 240, respectively. Independent input and output of data DQ1 and DQ2 to semaphore cells 260 to 290 of FIG.

Each semaphore cell 260-290 controls mutually exclusive access between the first processor 110 and the second processor 120 to the corresponding shared memory areas 211-217 to ensure inter-processor synchronized work. do.

In addition, each semaphore cell 260 through 290 may share a shared memory area 211 through 217 between a plurality of tasks executed by any one of the first processor 110 and the second processor 120 and another processor. Control mutually exclusive access to ensure the synchronized work between multiple tasks and processors.

FIG. 3A is a block diagram illustrating a detailed configuration of the semaphore cell illustrated in FIG. 2, and illustrates a first semaphore cell 260 among the first to fourth semaphore cells 260 to 290 included in the hardware semaphore 250. The second to fourth semaphore cells 270 to 290 have the same structure as the first semaphore cell 260.

Referring to FIG. 3A, the first semaphore cell 260 includes a first input latch 261, a second input latch 262, a state control unit 263, a first state latch 264, and a second state latch 265. ).

The first input latch 261 receives an access request signal REQ1 for the first shared memory area 211 provided through the first memory interface 220 from the first processor 110, and provides the provided access request signal ( REQ1) is latched and stored.

The second input latch 262 receives the access request signal REQ2 for the first shared memory area 211 from the second processor 120 through the second memory interface 230, and provides the provided access request signal REQ2. ) To latch and save. Here, the first input latch 261 and the second input latch 262 may be configured as an S-R latch.

The access request signals REQ1 and REQ2 for the first processor 110 and the second processor 120 to access the first shared memory area 211 may be logical values '0', and the first processor 110 may be used. ) And the second processor 120 terminate the access to the shared memory area 217, the access request signals REQ1 and REQ2 may be logical values '1'.

The state controller 263 receives the access request signals REQ1 and REQ2 latched to the first input latch 261 and the second input latch 262, and exclusive access permission signals RDY1 and RDY2 according to the current state. ) Is provided to the first state latch 264 and the second state latch 265. In this case, the state controller 263 may be configured as an S-R latch.

The first state latch 264 latches and stores the access permission signal RDY1 provided from the state control unit 263, and the second state latch 265 latches the access permission signal RDY2 provided from the state control unit 263. Save it. Here, the first state latch 264 and the second state latch 265 may be implemented as a D-flip flop.

FIG. 3B is a state table illustrating the operation of the semaphore cell shown in FIG. 3A.

3A and 3B, when the dual port system is initialized at time t0, the access permission signals RDY1, which are output from the first state latch 264 and the second state latch 265 of the first semaphore cell 260, are output. RDY2) becomes logical values '1' and '1', respectively.

Subsequently, at time t1, the first processor 110 sets a logic value '0' as the access request signal REQ1 for the first shared memory area 211 to the first input latch 261 of the first semaphore cell 260. In this case, the state controller 263 provides a logic value '0' to the first state latch 264 as an access permission signal RDY1, and the access permission signal RDY1 stored in the first state latch 264. ) Is transmitted to the first processor 110 under the control of the synchronization controller 240 so that the first processor 110 approaches the first shared memory area 211.

In operation t2, the second processor 120 sets a logic value '0' as the access request signal REQ2 for the first shared memory area 211 to the second input latch 262 of the first semaphore cell 260. ), The state controller 263 does not change the access permission signal RDY2 stored in the second state latch 265 because the first processor 110 is currently approaching the first shared memory area 211. Instead, the access request signal REQ2 transmitted by the second processor 120 remains latched by the second input latch 262.

Accordingly, the access permission signal RDY2 for the second processor 120 is still a logic value '1', and the second processor 120 cannot access the first shared memory area 211.

When the first processor 110 terminates the access to the first shared memory area 211 at time t3 and transmits a logic value '1' to the first input latch 261 using the access request signal REQ1, the state The control unit 263 changes the access permission signals RDY1 and RDY2 stored in the first state latch 264 and the second state latch 264 so that the access permission signals RDY1 and RDY2 are logical values '1', respectively. Is '0'.

The state-converted access permission signals RDY1 and RDY2 are transmitted to the first processor 110 and the second processor 120 under the control of the synchronization controller 240, so that the second processor 120 shares the first share. The memory area 211 is accessible.

Subsequently, at time t4, the first processor 110 sets a logic value '0' as the access request signal REQ1 for the first shared memory area 211 to the first input latch 261 of the first semaphore cell 260. In this case, the state controller 263 does not change the access permission signal RDY1 stored in the first state latch 264 because the second processor 120 is currently approaching the first shared memory area 211. The access request signal REQ1 transmitted by the first processor 110 remains latched in the first input latch 261.

Therefore, the access permission signal RDY1 for the first processor 110 is still a logic value '1', and the first processor 110 cannot access the first shared memory area 211.

When the second processor 120 terminates the access to the first shared memory area 211 at time t5 and transmits a logic value '1' to the second input latch 262 by the access request signal REQ, the state controller 263 changes the access permission signals RDY1 and RDY2 stored in the first state latch 264 and the second state latch 265, and the access permission signals RDY1 and RDY2 are logical values' 0 'and', respectively. 1 '. In addition, the changed access permission signals RDY1 and RDY2 are transmitted to the first processor 110 and the second processor 120 under the control of the synchronization controller 240, so that the first processor 110 receives the first shared memory area. 211 can be accessed.

Thereafter, when the first processor 110 terminates the access to the first shared memory area 211 at time t6 and transmits a logic value '1' to the first input latch 261 using the access request signal REQ1, The control unit 263 changes the access permission signal RDY1 stored in the first state latch 264 accordingly, and the access permission signal RDY1 becomes a logic value '1'.

FIG. 4A is a circuit diagram showing the detailed configuration of the synchronization control device shown in FIG. 2, and FIG. 4B is a truth table showing the operation of the synchronization control device.

4A illustrates only the one of the first port 150 and the second port 160 of the dual port memory system shown in FIG. 2 connected to the first port 150. The connection between the synchronous control device 240 and the second port 160 is also the same as that shown in FIG. 4A.

4A and 4B, the synchronization control device 240 according to an embodiment of the present invention may include a decoder 241, a multiplexer 242, a demultiplexer 243, and a plurality of three-state buffers 245 and 246. Include.

The decoder 241 decodes the addresses of the first to fourth semaphore cells 260 to 290 provided through the address bus 247 to correspond to the semaphores corresponding to the decoded addresses of the first to fourth semaphore cells 260 to 290. By enabling the three-state buffer 245 connected to the input / output line of the cell, the input / output of the data DQ1 is enabled to the enabled semaphore cell. Here, the data DQ1 input to the semaphore cell becomes the access request signals REQ1.1 to REQ1.4, and the data DQ1 output from the semaphore cell becomes the access permission signals RDY1.1 to RDY1.4. .

Each semaphore cell 260 to 290 has an address in byte units, and an address input to the decoder 241 is as many as the number of semaphore cells in the least significant bit of the address bytes of the semaphore cell. Address bits are input.

In FIG. 4A, since the number of semaphore cells 260 through 290 is four, the decoder 241 has two input lines and four output lines, and the two inputs of the decoy have the least significant bits A1 and the addresses of the semaphore cells. A0 is entered. The decoder decodes the addresses A1 and A0 of the semaphore cell to enable any one of the four outputs EN0 to EN3.

The multiplexer 242 receives the addresses A1 and A0 of the semaphore cell as a selection input and performs multiplexing according to the provided addresses A1 and A0 to connect the output line and the data bus 248 of the selected semaphore cell. Data DQ1 output from the semaphore cell with the output line enabled is output to the data bus 248. The data DQ1 output here is the access permission signals RDY1.1 to RDY1.4.

The demultiplexer 243 receives the addresses A1 and A0 of the semaphore cell as a selection input and performs demultiplexing according to the provided addresses A1 and A0 to connect the input line and the data bus 248 of the selected semaphore cell. As a result, the data DQ1 provided from the data bus 248 is provided to the input line of the selected semaphore cell.

Since the multiplexer 242 and the demultiplexer 243 are provided with the addresses A1 and A0 of the same semaphore cell as respective selection inputs, the data DQ1 of the data for the same semaphore cell is determined according to the addresses A1 and A0 of the semaphore cell. Multiplexing and demultiplexing are performed to enable input and output.

In addition, the synchronization control device 240 determines the input and output of the data DQ1 for the semaphore cell selected according to the write control signal / WE. When the write control signal / WE is activated, input of data DQ1 for the selected semaphore cell, that is, a write operation is performed, and when the write control signal / WE is deactivated, output of the data DQ1 for the selected semaphore cell. That is, a read operation is performed.

As an example of the operation of the synchronization control device 240 with reference to the truth table shown in FIG. 4B, the addresses A1 and A0 of the semaphore cells input through the address bus 247 are logical values '1, 0'. When the write control signal / WE is a logic value '0', the decoder 241 decodes the logic values '1 and 0' to activate the output EN2 so that the third semaphore cell 280 is selected.

In addition, the demultiplexer 243 receives a logic value '1, 0', which is the address A1, A0, of the semaphore cell as a selection input and performs demultiplexing to access the access request signal, which is the data DQ1 provided from the data bus 248. (REQ1.3) to the input line of the third semaphore cell 280.

In addition, the input line of the data DQ1 is activated by the logic value '0', which is the write control signal / WE, so that the access request signal RE1.3 provided through the demultiplexer 243 on the data bus 248 is generated. 3 is input to the semaphore cell 280.

As shown in FIGS. 4A and 4B, according to an embodiment of the present invention, addresses of semaphore cells 260 to 290 which control mutually exclusive access to each shared memory area are separately designated, and addresses of the semaphore cells (A1, According to A0), each semaphore cell is separately selected to input and output the access request signals REQ1 and REQ2 and the access permission signals RDY1 and RDY2 to the selected semaphore cell to ensure synchronized work between the processor and the task.

FIG. 5 is a state table for describing a synchronous control method of a dual port memory system according to an exemplary embodiment of the present invention, wherein a first task and a second task are executed by the first processor 110, and the first task and the first task are illustrated in FIG. The state of the first to fourth semaphore cells 260 to 290 when context switching occurs between two tasks is shown.

First, each of the first input latches 261 to 291 of the first to fourth semaphore cells 260 to 290 at the time t0 has the logic values '0, 1, 0, 1' and the first to fourth semaphore cells. Each first state latch 264-294 of 260-290 has a logic value of '0, 1, 0, 1'.

At time t0, the first task grants access stored in the first state latch 274 of the second semaphore cell 270 corresponding to the second shared memory area 213 to access the second shared memory area 213. Read logical value '1' which is signal RDY1.

The first state latch 294 of the fourth semaphore cell 290 corresponding to the fourth shared memory region 217 so that the context switch occurs at time t1 so that the second task may access the fourth shared memory region 217. Read the logical value '1' which is the access permission signal (RDY1) stored in the system.

In operation t2, the second task transmits a logic value '0', which is an access request signal REQ1 for the fourth shared memory area 217, to the first input latch 291 of the fourth semaphore cell 290. When there is no access of the second processor 120 to the fourth shared memory area 217, the state controller of the fourth semaphore cell 290 may logic the first state latch 294 of the fourth semaphore cell 290. The value '0' is stored.

Thereafter, a context switch occurs again at time t3, and the first task continues to access the second shared memory area 213 at time t0 to the first input latch 271 of the second semaphore cell 270. The logical value '0', which is the access request signal REQ1, is transmitted, and when there is no access of the second processor 120 to the second shared memory area 213, the state controller of the second semaphore cell 270 may transmit the logical value '0'. The logic value '0' is stored in the first state latch 274 of the two semaphore cells 270.

As shown in FIG. 5, in a dual port memory system according to an embodiment of the present invention, an address is assigned to a semaphore cell that controls mutually exclusive access to each shared memory area, and each semaphore is allocated using the assigned address. By inputting and outputting data DQ independently to a cell, synchronized tasks of each task are guaranteed even when a context exchange occurs between tasks.

FIG. 6 is a flowchart illustrating a process of accessing a shared memory in a dual port memory system according to an exemplary embodiment of the present invention, wherein the processor of any one of the first processor 110 and the second processor 120 or one of the processors may be used. A task of any one of a plurality of tasks to be executed is performed to access a predetermined shared memory area.

In FIG. 6, it is assumed that a first task among a plurality of tasks executed in the first processor 110 approaches the first shared memory area 211.

Referring to FIG. 6, first, the first task receives an address of the first semaphore cell 260 corresponding to the first shared memory area 217 to access the first shared memory area 211. In step 301.

Thereafter, the decoder 241 of the synchronization controller 240 decodes the addresses A1 and A0 of some of the addresses of the first semaphore cell 260 provided through the address bus 247. At the same time, the addresses A1 and A0 of the first semaphore cell 260 provided through the address bus 247 are provided as selection inputs of the multiplexer 242 and the demultiplexer 243 to provide the address bus 247 and the first input. The input / output lines of the 1 semaphore cell 260 are connected to each other so that the data DQ1 output from the first semaphore cell 260 is provided to the data bus 248 through the multiplexer 242 or data provided from the data bus 248. (DQ1) may be input to the first semaphore cell 260 through the demultiplexer 243 (step 303).

When the addresses A1 and A0 provided to the decoder 241 through the address bus 247 are decoded, one of the four decoder outputs EN0 corresponding to the addresses A1 and A0 is activated, and the activated output is activated. The tri-state buffer connected to (EN0) is activated. The semaphore cell, ie, the first semaphore cell 260, to which the input / output line is connected to the activated tri-state buffer is selected (step 305).

The addresses input to the decoder 241 may be as many addresses A1 and A0 as the number corresponding to the number of semaphore cells from the least significant bit LSB among the addresses of the first semaphore cell 260.

For example, in a dual port memory system having eight shared memory areas and semaphore cells, three bits are used to distinguish the actual semaphore cells from the least significant bit of the byte unit address allocated to each semaphore cell. When the number of shared memory areas and semaphore cells is four, as in the dual port memory system according to the exemplary embodiment of FIG. 2, two bits are selected from the least significant bit among the address of the byte unit allocated to each semaphore cell. Is used to distinguish the actual semaphore cells.

Then, the write control signal / WE is provided to the synchronization control unit 240 (step 307). Here, when the write control signal / WE is activated, the data DQ1 provided from the data bus 248, that is, the access request signal REQ1, is transmitted through the input line of the first semaphore cell 260 through the demultiplexer 242. Stored in the first input latch 261 of the first semaphore cell 260 (step 309) and stored in the first state latch 264 of the first semaphore cell 260 when the write control signal / WE is deactivated. An access permission signal RDY1 is provided to the data bus 248 via the multiplexer 242 (step 311).

According to the synchronous control method of the dual port memory having the synchronous control device, the dual port memory system having the synchronous control device, and the dual port memory system, a separate address is assigned to each semaphore cell corresponding to each shared memory area. In addition, a processor or a task that attempts to access a predetermined shared memory area independently records an access request signal in a semaphore cell corresponding to the predetermined shared memory area, and reads an access permission signal.

Therefore, even in a multi-task environment in which a plurality of tasks are executed in one processor, continuous synchronization between tasks can be guaranteed even when a context switch between tasks occurs.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. I will be able.

Claims (19)

A memory array having a plurality of shared memory regions; A first memory interface configured to perform a read or write operation on the plurality of shared memory regions based on an address and a control signal provided from a first processor through a first port; A second memory interface configured to perform a read or write operation on the plurality of shared memory regions based on an address and a control signal provided from a second processor through a second port; And At least one task that controls a mutually exclusive access to the plurality of shared memory regions and includes a plurality of semaphore cells, each assigned an independent address, and which is executed in any one of the first processor and the second processor And a synchronous access control unit configured to independently perform input / output of an access request signal and an access permission signal to the semaphore cell corresponding to the shared memory region to be accessed by the independent address. delete The method of claim 1, wherein the synchronous access control unit A hardware semaphore having the same number as the plurality of shared memory regions and including the plurality of semaphore cells corresponding to each of the plurality of shared memory regions and controlling mutually exclusive access to the corresponding shared memory region; And Selecting one semaphore cell of the plurality of semaphore cells based on an address of a semaphore cell provided from each of the at least one task, and performing input / output of the access request signal and the access permission signal to the selected semaphore cell Dual port memory, characterized in that it comprises a synchronization control unit. The method of claim 3, wherein each of the plurality of semaphore cells A first input latch for storing a first access request signal provided from one of the first processor and the at least one task; A second input latch for storing a second access request signal provided from one of the second processor and the at least one task; A state control unit receiving the first access request signal and the second access request signal from the first input latch and the second input latch and exclusively providing a first access permission signal and a second access permission signal; A first state latch for storing the first access permission signal provided from the state control unit; And And a second state latch for storing the second access permission signal provided from the state controller. The dual port memory of claim 4, wherein the first input latch, the second input latch, and the state controller are configured as S-R latches. 5. The dual port memory of claim 4 wherein the first state latch and the second state latch are configured as D-flip flops. The method of claim 3, wherein the synchronization control unit A decoder configured to decode the address of the semaphore cell and select one semaphore cell among the plurality of semaphore cells; A multiplexer receiving an address of the semaphore cell as a selection input and connecting an output line of the selected semaphore cell and a data bus based on the selection input; A demultiplexer configured to receive an address of the semaphore cell as a selection input and connect the data bus and an input line of the selected semaphore cell based on the selection input; And And a tri-state buffer configured to perform a write operation of the access request signal to the selected semaphore cell based on an activated write control signal. 8. The dual port memory of claim 7, wherein the decoder receives the number of address bits corresponding to the number of the plurality of semaphore cells from the least significant bit (LSB) among the addresses of the semaphore cells. 2. The dual port memory of claim 1 wherein the memory array has a DRAM cell structure. The dual port memory of claim 1, wherein the first memory interface and the second memory interface are SDRAM memory interfaces. A first processor; A second processor; And A memory array having a plurality of shared memory regions, a first memory interface configured to perform a read or write operation on the plurality of shared memory regions based on an address and a control signal provided through a first port from a first processor; A second memory interface for performing a read or write operation on the plurality of shared memory areas based on an address and a control signal provided through a second port from a second processor, and controlling mutually exclusive access to the plurality of shared memory areas, respectively. The semaphore cell includes a plurality of semaphore cells assigned with independent addresses, and the at least one semaphore cell corresponding to the shared memory region to which each of at least one or more tasks executed by any one of the first processor and the second processor is to be accessed is independent of the semaphore cell. Independently using an address Near-request signal and a dual-port memory system including a dual-port memory that has a synchronous control unit for access to perform input and output of the access permission signal. delete The method of claim 11, wherein the synchronous access control unit A hardware semaphore having the same number as the plurality of shared memory regions and including the plurality of semaphore cells corresponding to each of the plurality of shared memory regions and controlling mutually exclusive access to the corresponding shared memory region; And Selecting one semaphore cell among the plurality of semaphore cells based on an address of a semaphore cell provided from each of the at least one task, and performing input / output of the access request signal and the access permission signal with respect to the selected semaphore cell; A dual port memory system comprising a synchronization control unit. The method of claim 13, wherein the synchronization control unit A decoder configured to decode the address of the semaphore cell and select one semaphore cell among the plurality of semaphore cells; A multiplexer receiving an address of the semaphore cell as a selection input and connecting an output line of the selected semaphore cell and a data bus based on the selection input; A demultiplexer configured to receive an address of the semaphore cell as a selection input and connect the data bus and an input line of the selected semaphore cell based on the selection input; And And a tri-state buffer configured to perform a write operation of the access request signal to the selected semaphore cell based on an activated write control signal. 12. The dual port memory system of claim 11 wherein the first processor is a modem processor and the second processor is an application processor that executes an application. A synchronization method of a dual port memory system including a first processor, a second processor, and a plurality of shared memory areas, Providing an address of a semaphore cell corresponding to a shared memory area to be accessed; Decoding the address of the provided semaphore cell to select the semaphore cell; And inputting an access request signal or an access permission signal to the selected semaphore cell. 17. The method of claim 16, wherein the address of the semaphore cell is allocated in units of bytes. 17. The method of claim 16, wherein decoding the address of the provided semaphore cell to select the semaphore cell comprises: And activating an input / output line of the selected semaphore cell by performing multiplexing and demultiplexing with the address of the provided semaphore cell as a selection input. The method of claim 16, wherein inputting an access request signal or outputting an access permission signal to the selected semaphore cell comprises: And an access request signal is input to the selected semaphore cell when a write control signal is activated, and an access permission signal is output from the selected semaphore cell when the write control signal is deactivated.

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