JP2018010698A - Data writing request processing method and storage array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data writing request processing method and a storage array.SOLUTION: There are provided a data writing request processing method and a storage array, therein a controller is connected via a switching device to a cache device, and an input/output manager is connected via the switching device to the controller, and the input/output manager is connected via the switching device to the cache device, and the controller acquires a cache address from a cache device for data to be written in accordance with a data writing request, and the controller transmits the identifier and cache address of the cache device via the switching device to the input/output manager, and the input/output manager writes the data to be written in the cache address via the switching device.SELECTED DRAWING: Figure 2

Description

  The present invention relates to the field of information technology, and in particular, to a data write request processing method and a storage array.

  A storage array typically includes one engine, with one engine including two controllers, commonly referred to as a dual controller structure. As shown in FIG. 1, the storage array includes an input / output manager A, an input / output manager B, a controller A, and a controller B. The input / output manager A is connected to the controller A, and the input / output manager B is connected to the controller B. The controller A includes a peripheral component interconnect express (PCIe) switch A, a central processing unit (CPU) A, and a memory A; the controller B includes a peripheral component interconnect express ( It includes a peripheral component interconnect (PCIe) switch B, a central processing unit (CPU) B, and a memory B. The PCIe switch A is connected to the PCIe switch B. In the storage array shown in FIG. 1, the input / output manager A receives a data write request. The target logical unit (Logical Unit, LU) of the data write request is homed to the controller A. That is, the controller A writes the data held in the data write request to the target LU. The input / output manager A transmits a data write request to the CPU A via the PCIe switch A of the controller A, and the CPU A writes the data and metadata held in the data write request to the memory A. CPU A writes the data and metadata in memory A to the hard disk according to the settings of the storage array.

  The above-described data writing process in the storage array consumes the CPU computing power of the controller and the memory resources of the controller, and seriously affects the performance of the storage array.

  Embodiments of the present invention provide a data write request processing method and a storage array.

According to a first aspect, an embodiment of the present invention provides a method for processing a data write request, the method being applied to a storage array, the storage array comprising: an input / output manager; a switching device; And a first cache device, wherein the I / O manager is connected to the switching device; the first controller is connected to the switching device; the first cache device is connected to the switching device; Connected to a hard disk in the array;
Sending, by the input / output manager, a data write request to the first controller via the switching device;
Obtaining a first cache address assigned to data to be written in the first cache device by the first controller in accordance with the data write request;
Sending, by the first controller, the identifier of the first cache device and the first cache address to the I / O manager via the switching device;
Writing data to be written to the first cache address via the switching device by the I / O manager according to the identifier of the first cache device and the first cache address;
including.

Referring to the first aspect of the present invention, in a first possible implementation manner, the data write request holds the address of the data to be written;
Receiving a response sent by the first cache device indicating successful writing of the data to be written by the I / O manager;
Notifying the first controller by the I / O manager via the switching device that the data to be written is written to the first cache address;
Establishing a correspondence between the address of the data to be written, the identifier of the first cache device and the first cache address according to the notification by the first controller;
Is further included.

Referring to the first aspect of the present invention, in a second possible implementation manner, the storage array further comprises a second cache device, the second cache device is connected to the switching device, and the method includes:
Obtaining, by the first controller, a second cache address assigned to data to be written in the second cache device according to the data write request;
Sending, by the first controller, the identifier of the second cache device and the second cache address to the I / O manager via the switching device;
Writing data to be written to the second cache address via the switching device by the I / O manager according to the identifier of the second cache device and the second cache address;
Is further included.

Referring to the first aspect of the present invention, in a third possible implementation manner, the storage array further comprises a second cache device, the second cache device is connected to the switching device, and the method includes:
Obtaining, by the first controller, a second cache address assigned to data to be written in the second cache device according to the data write request;
Sending a data write instruction to the first cache device by the first controller via the switching device, the data write instruction holding an identifier of the second cache device and a second cache address; Steps and;
Writing data to be written by the first cache device to the second cache address via the switching device in accordance with a data write instruction;
Is further included.

Referring to the first aspect of the invention, in a fourth possible implementation scheme, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic where the data to be written is located. Including the identifier of the unit LU, the logical block address of the data to be written and the length of the data to be written; the step of sending a data write request by the I / O manager via the switching device to the first controller:
Querying the homing relationship between the target LU stored in the I / O manager and the controller by the I / O manager according to the identifier of the target LU and determining that the first controller is the home controller of the target LU;
Sending, by the input / output manager, a data write request to the first controller via the switching device;
In particular.

Referring to the first aspect of the present invention, in a fifth possible implementation scheme, the data write request holds the address of the data to be written and the address of the data to be written is the target logic where the data to be written is located. Including the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the storage array further comprises a second controller, the second controller being connected to the switching device; The steps of sending a data write request to the first controller via the switching device are:
Sending a data write request by the I / O manager to the second controller via the switching device;
Determining by the second controller according to the identifier of the target LU that the first controller is the home controller of the target LU;
Sending a data write request by the second controller to the first controller via the switching device;
In particular.

According to a second aspect, one embodiment of the present invention provides a storage array, the storage array comprising an input / output manager, a switching device, a first controller, and a first cache device. The output manager is connected to the switching device; the first controller is connected to the switching device; the first cache device is connected to the switching device; the switching device is connected to a hard disk in the storage array;
The I / O manager is configured to send a data write request to the first controller via the switching device;
The first controller obtains a first cache address assigned to data to be written in the first cache device according to the data write request, and uses the identifier of the first cache device and the first cache address as the switching device. Configured to send to the I / O manager via
The input / output manager is further configured to write data to be written to the first cache address via the switching device according to the identifier of the first cache device and the first cache address.

With reference to the second aspect of the invention, in a first possible implementation manner, the data write request holds the address of the data to be written;
The I / O manager is further configured to receive a response sent by the first cache device indicating successful writing of the data to be written;
The I / O manager is further configured to notify the first controller that the data to be written is written to the first cache address via the switching device;
The first controller is further configured to establish a correspondence between the address of the data to be written, the identifier of the first cache device, and the first cache address according to the notification.

Referring to the second aspect of the present invention, in a second possible implementation manner, the storage array further comprises a second cache device, the second cache device being connected to the switching device;
The first controller is further configured to obtain a second cache address assigned to the data to be written in the second cache device according to the data write request;
The first controller is further configured to send the identifier of the second cache device and the second cache address to the I / O manager via the switching device;
The input / output manager is further configured to write data to be written to the second cache address via the switching device according to the identifier of the second cache device and the second cache address.

Referring to the second aspect of the present invention, in a third possible implementation manner, the storage array further comprises a second cache device, wherein the second cache device is connected to the switching device;
The first controller is further configured to obtain a second cache address assigned to the data to be written in the second cache device according to the data write request;
The first controller is further configured to send a data write instruction to the first cache device via the switching device, the data write instruction holding an identifier of the second cache device and a second cache address. ;
The first cache device is configured to write data to be written to the second cache address via the switching device in accordance with a data write instruction.

Referring to the second aspect of the present invention, in a fourth possible implementation scheme, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic where the data to be written is located. Including the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the I / O manager sends a data write request to the first controller via the switching device:
Querying the homing relationship between the target LU stored in the I / O manager and the controller by the I / O manager according to the identifier of the target LU and determining that the first controller is the home controller of the target LU;
Sending a data write request by the I / O manager to the first controller via the switching device;
In particular.

Referring to the second aspect of the present invention, in a fifth possible implementation scheme, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic where the data to be written is located. Including the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the storage array further comprises a second controller, the second controller being connected to the switching device; Sending a data write request to the first controller via the switching device is:
Sending a data write request by the I / O manager to the second controller via the switching device;
Determining by the second controller that the first controller is the home controller of the target LU according to the identifier of the target LU;
Sending a data write request by the second controller to the first controller via the switching device;
In particular.

  According to the data write request processing method and the storage array provided in the embodiment of the present invention, the controller is connected to the cache device via the switching device, and the input / output manager is connected to the controller via the switching device. A manager is connected to the cache device via the switching device. The controller obtains a cache address from the cache device for the data to be written according to the data write request, and the controller sends the identifier of the cache device and the cache address to the input / output manager via the switching device. Writes the data to be written to the cache address via the switching device, thereby saving the controller's CPU computing resources and the controller's memory resources and improving the data writing efficiency.

  BRIEF DESCRIPTION OF THE DRAWINGS To describe the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments. The accompanying drawings in the following description show merely some embodiments of the invention, and other drawings can be further derived from these accompanying drawings.

It is a block diagram of the storage array in a prior art. 1 is a configuration diagram of a storage array according to an embodiment of the present invention. FIG. It is a flowchart of the process of the data write request by one Embodiment of this invention. It is a flowchart of the process of the data write request by one Embodiment of this invention. 6 is a flowchart of data read request processing according to an embodiment of the present invention. It is the schematic of the eigenvalue index set of a data block. It is a flowchart of the data deduplication process by one Embodiment of this invention.

  Hereinafter, technical solutions in the embodiments of the present invention will be described clearly with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are merely a few, but not all, of the embodiments of the invention. All other embodiments obtained based on the embodiments of the present invention shall fall within the protection scope of the present invention.

  The storage array provided in the embodiment of the present invention such as the storage array shown in FIG. 2 includes an input / output manager A, a controller A, an input / output manager B, a controller B, a switching device A, and a switching device B. And a cache device M. Controller A includes CPU A and memory A, and CPU A communicates with memory A via a bus; controller B includes CPU B and memory B, and CPU B includes memory B via a bus. Communicate with. Input / output manager A is connected to switching device A and switching device B, and input / output manager B is connected to switching device A and switching device B. Switching device A is interconnected to switching device B. Both the switching device A and the switching device B are connected to the cache device M. The cache device M will be described in detail below. Controller A is connected to switching device A and switching device B, and controller B is connected to switching device A and switching device B. Based on the above description, a completely interconnected architecture is formed around the switching device A and the switching device B by the input / output manager A, the input / output manager B, the controller A and the controller B. In the storage array shown in FIG. 2, the switching device A is connected to all hard disks, and the switching device B is also connected to all hard disks. Both controller A and controller B communicate with all hard disks shown in FIG. In particular, controller A communicates with all hard disks via switching device A, and controller B communicates with all hard disks via switching device B. The controller A is configured to virtualize the hard disk to form a logical unit LU A that can be used by the host A. LU A is mounted on the host A, and the host A executes a data access operation to the LU A via the controller A. Here, LU A is homed to controller A, ie, controller A is LU A's home controller. Similarly, the controller B is configured to virtualize a hard disk to form a logical unit LU B usable for the host B. LU B is mounted on the host B, and the host B performs a data access operation on the LU B via the controller B. Here, LU B is stated to be homed to controller B, ie, controller B is LU B's home controller. The host here may be a physical host (or called a physical server) or a virtual host (or called a virtual server). The logical unit LU is generally referred to as a logical unit number (LUN) in the industry. Assigning a LUN to a host actually means assigning an LU identifier to the host, whereby the LU is mounted on the host. Therefore, LU and LUN here mean the same thing. In the storage array shown in FIG. 2, the switching devices A and B are a PCIe switching device, a non-volatile memory express transmission bus (NVMe) switching device, a serial connection small computer system interface (Serial attached SCSI, SAS). It may be a switching device or the like, and is not limited by the embodiment of the present invention. When switching devices A and B are PCIe switching devices, the hard disk connected to the PCIe switching device is a hard disk having a PCIe protocol interface; when switching devices A and B are NVMe switching devices, it connects to the NVMe switching device The hard disk to be played is a hard disk having an NVMe protocol interface; when the switching devices A and B are SAS switching devices, the hard disk connected to the SAS switching device is a hard disk having a SAS protocol interface. The hard disk shown in FIG. 2 may be a mechanical hard disk, a solid state disk (SSD), or a hard disk of another medium. With respect to the hard disks in the storage array shown in FIG. 2, the storage media of the different disks may be different, thereby forming a hybrid hard disk storage array, which is not limited by the embodiments of the present invention.

  The cache device M is a storage device formed by a volatile storage medium or a non-volatile storage medium such as a phase change memory (PCM). It may be a non-volatile storage medium, which is not limited by the embodiments of the present invention. The cache device M is configured to cache data. In the following, the cache device M will be described with reference to a particular embodiment of the invention. In the embodiment of the present invention, the switching device A is a PCIe switching device, the switching device B is a PCIe switching device, and the hard disk is an SSD having a PCIe protocol interface.

  In the storage array shown in FIG. 2, the input / output manager A receives a data write request transmitted by the host. In one implementation, controller A is the home controller of input / output manager A. Therefore, the input / output manager A receives the data operation request transmitted by the host. If the request transmission policy of I / O manager A is not changed, the request is sent to controller A by default according to the data operation request, and therefore controller A is called the home controller of I / O manager A. In one embodiment of the present invention, the input / output manager A receives a data write request sent by the host and sends the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. With respect to the specific PCIe switching device through which the request is forwarded, it may be determined according to a preset rule. When the PCIe switching device is selected, the input / output manager A then communicates with the controller A via the PCIe switching device. Of course, the input / output manager A may randomly select a PCIe switching device to communicate with the controller A, which is not limited by the embodiments of the present invention. The embodiment of the present invention uses an example in which the input / output manager A selects the PCIe switching device A and communicates with the controller A.

  The data write request received by the input / output manager A holds the address of the data to be written. The address of the data to be written includes the identifier of the target LU of the data to be written, the logical block address (Logical Block Address, LBA) of the data to be written, and the length of the data to be written. The input / output manager A transmits a data write request to the controller A. The controller A receives the data write request and determines whether or not the controller A is the home controller of the target LU according to the identifier of the target LU of the data to be written at the address of the data to be written.

  When the controller A is the home controller of the target LU, that is, the target LU is generated by the controller A by virtualizing the hard disk and provided to the host. Controller A determines the cache device used to cache the data to be written. This cache device is the cache device M in this embodiment of the invention. The implementation scheme is as follows: Controller A instructs cache device M to assign a cache address to the data to be written according to the data write request, and cache device M assigns a cache address according to the length of the data to be written. . The controller A obtains a cache address assigned by the cache device M to the data to be written (hereinafter, the cache address assigned by the cache device M to the data to be written is referred to as a cache address M. Cache address includes start address and length). The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The input / output manager A receives the identifier and the cache address M of the cache device M transmitted by the controller A, and writes (or writes) the data to be written to the cache address M according to the identifier and the cache address M of the cache device M. May be directly written to the cache address M). The controller A acquires only the cache address M assigned to the data to be written, and the input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A. This saves CPU computing resources of controller A and memory resources of controller A and improves data writing efficiency compared to the prior art.

  The controller A establishes a correspondence relationship between the address of the data to be written, the identifier of the cache device M, and the cache address M. Therefore, when reading the data to be written, the controller A reads the cache address of the data to be written. M is transmitted to the input / output manager A, and the input / output manager A may read the data to be written from the cache address M of the data to be written (or directly read the data to be written from the cache address M of the data to be written). May save CPU controller resources of controller A and memory resources of controller A and improve data read efficiency.

  If the storage array does not perform data deduplication after the condition is met, the cache device M stores the data to be written to the target SSD of the storage array. The target SSD refers to an SSD for storing data to be written. The specific process of writing the data to be written to the target SSD may be as follows: the controller A sends the identifier of the cache device M and the cache address M to the controller of the target SSD via the PCIe switching device A or the PCIe switching device B. Send. The controller of the target SSD directly reads data to be written from the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address M, and stores the data to be written. The controller of the target SSD transmits the storage address of the data to be written in the target SSD to the controller A via the PCIe switching device A or the PCIe switching device B. The storage address of data to be written in the target SSD includes an identifier of the controller of the target SSD and a logical storage address for storing data to be written to the target SSD. The controller A establishes a correspondence between the address of the data to be written and the storage address of the data to be written to the target SSD.

  The above process is specifically illustrated in FIG.

  Step 301: The host sends a data write request to the input / output manager A.

  The input / output manager A is an input / output reception management device in the storage array, and plays a role of receiving a data operation request transmitted by the host and transferring the data operation request to the controller. In one embodiment of the present invention, the host sends a data write request holding the address of the data to be written to the input / output manager A. Illustratively, a Small Computer System Interface (SCSI) protocol, ie, a SCSI protocol data write request may be used for the data write request. Of course, other protocols may be used and are not limited by the embodiments of the present invention.

  Step 302: Send a data write request to the controller A.

  In this embodiment of the invention, input / output manager A typically communicates with a particular controller. The input / output manager A may establish the correspondence with the controller in a plurality of ways, for example according to the load of the controller or according to a specific path selection algorithm, but this is not limited by the present invention. The input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. In this embodiment of the present invention, it is used as an example that the input / output manager A receives a data write request and sends the data write request to the controller A via the PCIe switching device A.

  Step 303: The controller A acquires a cache address of data to be written.

  Controller A receives the data write request sent by I / O manager A and determines the cache device used to cache the data to be written. This is the cache device M in this embodiment of the invention. In one implementation, the cache device M assigns a segment of the cache address to the controller A. In the cache address segment, the controller A assigns a cache address M to the data to be written according to the length of the data to be written. In another implementation, controller A sends instructions to cache device M via PCIe switching device A or PCIe switching device B. The instruction holds the length of the data to be written and instructs the cache device M to allocate a cache address for the data to be written. The controller A acquires the cache address M.

  Step 304: Send the identifier of the cache device M and the cache address M.

  The controller A acquires the cache address M, and transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The identifier of the cache device M is a device address.

  Step 305: The host sends the data to be written to the input / output manager A.

  The input / output manager A receives the identifier of the cache device M and the cache address M transmitted by the controller A, and receives the written data transmitted by the host.

  Step 306: Write the data to be written to the cache address M.

  The input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M. The input / output manager A receives a response sent by the cache device M via the PCIe switching device A indicating that the data to be written has been successfully written. The input / output manager A sends a response indicating that the data write request has been completed to the host, and notifies the host that the write request operation has been completed.

  Step 307: Notify the controller A that the data to be written is written to the cache address M.

  The input / output manager A succeeds in writing the data to be written to the cache address M, and notifies the controller A that the data to be written is written to the cache address M.

  Step 308: The controller A establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M.

  The controller A receives the notification transmitted by the input / output manager A, and establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M.

  The cache device M assigns a cache address M to the data to be written, thereby establishing a correspondence between the address of the data to be written and the cache address M. The cache device M may obtain the address of the data to be written from the cache address assignment instruction sent by the controller A. After assigning the cache address M, the cache device M A correspondence relationship with the address M is established. In another implementation, the cache device M is an exclusive cache device of the target LU and is used only to cache the data of the target LU, so the cache device M by default is the target LU and the target LU. The correspondence relationship between the LBA and the cache address is stored. By default, the cache device M stores a correspondence relationship between the target LU, the LBA in the target LU, and the cache address segment of the cache device M. In this segment of the cache address, the cache device M assigns the cache address M to the data to be written.

  In order to improve the reliability of the storage array and to cache multiple copies of the data to be written, in the prior art shown in FIG. 1, the input / output manager A sends the data to be written, and CPU A The data to be written is written in the memory A, the CPU A reads the data to be written from the memory A, and transmits the data to be written to the PCIe switch B via the PCIe switch A. The PCIe switch B transmits data to be written to the CPU B, and the CPU B writes the data to be written to the memory B. In this embodiment of the invention, to prevent loss of written data in the cache device M, the storage array caches written data in multiple cache devices. Therefore, it is used as an example that the data to be written is cached in two cache devices. The storage array shown in FIG. 2 further includes a cache device N. The PCIe switching device A and the PCIe switching device B are both connected to the cache device N. Therefore, the controller A receives the data write request transmitted by the input / output manager A, determines that the cache device M serves as a primary cache device that caches data to be written, and the data to which the cache device N is written. It is determined that it plays a role as a secondary cache device that caches. The controller A acquires a cache address assigned to the data to be written and located in the cache device M and the cache device N. In one implementation, the controller A sends an instruction to each of the cache device M and the cache device N. The instruction is used to instruct both the cache device M and the cache device N to assign a cache address to the data to be written. The instruction holds the length of the data to be written. A cache address assigned to data to be written by the cache device M is called a cache address M, and a cache address assigned to data to be written by the cache device N is called a cache address N. The controller A acquires the cache address M and the cache address N. The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A, and inputs / outputs the identifier of the cache device N and the cache address N via the PCIe switching device A. Send to Manager A. In a particular embodiment, the controller A sends the identifier and cache address M of the cache device M and the identifier and cache address N of the cache device N via one message or via two messages respectively. A can be sent to A, which is not limited here. In another implementation, cache device M allocates an exclusive segment of the cache address to controller A. This exclusive segment is used only to cache the data of the LU of the home controller A. In this segment of the cache address of the cache device M, the controller A directly assigns the cache address M to the data to be written. The cache device N assigns an exclusive segment of the cache address to the controller A, and in this segment of the cache address of the cache device N, the controller A directly assigns the cache address N to the data to be written.

  The input / output manager A receives the identifier and cache address M of the cache device M, and the identifier and cache address N of the cache device N. The input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A according to the identifier and cache address M of the cache device M. The input / output manager A reads the identifier and cache address of the cache device N. According to N, the data to be written is directly written to the cache address N via the PCIe switching device A. The input / output manager A receives a response indicating that the data to be written has been successfully written to the cache address M via the PCIe switching device A, and sends the address of the data to be written and the cache device M to the controller A. Is instructed to establish a correspondence between the identifier and the cache address M. Similarly, the controller A establishes a correspondence relationship between the address of data to be written, the identifier of the cache device N, and the cache address N.

  In another implementation, the controller A sends the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The input / output manager A receives the identifier of the cache device M and the cache address M. The input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address M. The controller A transmits a data write command to the cache device M via the PCIe switching device A or the PCIe switching device B. The data write instruction holds the identifier of the cache device N and the cache address N. The cache device M caches data to be written, and the cache device M directly writes the data to be written to the cache address N via the PCIe switching device A or the PCIe switching device B according to the data write command.

  The controller A only needs to obtain the cache address M and the cache address N assigned to the data to be written so that the input / output manager A performs the writing of the data to be written to the cache device M and the cache device N. Thereby, the CPU calculation resource of the controller A and the memory resource of the controller A are saved, and the data writing efficiency is improved.

  In another case, the I / O manager A receives a host data write request. The data write request holds the address of data to be written. The input / output manager A transmits a data write request to the controller A by transferring it by the PCIe switching device A. The controller A receives the data write request transmitted by the input / output manager A, and determines that the controller A is not the home controller of the target LU according to the identifier of the target LU held in the data write request. A particular embodiment is shown in FIG.

  Step 401: The host sends a data write request to the input / output manager A.

  The host sends a data write request to the input / output manager A. The data write request holds the address of data to be written.

  Step 402: A data write request is transmitted to the controller A.

  In this embodiment of the invention, controller A is the home controller of input / output manager A. The input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. In this embodiment of the present invention, it is used as an example that the input / output manager A receives a data write request and sends the data write request to the controller A via the PCIe switching device A.

  Step 403: Determine that the controller A is not the home controller of the target LU.

  The controller A receives the data write request transmitted by the input / output manager A, and determines that the controller A is not the home controller of the target LU according to the target LU identifier of the data to be written held in the data write request. The controller A inquires about the correspondence between the controller and the LU, and determines that the controller B is the home controller of the target LU.

  Step 404: Send a data write request to the controller B.

  The controller A transmits a data write request to the controller B via the PCIe switching device A or the PCIe switching device B. In this embodiment, it is used as an example that the PCIe switching device B transfers a data write request to the controller B.

  Step 405: Obtain a cache address of data to be written.

  Controller B receives the data write request sent by controller A and determines the cache device used to cache the data to be written. In this embodiment of the invention, this is a cache device M. For the specific implementation method, refer to the method in which the controller A obtains the cache address of the data written from the cache device M.

  Step 406: Send the identifier of the cache device M and the cache address M to the controller A.

  The controller B acquires the cache address M, and transmits the identifier of the cache device M and the cache address M to the controller A via the PCIe switching device B. In another implementation, the identifier of the cache device M and the cache address M may also be sent directly to the controller A via the PCIe switching device A or the PCIe switching device B.

  Step 407: The identifier of the cache device M and the cache address M are transmitted to the input / output manager A.

  The controller A receives the identifier and the cache address M of the cache device M transmitted by the controller B, and transmits the cache address M of the data to be written via the PCIe switching device.

  Step 408: The host sends the data to be written to the input / output manager A.

  The input / output manager A receives the identifier of the cache device M and the cache address M, and responds to the data write request sent by the host. The host transmits data to be written to the input / output manager A.

  Step 409: Write the data to be written to the cache address M.

  The input / output manager A receives the data to be written transmitted by the host, and writes the data to be written directly to the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M. The input / output manager A receives a response sent by the cache device M via the PCIe switching device A indicating that the data to be written has been successfully written. The input / output manager A sends a response indicating that the data write request has been completed to the host, and notifies the host that the write request operation has been completed.

  Step 410: Notify the controller B that the data to be written is written to the cache address M.

  The input / output manager A succeeds in writing the data to be written to the cache address M, and notifies the controller B that the data to be written is written to the cache address M. This is particularly true when the I / O manager A forwards the notification to the controller A via the PCIe switching device A and the controller A forwards the notification to the controller B via the PCIe switching device B; or The input / output manager A includes sending the notification directly to the controller B via the PCIe switching device A or the PCIe switching device B.

  Step 411: The controller B establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M.

  The controller B establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M in accordance with the notification transmitted by the input / output manager A.

  For how the cache device M establishes the correspondence between the address of the data to be written and the cache address M, refer to the description in the above embodiment, and the details will not be repeated here. .

  The cache device N assigns a cache address N to the data to be written, thereby establishing a correspondence between the address of the data to be written and the cache address N. The cache device N may obtain the address of the data to be written from the cache address assignment instruction sent by the controller A. After assigning the cache address N, the cache device N A correspondence relationship with the address N is established.

  In order to prevent loss of written data cached in the cache device M, in a scenario where the controller A is not the home controller of the target LU of the data to be written, the written data requires multiple cache devices that act as a cache. When doing so, the input / output manager A sends a data write request to the controller B. For the process, refer to the description in the above embodiment. For the process of acquiring the cache address of the data to be written by the controller B, refer to the scenario in which the controller A is the home controller of the target LU of the data to be written and the controller A acquires the cache addresses of a plurality of cache devices. . For other steps as well, the description in the above embodiment is referred to, and details are not repeatedly described here.

  After the host writes data to the storage array, the host accesses the written data, that is, sends a data read request. A specific process is shown in FIG.

  Step 501: A data read request is transmitted.

  The host transmits a data read request to the input / output manager A. The data read request holds the address of data to be read. The address of the read data includes the identifier of the logical unit LU where the read data is located, the LBA of the read data, and the length of the read data. In particular, the host may send a data read request to the input / output manager A by using the SCSI protocol, but this is not limited by the present invention. For ease of explanation, the data read here is the written data described above.

  Step 502: Send a data read request to the controller A.

  The input / output manager A receives the data read request transmitted by the host, and transmits the data read request to the controller A via the PCIe switching device A.

  Step 503: The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A.

  When the controller A is the home controller of the LU where the data to be read is located and the read data is cached in a cache device such as the cache device M, the address of the data to be read and the identifier of the cache device according to the data read request The cache address M is used to cache the read data in the cache device M, and the correspondence relationship between the cache address and the cache address is determined. When the read data is still cached in the cache device M, the cache address of the read data in the cache device M is the cache address M. The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A.

  Step 504: Read data read from the cache address M.

  The input / output manager A directly reads data read from the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M.

  Step 505: Return the data to be read.

  The input / output manager A reads the data read from the cache address M and returns the read data to the host.

  When the input / output manager A sends a query request for data to be read to the controller A via the PCIe switching device A according to the data read request, and the controller A is not the home controller of the LU where the data to be read is located, the controller A inquires the correspondence between the LU where the data to be read is located and the home controller, and controller B determines that it is the home controller of the LU where the data to be read is located. The controller A transmits a query request for data to be read to the controller B via the PCIe switching device B. It is used as an example that the written data is still the read data referred to here. Therefore, the address of the data to be read is the address of the data to be written described above. When the read data is still cached in the cache device M, the cache address of the read data in the cache device M is the cache address M. The controller B inquires the correspondence between the address of the data to be written, the identifier of the cache device M, and the cache address M, determines the identifier and the cache address M of the cache device M that caches the read data, and The identifier of the device M and the cache address M are transmitted to the controller A via the PCIe switching device B. The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The controller B may also transmit the identifier of the cache device M and the cache address M directly to the input / output manager A via the PCIe switching device A or the PCIe switching device B. Regarding the subsequent read operation, the read operation in the above-described embodiment is referred to, and details thereof will not be repeated here.

  It is used as an example that the written data is still the read data referred to here. Therefore, the address of the data to be read is the address of the data to be written described above. When the data to be read is already stored in the target SSD, the home controller of the LU where the data to be read is located has the address of the data to be read (the address of the data to be written) and the storage address of the data to be read in the target SSD. The storage address of the data to be read in the target SSD is obtained, and the storage address of the data to be read in the target SSD is transmitted to the input / output manager A via the PCIe switching device A or the PCIe switching device B. To do. The storage address of the data to be read in the target SSD includes the controller identifier of the target SSD and the logical storage address of the data to be read in the target SSD. The input / output manager A reads the data read from the logical storage address of the data read in the target SSD directly via the PCIe switching device A or the PCIe switching device B according to the storage address of the data read in the target SSD.

  In the above embodiment, when the read data is partially stored in the target SSD and partially cached in the cache device M in this embodiment of the present invention as described above, the input / output manager A Read data directly from the cache address via the PCIe switching device A or PCIe switching device B according to the cache address of the data to be read in the cache device; the I / O manager A is read in the controller identifier of the target SSD and in the target SSD Data is directly read from the logical storage address in the target SSD via the PCIe switching device A or the PCIe switching device B according to the logical storage address of the data. This is not described in detail here.

  When a plurality of cache devices perform an operation of caching read data, a primary cache in which the LU home controller where the read data is located normally caches the read data and the cache address M in the input / output manager A Returns the identifier of device M. For other procedural operations, refer to the read operation in the above embodiment, and the details will not be repeated here.

  Data deduplication is performed in the storage array. This can save storage space and reduce storage costs. In the storage array shown in FIG. 2 according to the embodiment of the present invention, the host sends a data write request to the input / output manager A, and the data write request holds the address of the data to be written. The input / output manager A transmits a data write request to the controller A via the PCIe switching device A. When the controller A is the home controller of the target LU of the data to be written, the controller A provides the input / output manager A with the identifier of the cache device M and the cache address M. The input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address M.

  Data deduplication is performed before the data to be cached in the cache device M is stored in the SSD of the storage array. This can effectively save storage space and improve the utilization rate of storage space. Using the storage array shown in FIG. 2 as an example, for data stored in the storage array SSD, data deduplication is performed before the data is stored in the SSD by the cache device M. The data deduplication technique is to divide data into data blocks according to preset rules and calculate eigenvalues of each data block. The eigenvalues of the data block are usually calculated by using a hash algorithm. A hash operation is performed on the data block to obtain a hash value, and this hash value is used as an eigenvalue. Common hash algorithms include MD5, SHA1, SHA-256, SHA-512, and the like. For example, when the eigenvalue of the data block A is the same as the eigenvalue of the data block B already stored in the SSD, the data block A and the data block B are the same. Therefore, the duplicate data block A is deleted from the cache device M, and the logical storage address for storing the data block B in the SSD is used as the logical storage address of the data block A in the SSD.

  In a particular implementation, a comparison of the eigenvalues of the data block is performed by the controller. Data deduplication is performed in the storage array, and many unique values are generated because each unique data block has a unique value. In order to implement a balance between the controllers in the storage array, each controller is responsible for comparing the eigenvalues of several data blocks according to a data block eigenvalue distribution algorithm such as a hash distribution algorithm. In this way, each controller maintains only the eigenvalue index of some unique data stored in the storage array according to the data block eigenvalue distribution algorithm. The unique value index of some unique data is called the unique value index set. The controller queries the eigenvalue index set for the eigenvalue of the data block to be written to the SSD and determines whether the eigenvalue is the same as the eigenvalue in the eigenvalue index set. For example, controller A needs to maintain eigenvalue index set A according to the eigenvalue distribution algorithm, and therefore controller A is the home controller for all eigenvalues in eigenvalue index set A; or eigenvalues from eigenvalue index set A The controllers for which are the same as the eigenvalues of data block X are both the eigenvalue home controller of data block X and the home controllers of all eigenvalues in eigenvalue index set A.

  In particular, the eigenvalue index set is formed by the eigenvalue index shown in FIG. For example, the index of the unique value 1 includes the unique value 1, the data block storage address 1, and the reference count. Data block storage address 1 is used to represent a storage address of a unique data block C in SSD A or a storage address of data block C in the cache device. The storage address of the data block C in the SSD A may include the identifier of the controller of the SSD A and the logical storage address of the data block C stored in the SSD A. The storage address of the data block C in the cache device includes a cache device identifier and a cache address. The eigenvalue 1 represents the eigenvalue of the data block C. The reference count represents the amount of data blocks having an eigenvalue of 1. For example, when data block A is stored in the storage array for the first time, the reference count is 1 if the amount of data blocks having unique value 1 is 1. When a data block D having the same eigenvalue 1 is stored again in the SSD, the data block D is not stored in the SSD according to the principle of data deduplication, but the reference count is incremented by 1 and updated to 2. In summary, the data block storage address in the eigenvalue index is the storage address of the data block in the cache device or the storage address of the data block in the target hard disk. The storage address of the data block in the cache device includes the identifier of the cache device and the cache address of the data block in the cache device; the storage address of the data block in the target hard disk includes the identifier of the controller of the target hard disk and the target hard disk And a logical storage address for storing the data block. The eigenvalue index shown in FIG. 6 is merely an exemplary implementation, and the eigenvalue index may be a multi-level index. The index may be any form of index that can be used for data deduplication, which is not limited by this embodiment of the invention.

  In the storage array shown in FIG. 2, it is used as an example that the controller A serves as the home controller of the target LU of the data block cached in the cache device M. Referring to the above embodiment, after receiving the data write request, the input / output manager A acquires the identifier of the cache device M and the cache address M from the controller A. The input / output manager A directly writes the data to be written to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address M. The controller A establishes a correspondence relationship between the address of data to be written, the identifier of the cache device M, and the cache address M. When the data cached in the LU of the home controller A is written from the cache device M to the SSD, the data at the cache address M is used as an example. Normally, when data deduplication is being performed, the eigenvalues of the data blocks need to be calculated. In order to calculate the eigenvalues of a data block, the data must first be partitioned according to specific rules in order to obtain the data block. There may be two methods for dividing into data blocks: dividing data into fixed-length data blocks or dividing data into variable-length data blocks. In this embodiment of the present invention, it is used as an example that data is divided into fixed-length data blocks. For example, the data is divided into data blocks having a size of 4 KB. Illustratively, the data to be written, which is written to the cache address M, is divided into several data blocks having a size of 4 KB. The controller A records the LU identifier of each data block, the LBA of the data block, and the length of the data block. The LU of the data block, the LBA of the data block, and the length of the data block are hereinafter referred to as the data block storage address. Using data block X in several data blocks of 4 KB size as an example (where data block X is called a data block to be deduplicated) and is shortened Controller A also sends a data block eigenvalue request to cache device M via PCIe switching device A or PCIe switching device B, also known as to-be-dedicated data block). . The eigenvalue request includes the address of the data block X. The cache device M transmits the unique value of the data block X to the controller A via the PCIe switching device A or the PCIe switching device B in order to perform data deduplication. As shown in FIG. 7, the specific process includes:

  Step 701: The cache device M calculates a unique value of the data block X.

  The controller A transmits to the cache device M an instruction for acquiring a unique value of the data block X. The instruction holds the address of data block X. The cache device M receives the instruction to acquire the unique value of the data block X transmitted by the controller A. In this case, the cache device M stores the correspondence between the address of the data block X and the cache address B, and the data according to the address of the data block X held in the instruction for obtaining the unique value of the data block X The block X is determined, the unique value of the data block X is calculated, and the unique value of the data block X is cached at the cache address X.

  Step 702: The eigenvalue of the data block X is transmitted to the controller A.

  The cache device M acquires the unique value of the data block X and transmits a response message of the unique value of the data block X to the home controller A of the LU where the data block X is located. The response message of the unique value of the data block X holds the unique value of the data block X. Further, the response message of the unique value of the data block X further holds the identifier of the cache device M that caches the unique value of the data block X and the cache address X of the unique value of the data block X in the cache device M.

  Step 703: The home controller of the eigenvalue of the data block X is determined according to the eigenvalue distribution algorithm.

  Step 704: Controller A queries local eigenvalue index set A.

  When the controller A is the home controller of the eigenvalue of the data block X, the controller A inquires the local eigenvalue index set A and determines whether or not the eigenvalue same as the eigenvalue of the data block X exists in the eigenvalue index set A. .

  When the same eigenvalue as the eigenvalue of the data block X exists in the eigenvalue index set A, steps 705a and 706a are executed. As shown in FIG. 6, the eigenvalue of the data block X is the same as the eigenvalue 1. That is, the data block X is the same as the data block A.

  Step 705a: Controller A updates the reference count in the index of eigenvalue 1.

  The reference count in the index of the unique value 1 is 1, that is, only the data block A exists in the storage array. It can be seen that the eigenvalue of the data block X is the same as the eigenvalue 1, so the reference count is updated to 2.

  Step 706a: The controller A instructs the cache device M to delete the data block X.

  The controller A instructs the cache device M to delete the data block X. The controller A establishes a correspondence between the address of the data block X and the unique value of the data block X, or the controller A sets the address of the data block X, the unique value of the data block X, and the data block A. Establish a correspondence with the storage address.

  In step 704, it is determined that the data block X is a duplicate data block. Therefore, the data block X does not need to be stored in the SSD, and the cache device M is instructed to delete the data block X.

  When the same eigenvalue as the eigenvalue of the data block X does not exist in the eigenvalue index set A, steps 705b, 706b, 707, 708, 709 and 710 are executed.

  Step 705b: The cache address B of the data block X cached in the cache device M is acquired.

  The controller A acquires the cache address B of the data block X from the cache device M via the PCIe switching device A according to the cache address X of the unique value of the data block X in the cache device M.

  Step 706b: The identifier of the cache device M and the cache address B are transmitted to the controller of the target SSD.

  The controller A acquires the identifier of the cache device M and the cache address B, and transmits the identifier of the cache device M and the cache address B to the controller of the target SSD via the PCIe switching device A or the PCIe switching device B.

  Step 707: The controller of the target SSD reads the data block X from the cache address B.

  The controller of the target SSD receives the identifier of the cache device M and the cache address B, and the data block X from the cache address B via the PCIe switching device A or the PCIe switching device B according to the identifier and the cache address B of the cache device M. Is read directly.

  Step 708: The controller of the target SSD sends the storage address of the data block X in the target SSD to the controller A.

  The controller of the target SSD reads the data block X from the cache address B and stores the data block X in the target SSD. The controller of the target SSD transmits the storage address of the data block X in the target SSD to the controller A via the PCIe switching device A. The storage address of the data block X in the target SSD includes a controller identifier of the target SSD and a logical storage address for storing the data block X in the target SSD.

  Step 709: The controller A establishes an eigenvalue index for the data block X.

  The controller A receives the storage address of the data block X in the target SSD, establishes the eigenvalue index of the data block X, and sets the reference count to 1. The controller A establishes a correspondence relationship between the address of the data block X, the unique value of the data block X, and the storage address of the data block X in the target SSD. The controller A also needs to record the cache address X of the unique value of the data block X. When the unique value of the data block X is stored in the SSD, the controller A needs to record the storage address of the unique value of the data block X in the target SSD.

  In another case, controller A is not the home controller of the eigenvalue of data block X, but is simply the home controller of the LU where data block X is located. In this embodiment of the present invention, it is used as an example that the controller B is the home controller of the eigenvalue of the data block X, and the controller A sends the eigenvalue of the data block X via the PCIe switching device A or the PCIe switching device B. Transmit to controller B. The controller B receives the eigenvalue of the data block X transmitted by the controller A and inquires about the eigenvalue index set B of the controller B. When controller B finds that the same eigenvalue as the eigenvalue of data block X exists in eigenvalue index set A, for example, the eigenvalue of data block R is the same as the eigenvalue of data block X, controller B Instructs device M to delete data block X. This includes in particular that controller B sends a delete instruction to controller A via PCIe switching device B. The controller A transmits a delete instruction to the cache device M via the PCIe switching device A, and the cache device M deletes the data block X. The controller B updates the reference count of the index having the same eigenvalue as the eigenvalue of the data block X, that is, increases the reference count by one. When the data block R is already stored in the SSD, the storage address of the data block R in the index of the data block R is the identifier of the controller of the SSD that stores the data block R, and the data block R for storing the data block R in the SSD Contains the logical storage address. When the data block R is in the cache device, the storage address of the data block R in the index of the data block R includes the identifier of the cache device and the cache address. The controller A establishes a correspondence relationship between the address of the data block X, the unique value of the data block X, and the address of the home controller B of the unique value of the data block X. Therefore, the correspondence between the unique value of the data block and the storage address of the data block is not required, and the amount of data stored by the controller A is efficiently reduced. Alternatively, the controller A establishes a correspondence relationship between the address of the data block X, the unique value of the data block X, and the storage address of the data block R. Thereafter, when reading the data block X, the controller A inquires about the correspondence relationship between the address of the data block X, the unique value of the data block X, and the storage address of the data block R, thereby determining the storage address of the data block R. The input / output manager A directly reads the data block X from the storage address of the data block R via the PCIe switching device A or the PCIe switching device B, thereby improving the data read efficiency.

  When the controller A is simply the home controller of the LU where the data block X is located, but is not the home controller of the eigenvalue of the data block X, the controller B has the same eigenvalue as the eigenvalue of the data block X in the eigenvalue index set B. The controller B obtains the cache address B of the data block X in the cache device M by sending a request to the controller A via the PCIe switching device B. The controller A sends a request to the cache device M via the PCIe switching device A. The cache device M transmits the identifier of the cache device M and the cache address B to the controller B. The controller B sends the identifier of the cache device M and the cache address B to the controller of the target SSD via the PCIe switching device A or the PCIe switching device B (here, the PCIe switching device A is used as an example). The controller of the target SSD directly reads the data block X from the cache address B via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address B, and stores the data block X in the target SSD. . The controller of the target SSD transmits the storage address of the data block X in the target SSD to the controller B via the PCIe switching device A or the PCIe switching device B. The controller B receives the storage address of the data block X in the target SSD, establishes the eigenvalue index of the data block X, and sets the reference count in the index to 1. The controller B also needs to record the cache address X of the unique value of the data block X. When the unique value of the data block X is stored in the SSD, the controller B needs to record the storage address of the unique value of the data block X in the SSD.

  The controller B receives the storage address of the data block X in the target SSD and sends a notification to the controller A. The notification holds the storage address of the data block X in the target SSD. In accordance with the notification sent by the controller B, the controller A establishes a correspondence relationship between the address of the data block X, the unique value, and the storage address of the data block X in the target SSD. In another implementation, when the controller A is simply the home controller of the LU where the data block X is located, but not the eigenvalue home controller of the data block X, the controller A will send the address of the data block X and the data A correspondence between the unique value of block X and the address of controller B is established.

  In accordance with the storage array in this embodiment of the invention, the cache device performs a fingerprint calculation of data block X. This saves controller computing resources. During the process of storing the data block X in the target SSD, the controller provides only the identifier of the cache device M and the cache address B, and the target SSD controller reads the data block X directly from the cache address B. This saves controller computing and memory resources and improves storage array performance.

  Based on the storage array shown in FIG. 2, data is written to the SSD according to the data deduplication operation described above. When the input / output manager A receives a data read request for holding the address of the data block X, for example, a request for reading the data block X, the input / output manager A sends a data read request to the controller A via the PCIe switching device A. Send. Controller A determines that controller A is the home controller of the LU where data block X is located. In one implementation, the controller A searches for the correspondence between the address of the data block X, the unique value of the data block X to be read, and the storage address of the data block X in the target SSD, and the data block in the target SSD. The storage address of X is determined. The controller A transmits the storage address of the data block X in the target SSD to the input / output manager A via the PCIe switching device A. The input / output manager A sends the data block X from the logical storage address of the data block X in the target SSD via the PCIe switching device A or PCIe switching device B according to the storage address of the data block to be read in the target SSD, that is, the storage address of the data block X. Is read directly. In another implementation, the controller A retrieves the correspondence between the address of the data block X, the unique value of the data block X, and the home controller address of the unique value of the data block X, and the unique value of the data block X Determine the home address of the data block X in the controller B and determine the storage address of the data block X in the target SSD; or determine the home controller B of the unique value in the data block X; Queries the eigenvalue index of the data block having the same eigenvalue as that of the data block X in the controller B, determines the storage address of the data block having the same eigenvalue as the data block X, and then determines the eigenvalue of the data block X Flip reading data from the memory address of the data block having a unique value. When the controller A is both the home controller of the LU in which the data block X is located and the home controller of the eigenvalue of the data block X, in another implementation, the controller A has the address of the data block X to be read and the data Retrieve the correspondence between the eigenvalues of block X, query the eigenvalue index set A maintained by controller A according to the eigenvalues of data block X, determine the storage address of data block X to be read, The storage address of the data block X to be read is transmitted to the input / output manager A. The input / output manager A reads the data block from the storage address of the data block X via the PCIe switching device A or the PCIe switching device B.

  When data to be written to the storage array shown in FIG. 2 is written to multiple cache devices, data deduplication is only performed on data in one of the cache devices when a data deduplication operation is being performed. Executed. In particular, data deduplication can be performed on the data at the primary cache device or one of the cache devices to perform data deduplication operations according to the load of the plurality of cache devices that cache the data. Is selected, but is not limited by this embodiment of the invention.

  In this embodiment of the invention, in another implementation, the concept of homing does not necessarily exist between the I / O manager and the controller. That is, the controller A is not the home controller of the input / output manager A. Each input / output manager stores a correspondence between the LU and the controller on which the LU is homed. The I / O manager inquires the correspondence between the target LU identifier and the home controller in accordance with the target LU identifier held in the data operation request, determines the home controller of the target LU, and the PCIe switching device A or PCIe. The request is directly transmitted to the home controller of the target LU via the switching device B. Furthermore, via any PCIe switching device, between controllers, or between controller and SSD, or between I / O manager and controller, or between I / O manager and SSD, or cache device. Communication may occur between the controller or between the cache device and the SSD. In this embodiment of the present invention, the logical storage address for storing the data block X at the storage address in the target hard disk refers to the logical block address for storing the data block X in the target hard disk, and in particular, the implementation of the present invention. In the form, it indicates a logical block address for storing the data block X in the target SSD.

  In this embodiment of the invention, FIG. 2 shows only two controllers, two switching devices, two input / output managers and one cache device. However, in certain embodiments, the amount of controllers, switching devices, I / O managers and cache devices may be set as needed and flexibly expanded. Any input / output manager is connected to any controller via any switching device, or any input / output manager is connected to any hard disk via any switching device, or any input / output A manager is connected to any cache device via any switching device. Any controller is connected to any controller via any switching device, or any controller is connected to any hard disk via any switching device, or any controller is any switching device To any cache device. An arbitrary cache device is connected to an arbitrary hard disk via a switching device. Bidirectional communication is performed between any two devices connected via any switching device. Any two switching devices are directly connected. In the storage array architecture provided in this embodiment of the invention, logically, the controller is collectively referred to as the controller plane, the switching device is collectively referred to as the switching plane, and the hard disk is collectively referred to as the storage plane, The input / output manager is collectively called an input / output management plane, and the cache device is also called a cache plane. In the architecture provided in this embodiment of the invention, data read and write control is separated from data read and write. The controller performs data read and write control, but data read and write (or in other words read and write data) do not pass through the controller. This saves the controller's CPU computational resources and the controller's memory resources, improves the data write efficiency, and improves the data processing efficiency of the storage array. The storage array architecture in this embodiment of the invention can implement expansion of devices such as controllers and hard disks, and controllers, switching devices, hard disks, etc. may be flexibly added according to the performance requirements of the storage array.

  Of course, the technical solution in this embodiment of the invention is also applicable to scenarios where the storage array includes one I / O manager, one controller, one switching device, one cache device and several hard disks. It is. For the method of writing data to the storage array in this scenario, refer to the description in the above embodiment. For scenarios where data deduplication is performed in the storage array, see the description in the above embodiment. For the data read operation executed in the storage array, refer to the description in the above embodiment. Of course, the storage array may include two controllers and one switching device, which are connected to the switching device. For the data write operation, the data deduplication operation, and the data read operation in such a scenario, refer to the description in the above embodiment, and the details will not be repeated here.

  In this embodiment of the invention, device A reads data from cache address A (or in other words, reads data directly from cache address A), and according to device B's identifier and cache address A, PCIe switching device A or Data is written to the cache address A via the PCIe switching device B (or in other words, data is directly written to the cache address A). Such an implementation scheme may be implemented by direct memory access (Direct Memory Access, DMA) technology, where device A and device B represent devices that perform DMA access specifically in this embodiment of the invention.

  The controller acquires the cache address of device B, and transmits the identifier of device B and the cache address of device B to device C via PCIe switching device A or PCIe switching device B. The controller communicates with device B to obtain the cache address via PCIe switching device A or PCIe switching device B and has already learned the identifier of device B, so the cache address is obtained and the identifier of device B And the cache address of device B may be transmitted to device C. Of course, the controller may also obtain the identifier and cache address of device B. The identifier of device B may be the address of device B or another identifier that uniquely identifies the device.

  Those skilled in the art will appreciate that the exemplary units and algorithm steps described with reference to the embodiments disclosed herein may be implemented by electronic hardware or by a combination of computer software and electronic hardware. Can be recognized. Whether the function is performed by hardware or software depends on the specific application and design constraints of the technical solution. One skilled in the art can use different methods to perform the functions described for each particular application, but the implementation should not be considered beyond the scope of the present invention.

  For convenience and brief description, the detailed operational processes of the above systems, devices and units will be referred to the corresponding processes in the above method embodiments, and details will not be repeated here. Can be clearly understood by those skilled in the art.

  It should be understood that in some embodiments provided in this application, the disclosed systems and methods may be implemented in other manners. For example, the described apparatus embodiment is merely exemplary. For example, the unit division is merely logical function division and may be other division in an actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. Furthermore, the mutual or direct coupling or communication connection that is displayed or considered may be implemented through several interfaces. Indirect coupling or communication connections between devices or units may be implemented electronically, mechanically, or otherwise.

  A unit described as a separate part may or may not be physically separate, and a part displayed as a unit may or may not be a physical unit. It may be located at a location or distributed over a plurality of network units. Some or all of the units may be selected according to the actual need to achieve the objectives of the solutions of the embodiments.

  Furthermore, the functional units in the embodiments of the present invention may be integrated into one processing unit, or each of the units may physically exist alone, or two or more units may be combined into one unit. Integrated.

  When functions are implemented in the form of software functional units and are sold or used as independent products, the functions may be stored on a computer-readable non-volatile storage medium. Based on such an understanding, the technical solution of the present invention may be implemented in the form of a software product, or a part that contributes to the prior art, or some of the technical solutions may be implemented. Good. The software product is stored in a non-volatile storage medium and the computer device (which may be a personal computer, server, or network device) performs all or some of the method steps described in the embodiments of the present invention. It includes a plurality of instructions for instructing to execute. The non-volatile storage medium includes any medium capable of storing a program code, such as a USB flash drive, a removable hard disk, a read-only memory (Read-Only Memory, ROM), a magnetic disk, or an optical disk.

Claims (12)

A data write request processing method, wherein the method is applied to a storage array, and the storage array includes an input / output manager, a switching device, a first controller, and a first cache device. The manager, the first controller, and the first cache device are connected to the switching device, the switching device is connected to a storage unit in the storage array, and the method includes:
Transmitting a data write request by the input / output manager to the first controller via the switching device, the data write request corresponding to data to be written;
Obtaining a first cache address assigned to the written data in the first cache device by the first controller in accordance with the data write request;
Sending an identifier of the first cache device and the first cache address by the first controller to the input / output manager via the switching device;
Writing the written data to the first cache address via the switching device by the I / O manager according to the identifier of the first cache device and the first cache address;
Including a data write request processing method. The data write request includes an address of the data to be written, and the method includes:
Receiving a response sent by the first cache device indicating successful writing of the written data by the I / O manager;
Sending a notification that the written data is written to the first cache address from the input / output manager to the first controller via the switching device;
Establishing a correspondence between the address of the data to be written, the identifier of the first cache device, and the first cache address by the first controller in accordance with the notification;
The method of claim 1, further comprising: The storage array further comprises a second cache device, the second cache device is connected to the switching device, and the method comprises:
Obtaining a second cache address assigned to the written data in the second cache device by the first controller in accordance with the data write request;
Transmitting, by the first controller, an identifier of the second cache device and the second cache address to the input / output manager via the switching device;
Writing the written data to the second cache address via the switching device by the I / O manager according to the identifier of the second cache device and the second cache address;
The method of claim 1, further comprising: The storage array further comprises a second cache device, the second cache device is connected to the switching device, and the method comprises:
Obtaining a second cache address assigned to the written data in the second cache device by the first controller in accordance with the data write request;
Sending a data write command to the first cache device via the switching device by the first controller, wherein the data write command includes the identifier of the second cache device and the second Holding the cache address of, and
Writing the written data to the second cache address via the switching device by the first cache device according to the data write instruction;
The method of claim 1, further comprising: The data write request holds an address of the written data, and the address of the written data includes an identifier of a target logical unit (target LU) where the written data is located, and a logical block of the written data Including an address and a length of the written data, the method comprising:
The input / output manager inquires about a homing relationship between the target LU stored in the input / output manager and the first controller according to the identifier of the target LU, and the first controller Identifying the home controller as
Sending the data write request by the I / O manager to the first controller via the switching device;
The method of claim 1, further comprising: The data write request holds an address of the written data, and the address of the written data includes an identifier of a target logical unit (target LU) where the written data is located, and a logical block of the written data An address and a length of the data to be written, wherein the storage array further comprises a second controller, the second controller is connected to the switching device, and the method comprises:
Sending the data write request by the input / output manager to the second controller via the switching device;
Determining by the second controller according to the identifier of the target LU that the first controller is a home controller of the target LU;
Sending the data write request by the second controller to the first controller via the switching device;
The method of claim 1, further comprising: A storage array, comprising: an input / output manager, a switching device, a first controller, and a first cache device, wherein the input / output manager, the first controller, and the first controller A cache device is connected to the switching device, the switching device is connected to a storage unit in the storage array;
The input / output manager is configured to send a data write request to the first controller via the switching device;
The first controller obtains a first cache address assigned to data to be written in the first cache device according to the data write request, and an identifier of the first cache device and the first cache An address is configured to be sent to the I / O manager via the switching device;
The input / output manager is further configured to write the written data to the first cache address via the switching device according to the identifier of the first cache device and the first cache address. Storage array. The data write request holds an address of the data to be written,
The input / output manager is further configured to receive a response from the first cache device indicating successful writing of the written data;
The input / output manager is further configured to notify the first controller via the switching device that the written data is written to the first cache address;
The first controller is further configured to establish a correspondence between the address of the written data, the identifier of the first cache device, and the first cache address according to the notification. The storage array of claim 7. The storage array further comprises a second cache device, the second cache device connected to the switching device;
The first controller is further configured to obtain a second cache address assigned to the written data in the second cache device in accordance with the data write request;
The first controller is further configured to send the identifier of the second cache device and the second cache address to the input / output manager via the switching device;
The I / O manager is further configured to write the written data to the second cache address via the switching device according to the identifier of the second cache device and the second cache address. The storage array according to claim 7. The first controller is further configured to obtain a second cache address assigned to the written data in a second cache device in accordance with the data write request;
The first controller is further configured to send a data write command to the first cache device via the switching device, the data write command including an identifier of the second cache device and the second Including the cache address of
The storage array according to claim 7, wherein the first cache device is configured to write the written data to the second cache address via the switching device in accordance with the data write instruction. The data write request holds an address of the written data, and the address of the written data includes an identifier of a target logical unit LU where the written data is located, a logical block address of the written data, The I / O manager sends the data write request to the first controller via the switching device, including the length of the data to be written;
The input / output manager inquires about a homing relationship between the target LU stored in the input / output manager and the first controller according to the identifier of the target LU, and the first controller Identifying the home controller as
Sending the data write request by the I / O manager to the first controller via the switching device;
8. The storage array of claim 7, wherein The data write request holds an address of the written data, and the address of the written data includes an identifier of a target logical unit LU where the written data is located, a logical block address of the written data, The storage array further comprises a second controller, the second controller is connected to the switching device, and the input / output manager sends the data write request to the switching device. Sending to the first controller via
Sending the data write request by the I / O manager to the second controller via the switching device;
Determining by the second controller according to the identifier of the target LU that the first controller is a home controller of the target LU;
Sending the data write request by the second controller to the first controller via the switching device;
8. The storage array of claim 7, wherein

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