JP6924671B2 - Data write request processing method and storage array - Google Patents

Description

The present invention relates to the field of information technology, and more particularly to data write request processing methods and storage arrays.

A storage array typically includes one engine, one engine containing two controllers, which is commonly referred to as a dual controller structure. As shown in FIG. 1, the storage array includes an input / output manager A, an input / output manager B, a controller A, and a controller B. The I / O manager A is connected to the controller A, and the I / O manager B is connected to the controller B. The controller A includes a peripheral component interconnect express (PCIe) switch A, a central processing unit (CPU) A, and a memory A; the controller B is a peripheral component interconnect express (PCIe). It includes a Peripheral Controller Input Express (PCIe) switch B, a central processing unit (CPU) B, and a memory B. The PCIe switch A is connected to the PCIe switch B. In the storage array shown in FIG. 1, the input / output manager A receives a data write request. The target logical unit (LU) of the data write request is homing to the controller A. That is, the controller A writes the data held in the data write request to the target LU. The input / output manager A transmits a data write request to the CPU A via the PCIe switch A of the controller A, and the CPU A writes the data and the metadata held in the data write request to the memory A. The CPU A writes the data and metadata in the memory A to the hard disk according to the settings of the storage array.

The above data writing process in the storage array consumes the CPU computing power of the controller and the memory resources of the controller, and seriously affects the performance of the storage array.

Embodiments of the present invention provide a data write request processing method and a storage array.

According to a first aspect, one embodiment of the present invention provides a data write request processing method, the method being applied to a storage array, the storage array being the input / output manager, the switching device, and the first. The controller and the first cache device are provided, the I / O manager is connected to the switching device; the first controller is connected to the switching device; the first cache device is connected to the switching device; the switching device is the storage. Connected to the hard disk in the array;
With the step of sending a data write request to the first controller via the switching device by the I / O manager;
With the step of acquiring the first cache address assigned to the data written in the first cache device according to the data write request by the first controller;
The step of transmitting the identifier of the first cache device and the first cache address to the input / output manager via the switching device by the first controller;
With the step of writing the data written by the input / output manager to the first cache address via the switching device according to the identifier of the first cache device and the first cache address;
including.

With reference to the first aspect of the invention, in the first possible embodiment, the data write request retains the address of the data to be written;
With the step of receiving the response by the I / O manager indicating that the data to be written was successfully written, which is sent by the first cache device;
The step of notifying the first controller that the data to be written is written to the first cache address by the input / output manager via the switching device;
The step of establishing a correspondence between the address of the data written by the first controller, the identifier of the first cache device, and the first cache address according to the notification;
Is further included.

With reference to the first aspect of the invention, in a second possible embodiment, the storage array further comprises a second cache device, the second cache device is connected to a switching device, the method:
With the step of acquiring the second cache address assigned to the data written in the second cache device according to the data write request by the first controller;
The step of transmitting the identifier of the second cache device and the second cache address to the input / output manager via the switching device by the first controller;
With the step of writing the data written by the input / output manager to the second cache address via the switching device according to the identifier of the second cache device and the second cache address;
Is further included.

With reference to the first aspect of the invention, in a third possible embodiment, the storage array further comprises a second cache device, the second cache device is connected to a switching device, the method:
With the step of acquiring the second cache address assigned to the data written in the second cache device according to the data write request by the first controller;
A step of transmitting a data write instruction to the first cache device via the switching device by the first controller, wherein the data write instruction holds the identifier of the second cache device and the second cache address. With steps;
With the step of writing the data written by the first cache device to the second cache address via the switching device according to the data write instruction;
Is further included.

With reference to the first aspect of the present invention, in a fourth possible embodiment, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic in which the data to be written is located. The unit LU identifier, the logical block address of the data to be written, and the length of the data to be written are included; the step of sending a data write request by the I / O manager to the first controller via the switching device is:
The step of inquiring the homing relationship between the target LU and the controller stored in the I / O manager by the I / O manager according to the identifier of the target LU, and determining that the first controller is the home controller of the target LU;
With the step of sending a data write request to the first controller via the switching device by the I / O manager;
In particular.

With reference to the first aspect of the present invention, in a fifth possible embodiment, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic in which the data to be written is located. Includes the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the storage array further comprises a second controller, which is connected to the switching device; by the I / O manager. , The step of sending a data write request to the first controller via the switching device is:
With the step of sending a data write request to the second controller via the switching device by the I / O manager;
The step of determining that the first controller is the home controller of the target LU according to the identifier of the target LU by the second controller;
With the step of transmitting a data write request to the first controller via the switching device by the second controller;
In particular.

According to a second aspect, one embodiment of the invention provides a storage array, the storage array comprising an input / output manager, a switching device, a first controller, and a first cache device. The output manager is connected to the switching device; the first controller is connected to the switching device; the first cache device is connected to the switching device; the switching device is connected to the hard disk in the storage array;
The I / O manager is configured to send data write requests through the switching device to the first controller;
The first controller acquires the first cache address assigned to the data written in the first cache device according to the data write request, and sets the identifier of the first cache device and the first cache address as the switching device. It is configured to send to the I / O manager via
The I / O manager is further configured to write the data to be written to the first cache address via the switching device according to the identifier of the first cache device and the first cache address.

With reference to the second aspect of the invention, in the first possible embodiment, the data write request retains the address of the data to be written;
The I / O manager is further configured to receive a response sent by the first cache device indicating that the data to be written has been successfully written;
The I / O manager is further configured to notify the first controller via the switching device that the data to be written will be written to the first cache address;
The first controller is further configured to establish a correspondence between the address of the data to be written, the identifier of the first cache device, and the first cache address in accordance with the notification.

With reference to a second aspect of the invention, in a second possible embodiment, the storage array further comprises a second cache device, the second cache device being connected to a switching device;
The first controller is further configured to obtain a second cache address assigned to the data written in the second cache device in response to a data write request;
The first controller is further configured to send the identifier of the second cache device and the second cache address to the I / O manager via the switching device;
The I / O manager is further configured to write the data to be written to the second cache address via the switching device according to the identifier of the second cache device and the second cache address.

With reference to a second aspect of the invention, in a third possible embodiment, the storage array further comprises a second cache device, where the second cache device is connected to a switching device;
The first controller is further configured to obtain a second cache address assigned to the data written in the second cache device in response to a data write request;
The first controller is further configured to send a data write instruction via the switching device to the first cache device, which holds the identifier of the second cache device and the second cache address. ;
The first cache device is configured to write the data to be written to the second cache address via the switching device in accordance with the data write instruction.

With reference to the second aspect of the present invention, in a fourth possible embodiment, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic in which the data to be written is located. It includes the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the I / O manager may send a data write request to the first controller via the switching device:
The I / O manager queries the homing relationship between the target LU and the controller stored in the I / O manager according to the identifier of the target LU, and determines that the first controller is the home controller of the target LU;
Sending a data write request through the switching device to the first controller by the I / O manager;
In particular.

With reference to the second aspect of the present invention, in a fifth possible embodiment, the data write request holds the address of the data to be written, and the address of the data to be written is the target logic in which the data to be written is located. Includes the identifier of the unit LU, the logical block address of the data to be written, and the length of the data to be written; the storage array further comprises a second controller, which is connected to the switching device; the I / O manager Sending a data write request to the first controller via the switching device is:
Sending a data write request through the switching device to the second controller by the I / O manager;
The second controller determines that the first controller is the home controller of the target LU according to the identifier of the target LU;
Sending a data write request to the first controller via the switching device by the second controller;
In particular.

According to the data write request processing method and storage array provided in the embodiments of the present invention, the controller is connected to the cache device via the switching device, and the input / output manager is connected to the controller via the switching device for input / output. The manager is connected to the cache device through the switching device. The controller obtains the cache address from the cache device for the data to be written according to the data write request, and the controller sends the cache device identifier and cache address to the I / O manager via the switching device, and the I / O manager Writes the data to be written to the cache address via the switching device, thereby saving the controller's CPU computing resources and the controller's memory resources and improving data write efficiency.

In order to more clearly explain the technical solution in the embodiments of the present invention, the accompanying drawings required to illustrate the embodiments will be briefly introduced below. The accompanying drawings in the following description merely show some embodiments of the present invention, and other drawings can be further derived from these attached drawings.

It is a block diagram of the storage array in the prior art. It is a block diagram of the storage array by one Embodiment of this invention. It is a flowchart of processing of the data write request by one Embodiment of this invention. It is a flowchart of processing of the data write request by one Embodiment of this invention. It is a flowchart of the process of the data read request by one Embodiment of this invention. It is a schematic diagram of the eigenvalue index set of a data block. It is a flowchart of data deduplication processing by one Embodiment of this invention.

Hereinafter, the technical solution according to the embodiment of the present invention will be clearly described with reference to the accompanying drawings according to the embodiment of the present invention. Obviously, the embodiments described are only some, but not all, of the embodiments of the present invention. It is assumed that all other embodiments obtained based on the embodiments of the present invention are within the scope of protection of the present invention.

The storage array provided in the embodiment of the present invention, such as the storage array shown in FIG. 2, includes an input / output manager A, a controller A, an input / output manager B, a controller B, a switching device A, and a switching device B. And a cache device M. The controller A includes a CPU A and a memory A, and the CPU A communicates with the memory A via a bus; the controller B includes a CPU B and a memory B, and the CPU B has a memory B via a bus. Communicate with. The input / output manager A is connected to the switching device A and the switching device B, and the input / output manager B is connected to the switching device A and the switching device B. The switching device A is interconnected to the switching device B. Both the switching device A and the switching device B are connected to the cache device M. The cache device M will be described in detail below. The controller A is connected to the switching device A and the switching device B, and the controller B is connected to the switching device A and the switching device B. Based on the above description, a fully interconnected architecture is formed around the switching device A and the switching device B by the I / O manager A, the I / O manager B, the controller A and the controller B. In the storage array shown in FIG. 2, the switching device A is connected to all hard disks, and the switching device B is also connected to all hard disks. Both controller A and controller B communicate with all the hard disks shown in FIG. In particular, the controller A communicates with all the hard disks via the switching device A, and the controller B communicates with all the hard disks via the switching device B. The controller A is configured to virtualize the hard disk to form a logical unit LU A that can be used by the host A. The LU A is mounted on the host A, and the host A executes a data access operation to the LU A via the controller A. Here, LU A is homing to controller A, that is, controller A is LU A's home controller. Similarly, the controller B is configured to virtualize the hard disk to form a logical unit LU B that can be used by the host B. The LU B is mounted on the host B, and the host B executes a data access operation to the LU B via the controller B. Here, it is stated that LU B is homing to controller B, i.e. controller B is the home controller of LU B. The host here may be a physical host (or is called a physical server) or a virtual host (or is called a virtual server). The logical unit LU is generally referred to as a logical unit number (LUN) in the industry. Assigning a LUN to a host actually means assigning an identifier for the LU to the host, thereby mounting the LU on the host. Therefore, LU and LUN mean the same thing here. In the storage array shown in FIG. 2, the switching devices A and B are a PCIe switching device, a non-volatile memory express (NVMe) switching device, and a serial attached small computer system interface (Serial Attached SCSI, SAS). It may be a switching device or the like, and this is not limited by the embodiment of the present invention. When the switching devices A and B are PCIe switching devices, the hard disk connected to the PCIe switching device is a hard disk having a PCIe protocol interface; when the switching devices A and B are NVMe switching devices, they are connected to the NVMe switching device. The hard disk to be used is a hard disk having an NVMe protocol interface; when switching devices A and B are SAS switching devices, the hard disk connected to the SAS switching device is a hard disk having a SAS protocol interface. The hard disk shown in FIG. 2 may be a mechanical hard disk, a solid state disk (SSD), or a hard disk of another medium. With respect to the hard disks in the storage array shown in FIG. 2, the storage media of different disks may be different, thereby forming a hybrid hard disk storage array, but this is not limited by the embodiments of the present invention.

The cache device M is another storage device suitable for use as a cache device, even if it is a storage device formed of a volatile storage medium or a non-volatile storage medium such as a phase change memory (PCM). It may be a non-volatile storage medium, which is not limited by embodiments of the present invention. The cache device M is configured to cache data. Hereinafter, the cache device M will be described with reference to the specific embodiment of the present invention. In the embodiment of the present invention, a case where the switching device A is a PCIe switching device, the switching device B is a PCIe switching device, and the hard disk is an SSD having a PCIe protocol interface is used as an example.

In the storage array shown in FIG. 2, the input / output manager A receives the data write request transmitted by the host. In one embodiment, the controller A is the home controller of the I / O manager A. Therefore, the I / O manager A receives the data operation request sent by the host. If the request transmission policy of the I / O manager A is not changed, the request is sent to the controller A by default according to the data operation request, so that the controller A is called the home controller of the I / O manager A. In one embodiment of the invention, the I / O manager A receives the data write request transmitted by the host and transmits the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. With respect to the particular PCIe switching device through which the request is transferred, it may be determined according to preset rules. When the PCIe switching device is selected, the input / output manager A then communicates with the controller A via the PCIe switching device. Of course, the input / output manager A may randomly select a PCIe switching device to communicate with the controller A, which is not limited by the embodiments of the present invention. An embodiment of the present invention uses an example in which the input / output manager A selects a PCIe switching device A and communicates with the controller A.

The data write request received by the I / O manager A holds the address of the data to be written. The address of the data to be written includes the identifier of the target LU of the data to be written, the logical block address (Logical Block Address, LBA) of the data to be written, and the length of the data to be written. The input / output manager A transmits a data write request to the controller A. The controller A receives the data write request and determines whether or not the controller A is the home controller of the target LU according to the identifier of the target LU of the data to be written at the address of the data to be written.

When the controller A is the home controller of the target LU, that is, the target LU is generated by the controller A by virtualizing the hard disk and provided to the host. The controller A determines the cache device used to cache the data to be written. This cache device is the cache device M in this embodiment of the present invention. The implementation method is as follows: The controller A instructs the cache device M to assign a cache address to the data to be written according to the data write request, and the cache device M assigns the cache address according to the length of the data to be written. .. The controller A acquires a cache address assigned by the cache device M for the data to be written (hereinafter, the cache address assigned by the cache device M for the data to be written is called a cache address M, and in one implementation method, the cache address M is used. The cache address includes the start address and length). The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The input / output manager A receives the cache device M identifier and cache address M transmitted by the controller A, and writes (or writes data) the data to be written to the cache address M according to the cache device M identifier and cache address M. May be written directly to the cache address M). The controller A acquires only the cache address M assigned to the data to be written, and the input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A. This saves the CPU computing resource of the controller A and the memory resource of the controller A as compared with the prior art, and improves the data writing efficiency.

The controller A establishes a correspondence between the address of the data to be written, the identifier of the cache device M, and the cache address M, and therefore, when reading the data to be written, the controller A is the cache address of the data to be written. M is transmitted to the input / output manager A, and the input / output manager A may read the data to be written from the cache address M of the data to be written (or directly read the data to be written from the cache address M of the data to be written). It may save CPU computing resources of controller A and memory resources of controller A, thereby improving data read efficiency.

If the storage array does not perform data deduplication after the conditions are met, the cache device M stores the data to be written in the target SSD of the storage array. The target SSD refers to an SSD for storing the data to be written. The specific process of writing the data to be written to the target SSD may be as follows: Controller A sends the cache device M identifier and cache address M to the controller of the target SSD via the PCIe switching device A or PCIe switching device B. Send. The controller of the target SSD directly reads the data written from the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address M, and stores the written data. The controller of the target SSD transmits the storage address of the data written in the target SSD to the controller A via the PCIe switching device A or the PCIe switching device B. The storage address of the data written in the target SSD includes the identifier of the controller of the target SSD and the logical storage address for storing the data written in the target SSD. The controller A establishes a correspondence between the address of the data to be written and the storage address of the data to be written to the target SSD.

The above process is particularly shown in FIG.

Step 301: The host sends a data write request to the I / O manager A.

The input / output manager A is an input / output / reception management device in the storage array, and plays a role of receiving the data operation request transmitted by the host and transferring the data operation request to the controller. In one embodiment of the invention, the host sends a data write request holding the address of the data to be written to the I / O manager A. Illustratively, a Small Computer System Interface (SCSI) protocol, ie, a SCSI protocol data write request, may be used for a data write request. Of course, other protocols may be used, which are not limited by embodiments of the invention.

Step 302: Send a data write request to controller A.

In this embodiment of the invention, the I / O manager A typically communicates with a particular controller. The input / output manager A may establish a correspondence with the controller in a plurality of methods, for example, according to the load of the controller or according to a specific route selection algorithm, but this is not limited by the present invention. The input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. In this embodiment of the present invention, it is used as an example that the input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A.

Step 303: Controller A acquires the cache address of the data to be written.

The controller A receives the data write request transmitted by the I / O manager A and determines the cache device used to cache the written data. This is the cache device M in this embodiment of the present invention. In one embodiment, the cache device M allocates a segment of cache address to the controller A. In the cache address segment, controller A assigns cache address M to the data to be written according to the length of the data to be written. In another embodiment, the controller A transmits an instruction to the cache device M via the PCIe switching device A or the PCIe switching device B. The instruction holds the length of the data to be written and instructs the cache device M to assign a cache address to the data to be written. The controller A acquires the cache address M.

Step 304: The identifier of the cache device M and the cache address M are transmitted.

The controller A acquires the cache address M and transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The identifier of the cache device M is the device address.

Step 305: The host sends the data to be written to the I / O manager A.

The I / O manager A receives the identifier and cache address M of the cache device M transmitted by the controller A, and receives the written data transmitted by the host.

Step 306: Write the data to be written to the cache address M.

The input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M. The input / output manager A receives a response, which is transmitted by the cache device M, indicating that the data to be written has been successfully written, via the PCIe switching device A. The I / O manager A sends a response indicating that the data write request is completed to the host, and notifies the host that the write request operation is completed.

Step 307: Notify the controller A that the data to be written is written to the cache address M.

The input / output manager A succeeds in writing the data to be written to the cache address M, and notifies the controller A that the data to be written is written to the cache address M.

Step 308: Controller A establishes a correspondence between the address of the data to be written, the cache device M, and the cache address M.

The controller A receives the notification transmitted by the input / output manager A, and establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M.

The cache device M assigns a cache address M to the data to be written, thereby establishing a correspondence between the address of the data to be written and the cache address M. The cache device M may acquire the address of the data to be written from the cache address allocation instruction transmitted by the controller A, and after allocating the cache address M, the cache device M may obtain the address of the data to be written and the cache. Establish a correspondence with the address M. In another embodiment, the cache device M is the exclusive cache device for the target LU and is only used to cache the data in the target LU, thus the cache device M is, by default, the target LU and the target LU. Stores the correspondence between the LBA and the cache address in. By default, the cache device M stores the correspondence between the target LU, the LBA in the target LU, and the segment of the cache address of the cache device M. In this segment of cache address, cache device M assigns cache address M to the data to be written.

In order to improve the reliability of the storage array and to cache multiple copies of the data to be written, in the prior art shown in FIG. 1, the I / O manager A transmits the data to be written and the CPU A. The data to be written is written to the memory A, the CPU A reads the data to be written from the memory A, and transmits the written data to the PCIe switch B via the PCIe switch A. The PCIe switch B transmits the data to be written to the CPU B, and the CPU B writes the data to be written to the memory B. In this embodiment of the present invention, the storage array caches the written data in a plurality of cache devices in order to prevent the loss of the written data in the cache device M. Therefore, it is used as an example that the data to be written is cached in two cache devices. The storage array shown in FIG. 2 further includes a cache device N. Both the PCIe switching device A and the PCIe switching device B are connected to the cache device N. Therefore, the controller A receives the data write request transmitted by the input / output manager A, determines that the cache device M plays a role as a primary cache device for caching the data to be written, and determines that the data to which the cache device N is written. It is judged that it plays a role as a secondary cache device that caches. The controller A is assigned to the data to be written and acquires a cache address located in the cache device M and the cache device N. In one embodiment, the controller A transmits an instruction to each of the cache device M and the cache device N. The instruction is used to instruct both the cache device M and the cache device N to assign a cache address to the data to be written. The instruction holds the length of the data to be written. The cache address assigned to the data written by the cache device M is called the cache address M, and the cache address assigned to the data written by the cache device N is called the cache address N. The controller A acquires the cache address M and the cache address N. The controller A transmits the identifier and cache address M of the cache device M to the input / output manager A via the PCIe switching device A, and inputs and outputs the identifier and cache address N of the cache device N via the PCIe switching device A. Send to manager A. In a particular embodiment, the controller A transfers the identifier and cache address M of the cache device M and the identifier and cache address N of the cache device N via one message or via two messages, respectively. It can be sent to A, which is not limited here. In another embodiment, the cache device M allocates an exclusive segment of the cache address to the controller A. This exclusive segment is only used to cache the data in the LU of home controller A. In this segment of the cache address of the cache device M, the controller A directly assigns the cache address M to the data to be written. The cache device N assigns an exclusive segment of the cache address to the controller A, and in this segment of the cache address of the cache device N, the controller A directly assigns the cache address N to the data to be written.

The input / output manager A receives the identifier and cache address M of the cache device M, and the identifier and cache address N of the cache device N. The input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A according to the identifier and the cache address M of the cache device M, and the input / output manager A writes the identifier and the cache address of the cache device N. According to N, the data to be written is written directly to the cache address N via the PCIe switching device A. The input / output manager A receives a response indicating that the data to be written has been successfully written to the cache address M via the PCIe switching device A, and the address of the data to be written to the controller A and the cache device M are received. Command to establish a correspondence between the identifier of and the cache address M. Similarly, the controller A establishes a correspondence between the address of the data to be written, the identifier of the cache device N, and the cache address N.

In another embodiment, the controller A transmits the cache device M identifier and cache address M to the I / O manager A via the PCIe switching device A. The input / output manager A receives the identifier of the cache device M and the cache address M. The input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier and the cache address M of the cache device M. The controller A transmits a data write instruction to the cache device M via the PCIe switching device A or the PCIe switching device B. The data write instruction holds the identifier of the cache device N and the cache address N. The cache device M caches the data to be written, and the cache device M writes the written data directly to the cache address N via the PCIe switching device A or the PCIe switching device B according to the data write instruction.

The controller A need only acquire the cache address M and the cache address N assigned to the written data so that the input / output manager A writes the data to be written to the cache device M and the cache device N. As a result, the CPU computing resource of the controller A and the memory resource of the controller A are saved, and the data writing efficiency is improved.

In another case, the I / O manager A receives the host data write request. The data write request holds the address of the data to be written. The input / output manager A transmits a data write request to the controller A by transferring the data by the PCIe switching device A. The controller A receives the data write request transmitted by the I / O manager A, and determines that the controller A is not the home controller of the target LU according to the identifier of the target LU held in the data write request. A particular embodiment is shown in FIG.

Step 401: The host sends a data write request to the I / O manager A.

The host sends a data write request to the I / O manager A. The data write request holds the address of the data to be written.

Step 402: Send a data write request to controller A.

In this embodiment of the present invention, the controller A is the home controller of the I / O manager A. The input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A or the PCIe switching device B. In this embodiment of the present invention, it is used as an example that the input / output manager A receives the data write request and transmits the data write request to the controller A via the PCIe switching device A.

Step 403: It is determined that the controller A is not the home controller of the target LU.

The controller A receives the data write request transmitted by the input / output manager A, and determines that the controller A is not the home controller of the target LU according to the identifier of the target LU of the data to be written held in the data write request. The controller A inquires about the correspondence between the controller and the LU, and determines that the controller B is the home controller of the target LU.

Step 404: Send a data write request to controller B.

The controller A transmits a data write request to the controller B via the PCIe switching device A or the PCIe switching device B. In this embodiment, the PCIe switching device B transfers a data write request to the controller B as an example.

Step 405: Acquire the cache address of the data to be written.

The controller B receives the data write request transmitted by the controller A and determines the cache device used to cache the written data. In this embodiment of the invention, this is the cache device M. For a specific implementation method, refer to a method in which the controller A acquires the cache address of the data written from the cache device M.

Step 406: The identifier of the cache device M and the cache address M are transmitted to the controller A.

The controller B acquires the cache address M and transmits the identifier of the cache device M and the cache address M to the controller A via the PCIe switching device B. In another embodiment, the cache device M identifier and cache address M may also be transmitted directly to the controller A via the PCIe switching device A or the PCIe switching device B.

Step 407: The identifier of the cache device M and the cache address M are transmitted to the I / O manager A.

The controller A receives the identifier and cache address M of the cache device M transmitted by the controller B, and transmits the cache address M of the data to be written via the PCIe switching device.

Step 408: The host sends the data to be written to the I / O manager A.

The I / O manager A receives the identifier of the cache device M and the cache address M, and responds to the data write request transmitted by the host. The host sends the written data to the I / O manager A.

Step 409: Write the data to be written to the cache address M.

The input / output manager A receives the written data transmitted by the host, and writes the written data directly to the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M. The input / output manager A receives a response indicating that the data to be written has been successfully written, which is transmitted by the cache device M, via the PCIe switching device A. The I / O manager A sends a response indicating that the data write request is completed to the host, and notifies the host that the write request operation is completed.

Step 410: Notify the controller B that the data to be written is written to the cache address M.

The input / output manager A succeeds in writing the data to be written to the cache address M, and notifies the controller B that the data to be written is written to the cache address M. This is in particular that the I / O manager A forwards the notification to the controller A via the PCIe switching device A, and the controller A forwards the notification to the controller B via the PCIe switching device B; The input / output manager A includes transmitting the notification directly to the controller B via the PCIe switching device A or the PCIe switching device B.

Step 411: The controller B establishes a correspondence between the address of the data to be written, the cache device M, and the cache address M.

The controller B establishes a correspondence relationship between the address of the data to be written, the cache device M, and the cache address M according to the notification transmitted by the input / output manager A.

Regarding how the cache device M establishes the correspondence between the address of the data to be written and the cache address M, the description in the above embodiment is referred to, and the details are not repeatedly described here. ..

The cache device N assigns a cache address N to the data to be written, thereby establishing a correspondence between the address of the data to be written and the cache address N. The cache device N may acquire the address of the data to be written from the cache address allocation instruction transmitted by the controller A, and after allocating the cache address N, the cache device N sets the address of the data to be written and the cache. Establish a correspondence with the address N.

In order to prevent the loss of the written data cached in the cache device M, the written data requires a plurality of cache devices that act as caches in a scenario in which the controller A is not the home controller of the target LU of the written data. At that time, the I / O manager A sends a data write request to the controller B. For the process, refer to the description in the above embodiment. For the process of acquiring the cache address of the data to be written by the controller B, refer to the scenario in which the controller A is the home controller of the target LU of the data to be written and the controller A acquires the cache addresses of a plurality of cache devices. .. The other steps will also be referred to in the above embodiments, and the details will not be repeated here.

After the host writes the data to the storage array, the host accesses the written data, i.e. sends a data read request. The specific process is shown in FIG.

Step 501: Send a data read request.

The host sends a data read request to the I / O manager A. The data read request holds the address of the data to be read. The address of the data to be read includes the identifier of the logical unit LU in which the data to be read is located, the LBA of the data to be read, and the length of the data to be read. In particular, the host may send a data read request to the I / O manager A by using the SCSI protocol, but this is not limited by the present invention. For ease of explanation, the data read here is the data to be written as described above.

Step 502: Send a data read request to controller A.

The input / output manager A receives the data read request transmitted by the host, and transmits the data read request to the controller A via the PCIe switching device A.

Step 503: The controller A transmits the identifier of the cache device M and the cache address M to the I / O manager A.

When the controller A is the home controller of the LU in which the data to be read is located and the data to be read is cached in a cache device such as the cache device M, the address of the data to be read and the identifier of the cache device are obtained according to the data read request. The correspondence between the data and the cache address is inquired, and the cache address M used to cache the read data in the cache device M is determined. When the data to be read is still cached in the cache device M, the cache address of the data to be read in the cache device M is the cache address M. The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A.

Step 504: Read the data read from the cache address M.

The input / output manager A directly reads the data read from the cache address M via the PCIe switching device A according to the identifier of the cache device M and the cache address M.

Step 505: Returns the data to be read.

The input / output manager A reads the data read from the cache address M and returns the read data to the host.

The input / output manager A sends a query request for the data to be read to the controller A via the PCIe switching device A in accordance with the data read request, and when the controller A is not the home controller of the LU in which the data to be read is located, the controller A inquires about the correspondence between the LU in which the data to be read is located and the home controller, and determines that the controller B is the home controller of the LU in which the data to be read is located. The controller A transmits a query request for the data to be read to the controller B via the PCIe switching device B. It is used as an example that the above written data is still the read data referred to herein. Therefore, the address of the data to be read is the address of the data to be written described above. When the data to be read is still cached in the cache device M, the cache address of the data to be read in the cache device M is the cache address M. The controller B inquires about the correspondence between the address of the data to be written, the identifier of the cache device M, and the cache address M, determines the identifier and cache address M of the cache device M that caches the read data, and caches the cache. The device M identifier and cache address M are transmitted to the controller A via the PCIe switching device B. The controller A transmits the identifier of the cache device M and the cache address M to the input / output manager A via the PCIe switching device A. The controller B may also transmit the identifier of the cache device M and the cache address M directly to the input / output manager A via the PCIe switching device A or the PCIe switching device B. For the subsequent read operation, refer to the read operation in the above embodiment, and the details will not be described repeatedly here.

It is used as an example that the above written data is still the read data referred to herein. Therefore, the address of the data to be read is the address of the data to be written described above. When the data to be read is already stored in the target SSD, the home controller of the LU where the data to be read is located has the address of the data to be read (the address of the data to be written) and the storage address of the data to be read in the target SSD. Inquire about the correspondence between the two, acquire the storage address of the data to be read in the target SSD, and transmit the storage address of the data to be read in the target SSD to the input / output manager A via the PCIe switching device A or the PCIe switching device B. do. The storage address of the data to be read in the target SSD includes the identifier of the controller of the target SSD and the logical storage address of the data to be read in the target SSD. The input / output manager A reads the data read from the logical storage address of the data read in the target SSD directly via the PCIe switching device A or the PCIe switching device B according to the storage address of the data read in the target SSD.

In the above embodiment, when the data to be read is partially stored in the target SSD and partially cached in the cache device M in this embodiment of the invention as described above, the I / O Manager A The data is read directly from the cache address via the PCIe switching device A or the PCIe switching device B according to the cache address of the data read in the cache device; the input / output manager A reads the controller identifier of the target SSD and the read in the target SSD. Data is read directly from the logical storage address in the target SSD via the PCIe switching device A or the PCIe switching device B according to the logical storage address of the data. This is not described in detail here.

When a plurality of cache devices execute an operation of caching the data to be read, the home controller of the LU in which the data to be read is usually located is a primary cache that caches the data to be read and the cache address M in the input / output manager A. Returns the device M identifier. For other procedural operations, the read operation in the above embodiment is referred to, and the details are not repeatedly described here.

Data deduplication is performed in the storage array. This can save storage space and reduce storage costs. In the storage array shown in FIG. 2 according to the embodiment of the present invention, the host sends a data write request to the I / O manager A, and the data write request holds the address of the data to be written. The input / output manager A transmits a data write request to the controller A via the PCIe switching device A. When the controller A is the home controller of the target LU of the data to be written, the controller A provides the identifier of the cache device M and the cache address M to the input / output manager A. The input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier and the cache address M of the cache device M.

Data deduplication is performed before the data to be written cached in the cache device M is stored in the SSD of the storage array. This can effectively save storage space and improve storage space utilization. Using the storage array shown in FIG. 2 as an example, data deduplication is executed for the data stored in the storage array SSD before the data is stored in the SSD by the cache device M. The data deduplication technique divides data into data blocks according to preset rules and calculates the eigenvalues of each data block. The eigenvalues of a data block are usually calculated by using the Hash algorithm. The hash operation is performed on the data block to obtain a hash value, and this hash value is used as an eigenvalue. Common hash algorithms include MD5, SHA1, SHA-256, SHA-512 and the like. For example, when the eigenvalue of the data block A is the same as the eigenvalue of the data block B already stored in the SSD, the data block A and the data block B are the same. Therefore, the duplicate data block A is deleted from the cache device M, and the logical storage address for storing the data block B in the SSD is used as the logical storage address of the data block A in the SSD.

In certain embodiments, the controller performs a comparison of the eigenvalues of the data blocks. Data deduplication is done in the storage array and each unique data block has eigenvalues, so many eigenvalues are generated. To achieve equilibrium between the controllers in the storage array, each controller serves to compare the eigenvalues of several data blocks according to a data block eigenvalue distribution algorithm, such as a hash distribution algorithm. In this way, each controller maintains only the eigenvalue index of some unique data stored in the storage array according to the data block eigenvalue distribution algorithm. The eigenvalue index of some unique data is called the eigenvalue index set. The controller queries the eigenvalue index set for the eigenvalues of the data blocks that will be written to the SSD and determines if the eigenvalues are the same as the eigenvalues in the eigenvalue index set. For example, controller A must maintain eigenvalue index set A according to the eigenvalue distribution algorithm, so is controller A the home controller for all eigenvalues in eigenvalue index set A; or eigenvalues from eigenvalue index set A. The controller in which is the same as the eigenvalue of the data block X is both the eigenvalue home controller of the data block X and the eigenvalue home controller of all the eigenvalues in the eigenvalue index set A.

In particular, the eigenvalue index set is formed by the eigenvalue indexes shown in FIG. For example, the index of eigenvalue 1 includes the eigenvalue 1, the data block storage address 1, and the reference count. The data block storage address 1 is used to represent the storage address of the unique data block C in the SSD A or the storage address of the data block C in the cache device. The storage address of the data block C in the SSD A may include the identifier of the controller of the SSD A and the logical storage address of the data block C stored in the SSD A. The storage address of the data block C in the cache device includes the identifier of the cache device and the cache address. The eigenvalue 1 represents the eigenvalue of the data block C. The reference count represents the amount of data blocks having an eigenvalue of 1. For example, when the data block A is stored in the storage array for the first time, if the amount of the data block having the eigenvalue 1 is 1, the reference count is 1. When the data block D having the same unique value 1 is stored in the SSD again, the data block D is not stored in the SSD according to the principle of data deduplication, but the reference count is increased by 1 and updated to 2. In summary, the data block storage address in the eigenvalue index is either the storage address of the data block in the cache device or the storage address of the data block in the target hard disk. The storage address of the data block in the cache device includes the cache device identifier and the cache address of the data block in the cache device; the data block storage address in the target hard disk includes the controller identifier of the target hard disk and in the target hard disk. Contains a logical storage address for storing data blocks of. The eigenvalue index shown in FIG. 6 is merely an exemplary embodiment, and the eigenvalue index may be a multi-level index. The index may be any form of index that can be used for data deduplication, which is not limited by this embodiment of the invention.

In the storage array shown in FIG. 2, it is used as an example that the controller A plays a role as a home controller of the target LU of the data block cached in the cache device M. Referring to the above embodiment, after receiving the data write request, the input / output manager A acquires the identifier of the cache device M and the cache address M from the controller A. The input / output manager A writes the data to be written directly to the cache address M via the PCIe switching device A or the PCIe switching device B according to the identifier and the cache address M of the cache device M. The controller A establishes a correspondence relationship between the address of the data to be written, the identifier of the cache device M, and the cache address M. When the data cached in the LU of the home controller A is written from the cache device M to the SSD, the data at the cache address M is used as an example. Normally, when data deduplication is taking place, the eigenvalues of the data blocks need to be calculated. In order to calculate the eigenvalues of a data block, the data must first be divided according to the unique rules to get the data block. There may be two methods for dividing into data blocks, namely dividing the data into fixed-length data blocks or dividing the data into variable-length data blocks. In this embodiment of the invention, it is used as an example that the data is divided into fixed length data blocks. For example, the data is divided into data blocks with a size of 4KB. Illustratively, the data to be written, which is written to the cache address M, is divided into several data blocks having a size of 4KB. The controller A records the LU identifier of each data block, the LBA of the data block, and the length of the data block. The LU identifier of the data block, the LBA of the data block, and the length of the data block are hereafter referred to as the data block storage address. Using the data block X in some data blocks with a size of 4KB as an example (where the data block X is called a data block to be deduplicated) and shortened. The controller A transmits a data block unique value request to the cache device M via the PCIe switching device A or the PCIe switching device B (also known as a to-be-deduplicated data block). .. The eigenvalue request includes the address of the data block X. The cache device M transmits the unique value of the data block X to the controller A via the PCIe switching device A or the PCIe switching device B in order to perform data deduplication. As shown in Figure 7, certain processes include:

Step 701: The cache device M calculates the eigenvalues of the data block X.

The controller A transmits an instruction to acquire the eigenvalue of the data block X to the cache device M. The instruction holds the address of the data block X. The cache device M receives an instruction to acquire the eigenvalue of the data block X transmitted by the controller A. In this case, the cache device M stores the correspondence between the address of the data block X and the cache address B, and data according to the address of the data block X held in the instruction for acquiring the unique value of the data block X. The block X is determined, the unique value of the data block X is calculated, and the unique value of the data block X is cached in the cache address X.

Step 702: The eigenvalue of the data block X is transmitted to the controller A.

The cache device M acquires the eigenvalue of the data block X and transmits a response message of the eigenvalue of the data block X to the home controller A of the LU in which the data block X is located. The response message of the eigenvalue of the data block X holds the eigenvalue of the data block X. Further, the response message of the unique value of the data block X further holds the identifier of the cache device M that caches the unique value of the data block X and the cache address X of the unique value of the data block X in the cache device M.

Step 703: Determine the home controller for the eigenvalues of the data block X according to the eigenvalue distribution algorithm.

Step 704: Controller A queries the local eigenvalue index set A.

When the controller A is the home controller of the eigenvalues of the data block X, the controller A queries the local eigenvalue index set A and determines whether or not the same eigenvalues as the eigenvalues of the data block X exist in the eigenvalue index set A. ..

Steps 705a and 706a are executed when the same eigenvalues as the eigenvalues of the data block X exist in the eigenvalue index set A. As shown in FIG. 6, the eigenvalue of the data block X is the same as the eigenvalue 1. That is, the data block X is the same as the data block A.

Step 705a: Controller A updates the reference count at the index of eigenvalue 1.

The reference count at the index of eigenvalue 1 is 1, i.e., only data block A is present in the storage array. It turns out that the eigenvalues of the data block X are the same as the eigenvalues 1, so the reference count is updated to 2.

Step 706a: Controller A instructs cache device M to delete the data block X.

The controller A instructs the cache device M to delete the data block X. The controller A establishes a correspondence between the address of the data block X and the unique value of the data block X, or the controller A has the address of the data block X, the unique value of the data block X, and the unique value of the data block A. Establish a correspondence with the storage address.

In step 704, the data block X is determined to be a duplicate data block. Therefore, the data block X does not need to be stored in the SSD, and the cache device M is instructed to delete the data block X.

Steps 705b, 706b, 707, 708, 709 and 710 are executed when the same eigenvalues as the eigenvalues of the data block X do not exist in the eigenvalue index set A.

Step 705b: Acquire the cache address B of the data block X cached in the cache device M.

The controller A acquires the cache address B of the data block X from the cache device M via the PCIe switching device A according to the cache address X of the unique value of the data block X in the cache device M.

Step 706b: The identifier of the cache device M and the cache address B are transmitted to the controller of the target SSD.

The controller A acquires the identifier of the cache device M and the cache address B, and transmits the identifier of the cache device M and the cache address B to the controller of the target SSD via the PCIe switching device A or the PCIe switching device B.

Step 707: The controller of the target SSD reads the data block X from the cache address B.

The controller of the target SSD receives the identifier of the cache device M and the cache address B, and according to the identifier and the cache address B of the cache device M, the data block X from the cache address B via the PCIe switching device A or the PCIe switching device B. Is read directly.

Step 708: The controller of the target SSD transmits the storage address of the data block X in the target SSD to the controller A.

The controller of the target SSD reads the data block X from the cache address B and stores the data block X in the target SSD. The controller of the target SSD transmits the storage address of the data block X in the target SSD to the controller A via the PCIe switching device A. The storage address of the data block X in the target SSD includes the identifier of the controller of the target SSD and the logical storage address for storing the data block X in the target SSD.

Step 709: Controller A establishes an eigenvalue index for data block X.

The controller A receives the storage address of the data block X in the target SSD, establishes the eigenvalue index of the data block X, and sets the reference count to 1. The controller A establishes a correspondence relationship between the address of the data block X, the eigenvalue of the data block X, and the storage address of the data block X in the target SSD. The controller A also needs to record the cache address X of the eigenvalue of the data block X. When the eigenvalue of the data block X is stored in the SSD, the controller A also needs to record the storage address of the eigenvalue of the data block X in the target SSD.

In another example, the controller A is not the home controller of the eigenvalues of the data block X, but is simply the home controller of the LU where the data block X is located. In this embodiment of the present invention, it is used as an example that the controller B is a home controller of the eigenvalue of the data block X, and the controller A transfers the eigenvalue of the data block X via the PCIe switching device A or the PCIe switching device B. Send to controller B. The controller B receives the eigenvalue of the data block X transmitted by the controller A and queries the eigenvalue index set B of the controller B. When the controller B finds that the eigenvalues of the data block X are the same as the eigenvalues of the data block X in the eigenvalue index set A, for example, the controller B finds that the eigenvalues of the data block R are the same as the eigenvalues of the data block X. Instruct device M to delete data block X. This specifically includes the controller B transmitting a delete instruction to the controller A via the PCIe switching device B. The controller A transmits a deletion instruction to the cache device M via the PCIe switching device A, and the cache device M deletes the data block X. The controller B updates the reference count of the index of the same eigenvalue as the eigenvalue of the data block X, that is, increases the reference count by one. When the data block R is already stored in the SSD, the storage address of the data block R in the index of the data block R is the identifier of the controller of the SSD that stores the data block R and the data block R for storing the data block R in the SSD. Includes logical storage address. When the data block R is in the cache device, the storage address of the data block R in the index of the data block R includes the identifier of the cache device and the cache address. The controller A establishes a correspondence between the address of the data block X, the unique value of the data block X, and the address of the home controller B of the unique value of the data block X, so that the controller A is the address of each data block. And, the correspondence between the unique value of the data block and the storage address of the data block is not required, and the amount of data stored by the controller A is efficiently reduced. Alternatively, the controller A establishes a correspondence between the address of the data block X, the eigenvalues of the data block X, and the storage address of the data block R. After that, when reading the data block X, the controller A obtains the storage address of the data block R by inquiring about the correspondence between the address of the data block X, the unique value of the data block X, and the storage address of the data block R. The input / output manager A can directly determine, and the input / output manager A directly reads the data block X from the storage address of the data block R via the PCIe switching device A or the PCIe switching device B, thereby improving the data reading efficiency.

When the controller A is simply the home controller of the LU in which the data block X is located, but is not the home controller of the eigenvalues of the data block X, the controller B has the same eigenvalues as the eigenvalues of the data block X in the eigenvalue index set B. The controller B obtains the cache address B of the data block X in the cache device M by sending a request to the controller A via the PCIe switching device B. The controller A transmits a request to the cache device M via the PCIe switching device A. The cache device M transmits the identifier of the cache device M and the cache address B to the controller B. The controller B transmits the identifier of the cache device M and the cache address B to the controller of the target SSD via the PCIe switching device A or the PCIe switching device B (where the PCIe switching device A is used as an example). The controller of the target SSD directly reads the data block X from the cache address B via the PCIe switching device A or the PCIe switching device B according to the identifier of the cache device M and the cache address B, and stores the data block X in the target SSD. .. The controller of the target SSD transmits the storage address of the data block X in the target SSD to the controller B via the PCIe switching device A or the PCIe switching device B. The controller B receives the storage address of the data block X in the target SSD, establishes the eigenvalue index of the data block X, and sets the reference count in the index to 1. The controller B also needs to record the cache address X of the eigenvalue of the data block X. When the eigenvalue of the data block X is stored in the SSD, the controller B also needs to record the storage address of the eigenvalue of the data block X in the SSD.

The controller B receives the storage address of the data block X in the target SSD and transmits a notification to the controller A. The notification holds the storage address of the data block X in the target SSD. The controller A establishes a correspondence between the address of the data block X, the eigenvalue, and the storage address of the data block X in the target SSD according to the notification transmitted by the controller B. In another embodiment, when controller A is simply the home controller of the LU in which the data block X is located, but not the home controller of the unique value of the data block X, the controller A is the address of the data block X and the data. Establish a correspondence between the unique value of block X and the address of controller B.

According to the storage array in this embodiment of the present invention, the cache device performs the calculation of the fingerprint of the data block X. This saves the controller's computational resources. During the process of storing the data block X in the target SSD, the controller provides only the cache device M identifier and cache address B, and the controller of the target SSD reads the data block X directly from the cache address B. This saves controller computing and memory resources and improves storage array performance.

Based on the storage array shown in FIG. 2, data is written to the SSD according to the above data deduplication operation. When the I / O manager A receives a data read request holding the address of the data block X, for example, a request to read the data block X, the I / O manager A sends a data read request to the controller A via the PCIe switching device A. Send. The controller A determines that the controller A is the home controller of the LU in which the data block X is located. In one embodiment, the controller A searches for a correspondence between the address of the data block X, the unique value of the data block X to be read, and the storage address of the data block X in the target SSD, and searches for the correspondence between the data block in the target SSD. Determine the storage address of X. The controller A transmits the storage address of the data block X in the target SSD to the input / output manager A via the PCIe switching device A. The input / output manager A uses the data block X read from the target SSD, that is, the data block X from the logical storage address of the data block X in the target SSD via the PCIe switching device A or the PCIe switching device B according to the storage address of the data block X. Is read directly. In another embodiment, controller A searches for a correspondence between the address of data block X, the unique value of data block X, and the home controller address of the unique value of data block X, and finds the unique value of data block X. The home controller B of the data block X is determined and the unique value index of the data block X in the controller B is queried to determine the storage address of the data block X in the target SSD; or the home controller B of the unique value of the data block X is determined. The eigenvalue index of the data block having the same eigenvalue as the eigenvalue of the data block X in the controller B is queried to determine the storage address of the data block having the same eigenvalue as the eigenvalue of the data block X, and then the eigenvalue of the data block X and Data is read from the storage address of the data block having the same unique value. When the controller A is both the home controller of the LU in which the data block X is located and the home controller of the unique value of the data block X, in another embodiment, the controller A has the address of the data block X to be read and the data. The correspondence with the unique value of block X is searched, the unique value index set A maintained by the controller A is queried according to the unique value of data block X, the storage address of the data block X to be read is determined, and then the storage address of the data block X to be read is determined. The storage address of the data block X to be read is transmitted to the input / output manager A. The input / output manager A reads a data block from the storage address of the data block X via the PCIe switching device A or the PCIe switching device B.

When the data written to the storage array shown in FIG. 2 is written to a plurality of cache devices and the data deduplication operation is executed, the data deduplication is performed only for the data in one of the cache devices. Will be executed. In particular, data deduplication can be performed on the data in the primary cache device, or one of the cache devices to perform a data deduplication operation according to the load of multiple cache devices that cache the data. One is selected, but this is not limited by this embodiment of the invention.

In this embodiment of the invention, in another embodiment, the concept of homing does not necessarily exist between the I / O manager and the controller. That is, the controller A is not the home controller of the I / O manager A. Each I / O manager stores a correspondence between the LU and the controller on which the LU is homing. The I / O manager inquires about the correspondence between the target LU identifier and the home controller according to the target LU identifier held in the data operation request, determines the home controller of the target LU, and determines the PCIe switching device A or PCIe. The request is sent directly to the home controller of the target LU via the switching device B. In addition, via any PCIe switching device, between controllers, between controllers and SSDs, between I / O managers and controllers, or between I / O managers and SSDs, or with cache devices. Communication may occur between the controller or between the cache device and the SSD. In this embodiment of the present invention, the logical storage address for storing the data block X in the storage address on the target hard disk refers to the logical block address for storing the data block X on the target hard disk, and in particular, the embodiment of the present invention. In the form, it refers to a logical block address for storing the data block X in the target SSD.

In this embodiment of the invention, FIG. 2 shows only two controllers, two switching devices, two I / O managers and one cache device. However, in certain embodiments, the amount of controllers, switching devices, I / O managers and cache devices may be set and flexibly expanded as needed. Any I / O manager is connected to any controller via any switching device, or any I / O manager is connected to any hard disk via any switching device, or any I / O The manager is connected to any cache device via any switching device. Any controller is connected to any controller via any switching device, or any controller is connected to any hard disk via any switching device, or any controller is any switching device. Connected to any cache device via. Any cache device is connected to any hard disk via a switching device. Bidirectional communication is carried out between any two devices connected via any switching device. Any two switching devices are directly connected. In the storage array architecture provided in this embodiment of the invention, logically, the controllers are collectively referred to as the controller plane, the switching devices are collectively referred to as the switching plane, and the hard disks are collectively referred to as the storage plane. The I / O manager is collectively referred to as the I / O management plane, and the cache device is collectively referred to as the cache plane. In the architecture provided in this embodiment of the invention, data read and write control is separated from data read and write. The controller performs data read and write control, but data read and write (or in other words, read and write data) does not pass through the controller. This saves the CPU computing resources of the controller and the memory resources of the controller, improves the data write efficiency, and improves the data processing efficiency of the storage array. The storage array architecture in this embodiment of the present invention can carry out expansion of devices such as controllers and hard disks, and controllers, switching devices, hard disks and the like may be flexibly added according to the performance requirements of the storage array.

Of course, the technical solution in this embodiment of the invention is also applicable to scenarios where the storage array includes one I / O manager, one controller, one switching device, one cache device and some hard disks. Is. For the method of writing data to the storage array in this scenario, refer to the description in the above embodiment. See description in the above embodiments for scenarios where data deduplication is performed on the storage array. For the data read operation performed in the storage array, refer to the description in the above embodiment. Of course, the storage array may include two controllers and one switching device, the two controllers being connected to the switching device. Regarding the data writing operation, the data deduplication operation, and the data reading operation in such a scenario, the description in the above-described embodiment is referred to, and the details are not repeatedly described here.

In this embodiment of the invention, device A reads data from cache address A (or, in other words, reads data directly from cache address A), and according to device B identifier and cache address A, PCIe switching device A or Data is written to cache address A via the PCIe switching device B (or in other words, data is written directly to cache address A). Such an embodiment may be implemented by Direct Memory Access (DMA) technology, where device A and device B specifically represent a device that performs DMA access in this embodiment of the invention.

The controller acquires the cache address of the device B and transmits the identifier of the device B and the cache address of the device B to the device C via the PCIe switching device A or the PCIe switching device B. The controller communicates with the device B to acquire the cache address via the PCIe switching device A or the PCIe switching device B, and has already learned the identifier of the device B. Therefore, the cache address is acquired and the identifier of the device B is obtained. And the cache address of device B may be transmitted to device C. Of course, the controller may also obtain the device B identifier and cache address. The identifier of device B may be the address of device B or another identifier that uniquely identifies the device.

Those skilled in the art will appreciate that the exemplary units and algorithmic steps described with reference to the embodiments disclosed herein may be performed by electronic hardware or by a combination of computer software and electronic hardware. Can be recognized. Whether a function is performed by hardware or software depends on the particular application and design constraints of the technical solution. One of ordinary skill in the art can use different methods to perform the functions described for a particular application, but the practice should not be considered beyond the scope of the present invention.

For convenience and brief description, the detailed operating processes of the above systems, devices and units will be referred to in reference to the corresponding processes in embodiments of the above methods, and the details may not be repeated herein. , Can be clearly understood by those skilled in the art.

It should be understood that in some embodiments provided in this application, the disclosed systems and methods may be implemented in other ways. For example, the embodiments of the devices described are merely exemplary. For example, the unit division is simply a logical function division, and may be another division in an actual embodiment. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. In addition, the interconnected or direct coupled or communication connections displayed or considered may be implemented through several interfaces. Indirect coupling or communication connections between devices or units may be performed electronically, mechanically, or in other forms.

A unit described as a separate part may or may not be physically separate, and the part displayed as a unit may be a physical unit or not a physical unit. It may be located in a location or distributed over multiple network units. Some or all of the units may be selected according to the actual need to achieve the objectives of the solution of the embodiment.

Further, the functional units according to the embodiments of the present invention may be integrated into one processing unit, or each of the units may exist physically alone, or two or more units may be combined into one unit. Will be integrated.

When a function is performed in the form of a software functional unit and sold or used as a stand-alone product, the function may be stored in a computer-readable non-volatile storage medium. Based on such an understanding, the technical solutions of the present invention may be implemented in the form of software products, either essentially or in part that contributes to the prior art, or some of the technical solutions. good. The software product is stored in a non-volatile storage medium and the computer device (which may be a personal computer, server, or network device) is subjected to all or some of the steps of the method described in the embodiments of the present invention. Includes multiple instructions to instruct to execute. The above-mentioned non-volatile storage medium includes any medium capable of storing a program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a magnetic disk or an optical disk.

Claims (6)

A method for processing a data write request in a storage array including an input / output manager, a switching device, a first controller, a first cache device, and a second cache device. manager, said first controller, said first cache device and the second cache devices connected to the switching device, the switching device is connected to the storage unit in the storage array, before SL method,
A step of transmitting a data write request to the first controller via the switching device by the input / output manager.
The first cache address in the first cache device for storing the data of the data write request and the second cache device in the second cache device for the data write request by the first controller. Steps to get the cache address of
The first controller transfers the identifier of the first cache device, the first cache address, the identifier of the second cache device, and the second cache address to the input / output manager via the switching device. And the steps to send to
The input / output manager writes the data of the data write request to the first cache address via the switching device according to the identifier of the first cache device and the first cache address, and the first cache address. A step of writing the data of the data write request to the second cache address via the switching device according to the identifier of the cache device 2 and the second cache address.
A step of storing the data of the first cache address in the storage unit by the first cache device, and
Including methods. The data write request includes the address of the data, and the method
A step of receiving a response by the input / output manager indicating that the data has been successfully written, which is transmitted by the first cache device, and
A step of transmitting a notification from the input / output manager to the first controller via the switching device that the data is written to the first cache address.
A step of establishing a correspondence between the address of the data, the identifier of the first cache device, and the first cache address by the first controller according to the notification.
The method according to claim 1, further comprising. The data write request holds the address of the data, and the address of the data includes the identifier of the target logical unit (LU) in which the data is located, the logical block address of the data, and the length of the data. Including, said method
The input / output manager inquires about the homing relationship between the target LU stored in the input / output manager and the first controller according to the identifier of the target LU, and the first controller asks the target LU. And the steps to identify it as a home controller
A step of transmitting the data write request to the first controller via the switching device by the input / output manager.
The method according to claim 1, further comprising. A storage array, the storage array comprising an input / output manager, a switching device, a first controller, a first cache device, and a second cache device, the input / output manager, the first. The controller, the first cache device and the second cache device are connected to the switching device, and the switching device is connected to a storage unit in the storage array .
The input / output manager is configured to send a data write request to the first controller via the switching device.
The first controller acquires a first cache address in the first cache device and a second cache address in the second cache device for storing the data of the data write request, and obtains the second cache address. The identifier of the first cache device, the first cache address, the identifier of the second cache device, and the second cache address are configured to be transmitted to the input / output manager via the switching device.
The input / output manager writes the data to the first cache address via the switching device according to the identifier of the first cache device and the first cache address, and the second cache device. According to the identifier and the second cache address, the data of the data write request is further configured to write to the second cache address via the switching device .
The first cache device is a storage array further configured to store the data at the first cache address in the storage unit. The data write request holds the address of the data and
The input / output manager receives a response from the first cache device indicating that the data has been successfully written, and the data is sent to the first controller via the switching device. Further configured to send a notification that it will be written to the cache address,
The first controller is further configured to establish a correspondence between the address of the data, the identifier of the first cache device, and the first cache address in accordance with the notification. , The storage array according to claim 4. The data write request holds the address of the data, and the address of the data includes the identifier of the target logical unit (LU) in which the data is located, the logical block address of the data, and the length of the data. Including, the input / output manager inquires about the homing relationship between the target LU and the first controller stored in the input / output manager according to the identifier of the target LU, and the first controller makes the said. The storage array according to claim 4 , further configured to identify the home controller of the target LU and transmit the data write request to the first controller via the switching device.

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