JPS62133560A - Access control system for dual port memory - Google Patents

Abstract

PURPOSE:To eliminate an access competition by determining an access right to a dual port memory according to the state of a flip-flop. CONSTITUTION:The flip-flop 34 is set by a CPU 11, and reset by a CPU 21. When it is confirmed that the state Q of the flip-flop 34 becomes L, by a state detecting circuit 37, and it is known that the access right to the dual port memory is obtained, the CPU 11 writes a message to the CPU 21, in the dual port memory. The CPU 21 which knows that the terminal Q becomes L, by a state detecting circuit 38, and secures the access right executes the read processing of a message from the CPU 11, and writes a result in the dual port memory.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Field of Industrial Application The present invention relates to a Keltual port memory in a multiprocessor system, and relates to the transfer of IP to a VW'l dual port memory.

(7) With the development of the conventional semiconductor integrated circuit wave 8, small, high-performance microprocessors are being supplied at low prices, and as a result, the use of multiple microprocessors has led to higher functionality, higher reliability, and higher scalability. Research and development of multiprocessor systems having a multiprocessor system have been actively conducted, and several applications have been filed (for example, Japanese Patent Application No. 197040/1983).

A shared memory that can be accessed by multiple different central processing units (hereinafter referred to as CPUs) is a memory-sharing type multiprocessor system in which the coupling between processors is relatively tight among multiprocessor systems, and communication between processors is frequent. Used as communication buffer memory essential to the system. Among them, a shared memory that can be accessed by two CPUs is called a dual-port memory, and is the most commonly used type of shared memory. FIG. 3 shows a configuration diagram of a conventional dual port memory. (211) is CP T
Local ROM (212), local RA, M in J1
(213), and (221) is local R on CPU2.
It includes an OM (222) and a local I/AM (223). (230) is a dual port memory and the memory part (
231), system bus 1 (2
14) and the data buffer 1 (262) and address buffer 1 (233) connected to the CPU 2 (221).
Data buffer 2 (234) and address buffer 2 (235) connected to system bus 2 (224) of
and a memory bus arbitration circuit (266) for eliminating access requests from two different CPUs. The memory bus arbitration circuit (236) is connected to the system bus 1 (2, 14).
) K connected bus arbiter 1 (237) and bus controller 1 (238), and the system bus 2 (2
24) FC-connected bus arbiter 2 (239), bus controller 2 (240), and bus priority circuit (241)
).

These bus arbiter 1 (237), bus controller 1 (238), bus arbiter 2 (239), bus controller 2 (240), and bus priority circuit (241) are connected to the CPUI (211) or the system bus 1 (21).
4) - or CPU 2 (221) or system bus 2 (224) has α1''I, which has the disadvantage that it cannot be used if the CPU or system bus family is different. For relatively low-level microprocessors such as bit microprocessors, peripheral devices such as path arbiters and bus controllers are not available, and it has been difficult to realize dual port memory between these CPUs.

c) Problems to be solved by the invention The present invention has been made in view of the above-mentioned points.
The overall purpose is to realize a dual port memory that eliminates access contention.

2) Means for resolving the problem of inadequacy The present invention provides an access control system for dual-port memory shared by two central processing units, in which the dual-port memory is set by only one central processing unit and A flip-flop that is reset only by a central processing unit is provided, and when the flip-flop is set, access to the dual port memory is enabled from the other central processing unit, and the clip-flop is reset. This is a dual-port memory access control system that allows one of the central processing units 4 to access the dual-port memory.

E) Function: Dual baud and memory access are determined by the states of the flip-flops that are set by only one central processing unit and reset by the other central processing bag 111, so two central processing units The first 10 matches from the top are eliminated.

f) Embodiment 81! Figure 1 is a schematic configuration diagram of a dual port memory according to the present invention. (The group is CPU1, local en OMQ
3. Local RAM (including 1~, system bus 104
Connected to 1. 121) The CPU 2 includes a local ROM and a local RAM, and is connected to the system bus 2. (1) is these CPU1 old), CP
This is a dual port memory provided between system bus 1 and system bus 2 between U21!21).

The dual port memory α island is set by the memory unit 011, the bidirectional buffer 1 C33 connected to the system bus 104), the bidirectional buffer 2 connected to the system bus 2, and the CPU 1111. CPU 261!1)
-8 flip-flop C34) and the system bus 1
a multiplexer IC3 that outputs either the address received from the zero address or the system bus 2041 to the memory section t31 depending on the state of the flip-flop;
5) and the command (π1, WR1) input received from the system bus 1 (141) or the system bus 2@
Depending on the state of the flip-flop, one of the commands (π2.WR2) received from the memory section (3.
1), two multiplexers for outputting to the surface terminal and layer 1 terminal, and a state detection circuit IC37) for setting the flip-flop (2) including a decoder and reading the state of the flip-flop (34). , a state detection circuit 2 (9) for resetting the flip-flop including the decoder and reading the state of the flip-flop (b);
), and the buffer 1 (321) and the buffer 2 are connected by a memory data bus (39).In this embodiment, the flip-flop (2) is a CP
It can be set by U1, reset by CPU2, and when the flip-flop is set, CPU2
When it is reset, CPU1 is given access to the dual port memory, but it is reset by CPU1 and set by CPU2 by the output of another port, and when setting the communication protocol, , set (or reset) with CPU1
, so that the CPU2 is reset (or set), and when the flip-flop is set, the CP
When U2 (or CPU1) is reset, CPU1 (or CPU2) may be given access to the dual port memory.

When the power is turned on, the flip-flop θ(a) is reset (ie, the Q terminal is set to "L") by a power-on reset circuit (not shown), and the CPU 1 acquires the right to access the dual port memory. When the CPU 1041 state detection circuit 107) confirms that the state Q of the flip-flop 04) has become "L" and learns that the access right to the dual port memory (1) is enabled,
CPU 2 e! to nuclear dual port memory (1) Write a message for 0. When terminal Q is at L°,
Buffer IC 321 is enabled and buffer 2031 is disabled, the address from system bus 1 (141) is selected in multiplexer 10, and the command (RD3WRt) of system bus 1 (141 color) is selected in multiplexer 2 (7). , memory section c3]) is a resource for CI'U1 (II!). At this time, the CPU 2 detects the state of the terminal σ by using the state detection circuit 20.
81, and the terminal phrase is 'H' (Q
, = “L”), so the dual port memory (to)
I found out that I don't have access to it.

Continue polling until access is established.

Now, once the message has been read to C1) Ul (Ill is CPU2al), it will either execute another process or wait for a message to be received from CPU 2121). You must waive your access rights. Therefore, the state detection circuit IC37) sets the terminal Q to "H".
-7. After completing the processing in step 110, the terminal Q becomes "L" again in order to receive the message from the CPU 2 (al), and the polling by the state detection circuit 1 (37) is continued. heart.

The CPU 2f2D learns that the terminal σ has become "L" (Q, - "H") by the state detection circuit 2 (To)) and has established access rights to the dual port memory (To).
#i, reads the message from the CPUI (11) from the dual port memory IJCII, processes it based on its contents, and writes the result to the CPU1 (message 7 for ill and dual port memory α), at this time , the terminal ζ is "Lo", so the buffer 1elZ is disabled and the buffer y2c331 is enabled, and the multiplexer 1c (9) receives the address from the system bus 2, and the multiplexer 2 (to) receives the address from the system bus 2. Bus 2 @ Garanoko-r7)” (1
1D2, WR2) is selected and the memo IJ section (3
1) It is a resource for U CPU U 2 all.

Now, after writing the message to CPU2e21JId'CPU1QI)K, other processing is executed.
P U 1 (Since it enters the state of waiting for message reception from Ill, the access right to the dual port memory must be relinquished (7. 7. Execute other processing In order to receive a message from CPtJl (111), the state detection circuit 2cJA continues polling until the terminal σ becomes "L"(Q-"H") again.

By setting the terminal Q to L°, the access right to the dual port memory button is granted.

Knowing that the access right has been obtained by the state detection circuit 107), it takes in the message from the CPU 2aη, and
After performing processing based on the contents and writing the maintenance for the CPU 2al) into the memory unit Q11.

The terminal Q and Th are set to "H" to give the access right to the dual port memory (to) to the CPU 221).

This operation is repeated thereafter. The above process is shown in the flowchart in Figure 2.

In this embodiment, the state of the flip-flop is monitored by polling the state detection circuit, but when the access right is transferred, the CPU on the side to which the access right has been transferred
It is also possible to interrupt the CPU, and by using the flip-flop status as an interrupt input to each CPU, the burden of polling can be reduced.

g) Effects of the Invention As is clear from the foregoing, the present invention does not require a special bus arbiter, bus controller, or path priority determination circuit for eliminating memory access contention, and can be implemented from two CPU systems that generally operate asynchronously. Accessible dual-port memory can be easily realized. In particular, it can be an extremely effective means for realizing dual port memory between relatively low-level microprocessors that are not equipped with special peripheral devices for path arbitration.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a dual port memory according to the present invention, FIG. 2 is a flowchart for explaining the operation, and FIG. 6 is a schematic configuration diagram of a conventional dual port memory.

Claims (1)

[Claims] 1. In an access control system for a dual-port memory shared by two central processing units, the dual-port memory includes a flip-flop that is set only by one central processing unit and reset only by the other central processing unit; When the flip-flop is set, the dual port memory can be accessed from the other central processing unit, and when the flip-flop is reset, the dual port memory can be accessed from the one central processing unit. A dual-port memory access control method characterized by allowing access to.