JPS6459447A - Data transfer circuit - Google Patents
Data transfer circuitInfo
- Publication number
- JPS6459447A JPS6459447A JP21539187A JP21539187A JPS6459447A JP S6459447 A JPS6459447 A JP S6459447A JP 21539187 A JP21539187 A JP 21539187A JP 21539187 A JP21539187 A JP 21539187A JP S6459447 A JPS6459447 A JP S6459447A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- mpu
- bit
- bit data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To minimize the capacity of a buffer memory by controlling a selector, which selects N-number of bits from (MXN)-bit data from an MPU and transfers N-bit data to a memory, and a [NX(M-1)]-bit buffer, where (M-1)-number of N-bit data are stored, by a timing generating part. CONSTITUTION:In case of data transfer from an MPU 1 to a memory 2, N- number of bits are selected from (MXN)-bit data from the MPU 1 by a selector 6 and a timing generating part 3 transfers data to the memory 2 M-number of times. In case of data transfer from the memory 2 to the MPU 1, the timing generating part 3 transfers data from the memory 2 (M-1)-number of times to store [(M-1)XN]-bit data in a buffer 5. The timing generating part 3 simultaneously transfers N-bit data from the memory 2 and [(M-1)XN]-bit data from the buffer 5 to the MPU 1 at the time of the M-th data transfer. Thus, the MPU accesses the N-bit memory in the same manner as the access to an (MXN)-bit memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21539187A JPS6459447A (en) | 1987-08-31 | 1987-08-31 | Data transfer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21539187A JPS6459447A (en) | 1987-08-31 | 1987-08-31 | Data transfer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6459447A true JPS6459447A (en) | 1989-03-07 |
Family
ID=16671536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21539187A Pending JPS6459447A (en) | 1987-08-31 | 1987-08-31 | Data transfer circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6459447A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315979A (en) * | 1992-03-27 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Electronic control apparatus for an internal combustion engine |
| KR100431107B1 (en) * | 1994-01-21 | 2004-05-20 | 가부시끼가이샤 히다치 세이사꾸쇼 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6111873A (en) * | 1984-06-28 | 1986-01-20 | Kokusai Electric Co Ltd | Accessing method to 8-bit and 16-bit peripheral devices by 16-bit microprocessor |
-
1987
- 1987-08-31 JP JP21539187A patent/JPS6459447A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6111873A (en) * | 1984-06-28 | 1986-01-20 | Kokusai Electric Co Ltd | Accessing method to 8-bit and 16-bit peripheral devices by 16-bit microprocessor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315979A (en) * | 1992-03-27 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Electronic control apparatus for an internal combustion engine |
| KR100431107B1 (en) * | 1994-01-21 | 2004-05-20 | 가부시끼가이샤 히다치 세이사꾸쇼 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method |
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