JPS5660933A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5660933A
JPS5660933A JP13614179A JP13614179A JPS5660933A JP S5660933 A JPS5660933 A JP S5660933A JP 13614179 A JP13614179 A JP 13614179A JP 13614179 A JP13614179 A JP 13614179A JP S5660933 A JPS5660933 A JP S5660933A
Authority
JP
Japan
Prior art keywords
memory
dma
contents
transfer
regarding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13614179A
Other languages
Japanese (ja)
Inventor
Hiromasa Tanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13614179A priority Critical patent/JPS5660933A/en
Publication of JPS5660933A publication Critical patent/JPS5660933A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To perform flexible high-speed data transfer between input-output equipment and a memory by providing a direct memory access controller that exercises continuous and automatic control on direct memory access transfer regarding plural data blocks.
CONSTITUTION: Direct memory access DMA start addresses of data blocks decentralized in the memory and the number of words are stored in memory part 3 successively. At the point in time when DMA transfer regarding one data block ends, the contents of memory part 3 assigned by the contents of the 2nd address register 4 are loaded into the 1st address register 1 and count register 2. Further, the DMA transfer regarding the next data block is started and repeated while the contents of register 4 are updated. Thus, the DMA controller that exercises continuous and automatic control on the DMA transfer regarding data blocks is provided so as to attain flexible high-speed data transfer between the input-output equipment and memory.
COPYRIGHT: (C)1981,JPO&Japio
JP13614179A 1979-10-22 1979-10-22 Information processor Pending JPS5660933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13614179A JPS5660933A (en) 1979-10-22 1979-10-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13614179A JPS5660933A (en) 1979-10-22 1979-10-22 Information processor

Publications (1)

Publication Number Publication Date
JPS5660933A true JPS5660933A (en) 1981-05-26

Family

ID=15168257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13614179A Pending JPS5660933A (en) 1979-10-22 1979-10-22 Information processor

Country Status (1)

Country Link
JP (1) JPS5660933A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181134A (en) * 1982-04-16 1983-10-22 Hitachi Ltd Data transfer circuit
EP0333594A2 (en) * 1988-03-18 1989-09-20 Fujitsu Limited Direct memory access controller
EP0428111A2 (en) * 1989-11-14 1991-05-22 Hitachi, Ltd. Data transfer control method and data processor using the same
EP0464615A2 (en) * 1990-06-25 1992-01-08 Nec Corporation Microcomputer equipped with DMA controller
US5218713A (en) * 1985-06-17 1993-06-08 International Business Machines Corporation Distributed data management mechanism for handling a data stream
US5644787A (en) * 1993-08-03 1997-07-01 Seiko Epson Corporation Apparatus for controlling data transfer between external interfaces through buffer memory using table data having transfer start address transfer count and unit selection parameter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192129A (en) * 1975-02-12 1976-08-12
JPS52147032A (en) * 1976-06-01 1977-12-07 Ibm Data transfer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5192129A (en) * 1975-02-12 1976-08-12
JPS52147032A (en) * 1976-06-01 1977-12-07 Ibm Data transfer system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181134A (en) * 1982-04-16 1983-10-22 Hitachi Ltd Data transfer circuit
US5218713A (en) * 1985-06-17 1993-06-08 International Business Machines Corporation Distributed data management mechanism for handling a data stream
EP0333594A2 (en) * 1988-03-18 1989-09-20 Fujitsu Limited Direct memory access controller
EP0428111A2 (en) * 1989-11-14 1991-05-22 Hitachi, Ltd. Data transfer control method and data processor using the same
EP0428111A3 (en) * 1989-11-14 1992-12-30 Hitachi, Ltd. Data transfer control method and data processor using the same
EP0464615A2 (en) * 1990-06-25 1992-01-08 Nec Corporation Microcomputer equipped with DMA controller
US5696989A (en) * 1990-06-25 1997-12-09 Nec Corporation Microcomputer equipped with DMA controller allowed to continue to perform data transfer operations even after completion of a current data transfer operation
US5644787A (en) * 1993-08-03 1997-07-01 Seiko Epson Corporation Apparatus for controlling data transfer between external interfaces through buffer memory using table data having transfer start address transfer count and unit selection parameter
US5832308A (en) * 1993-08-03 1998-11-03 Seiko Epson Corporation Apparatus for controlling data transfer between external interfaces through buffer memory using a FIFO, an empty signal, and a full signal

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