JPS6481054A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS6481054A
JPS6481054A JP62237142A JP23714287A JPS6481054A JP S6481054 A JPS6481054 A JP S6481054A JP 62237142 A JP62237142 A JP 62237142A JP 23714287 A JP23714287 A JP 23714287A JP S6481054 A JPS6481054 A JP S6481054A
Authority
JP
Japan
Prior art keywords
data
empu
transferred
delivers
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62237142A
Other languages
Japanese (ja)
Other versions
JP2619416B2 (en
Inventor
Giichi Aoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62237142A priority Critical patent/JP2619416B2/en
Publication of JPS6481054A publication Critical patent/JPS6481054A/en
Application granted granted Critical
Publication of JP2619416B2 publication Critical patent/JP2619416B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To realize the transfer of data among plural address spaces based on a block transfer instruction of data by using a control means which switches the spaces based on the control of the read/write directions of data carried out by a microcomputer. CONSTITUTION:When an address of the data related to the head to be transferred in blocks is delivered from an emulation microcomputer EMPU, a data input buffer DIBUFS delivers the data read out of a system memory SMEM to the EMPU. Then the EMPU delivers its fetched data in the next cycle as well as the head addresses of a series of transfer destinations to be transferred in blocks. Furthermore the EMPU instructs a writing action. Thus a data output buffer DOBUFU is ready to deliver the data delivered from the MPU and to be transferred to a user memory UMEM. Thus data are transferred.
JP62237142A 1987-09-24 1987-09-24 emulator Expired - Fee Related JP2619416B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237142A JP2619416B2 (en) 1987-09-24 1987-09-24 emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237142A JP2619416B2 (en) 1987-09-24 1987-09-24 emulator

Publications (2)

Publication Number Publication Date
JPS6481054A true JPS6481054A (en) 1989-03-27
JP2619416B2 JP2619416B2 (en) 1997-06-11

Family

ID=17011028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237142A Expired - Fee Related JP2619416B2 (en) 1987-09-24 1987-09-24 emulator

Country Status (1)

Country Link
JP (1) JP2619416B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328425B1 (en) * 1996-08-29 2002-03-16 피터 엔. 데트킨 method and apparatus for supporting multiple overlapping address spaces on a shared bus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127133A (en) * 1983-01-11 1984-07-21 Minolta Camera Co Ltd Data transmitting system
JPS59161737U (en) * 1984-03-29 1984-10-30 セイコーエプソン株式会社 A-D conversion circuit
JPS60245052A (en) * 1984-05-21 1985-12-04 Hitachi Ltd Data processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59127133A (en) * 1983-01-11 1984-07-21 Minolta Camera Co Ltd Data transmitting system
JPS59161737U (en) * 1984-03-29 1984-10-30 セイコーエプソン株式会社 A-D conversion circuit
JPS60245052A (en) * 1984-05-21 1985-12-04 Hitachi Ltd Data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100328425B1 (en) * 1996-08-29 2002-03-16 피터 엔. 데트킨 method and apparatus for supporting multiple overlapping address spaces on a shared bus

Also Published As

Publication number Publication date
JP2619416B2 (en) 1997-06-11

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees