JPS6432348A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS6432348A
JPS6432348A JP18941587A JP18941587A JPS6432348A JP S6432348 A JPS6432348 A JP S6432348A JP 18941587 A JP18941587 A JP 18941587A JP 18941587 A JP18941587 A JP 18941587A JP S6432348 A JPS6432348 A JP S6432348A
Authority
JP
Japan
Prior art keywords
memory
counter
address
buffer
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18941587A
Other languages
Japanese (ja)
Inventor
Takehiko Kurashige
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18941587A priority Critical patent/JPS6432348A/en
Publication of JPS6432348A publication Critical patent/JPS6432348A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the performance of a memory access system by regarding the buffer areas, etc., scattering in a physical memory space as one continuous memory area of an input/output buffer, etc., and giving the automatic and continuous accesses to plural partial areas after a single direct programming action given to a memory access device by a CPU. CONSTITUTION:When the information is transferred from a memory 12, a CPU sets the total transfer length (byte number) at a counter 26 of a DMA device 13. Then the CPU 11 takes out the head memory address A0 of a head input/ output buffer 0 and sets lower 12 bits of the address A0 at a counter 25. Then the memory addresses A0-n included in the buffer description words BDW0-n are successively transferred and written into a page number memory 21 at and after an address 0. A selector 31 selects a write signal 29 in accordance with a selection number 30 of a control part 23. A counter 22 shows the following write addresses every time 12 bits (page No.) are written. The device 13 become enable when the writing action is through up to an address (n). Hereafter the information is transferred by the start and the counter 26 transmits a transfer end signal 27 to the part 23 when an access is given to the final word position of the final buffer.
JP18941587A 1987-07-29 1987-07-29 Memory access system Pending JPS6432348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18941587A JPS6432348A (en) 1987-07-29 1987-07-29 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18941587A JPS6432348A (en) 1987-07-29 1987-07-29 Memory access system

Publications (1)

Publication Number Publication Date
JPS6432348A true JPS6432348A (en) 1989-02-02

Family

ID=16240884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18941587A Pending JPS6432348A (en) 1987-07-29 1987-07-29 Memory access system

Country Status (1)

Country Link
JP (1) JPS6432348A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354058U (en) * 1989-09-27 1991-05-24
JPH09114772A (en) * 1995-10-20 1997-05-02 Kofu Nippon Denki Kk Dma device and dma address conversion device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0354058U (en) * 1989-09-27 1991-05-24
JPH09114772A (en) * 1995-10-20 1997-05-02 Kofu Nippon Denki Kk Dma device and dma address conversion device

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