JPS6459692A - Dram control device with page mode function - Google Patents

Dram control device with page mode function

Info

Publication number
JPS6459692A
JPS6459692A JP62215104A JP21510487A JPS6459692A JP S6459692 A JPS6459692 A JP S6459692A JP 62215104 A JP62215104 A JP 62215104A JP 21510487 A JP21510487 A JP 21510487A JP S6459692 A JPS6459692 A JP S6459692A
Authority
JP
Japan
Prior art keywords
information
cell
generator
address information
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62215104A
Other languages
Japanese (ja)
Inventor
Yoshiki Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62215104A priority Critical patent/JPS6459692A/en
Publication of JPS6459692A publication Critical patent/JPS6459692A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE:To shorten an access time by selecting a generator based on the compared result of the row address information of a cell during the access at present and the row address of the cell accessed last time. CONSTITUTION:When a microprocessor 1 receives a cycle completion signal S3 or S4 from a timing generator 3 for a page mode or a timing generator 4 for normal access, the microprocessor 1 reads a piece of row address information RA and a piece of column address information CA. Next, when the information RA during an output at present corresponds to that of the pre-cycle, the RA enables the generator 3. Thus, a selector first selects the information RA, and next selects the information CA, and supplies them to a DRAM 1 as an address information ADD. Thus, a word line and a bit line are selected, and then, the cell is selected. When the information during the output at present does not correspond to that of the pre-cycle, the generator 4 is enabled, and the cell of the DRAM 1 is selected in the same way.
JP62215104A 1987-08-31 1987-08-31 Dram control device with page mode function Pending JPS6459692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62215104A JPS6459692A (en) 1987-08-31 1987-08-31 Dram control device with page mode function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62215104A JPS6459692A (en) 1987-08-31 1987-08-31 Dram control device with page mode function

Publications (1)

Publication Number Publication Date
JPS6459692A true JPS6459692A (en) 1989-03-07

Family

ID=16666820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62215104A Pending JPS6459692A (en) 1987-08-31 1987-08-31 Dram control device with page mode function

Country Status (1)

Country Link
JP (1) JPS6459692A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging
US6336162B1 (en) 1998-03-03 2002-01-01 International Business Machines Corporation DRAM access method and a DRAM controller using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715421A (en) * 1992-10-16 1998-02-03 Seiko Epson Corporation Apparatus and method of addressing paged mode memory including adjacent page precharging
US6336162B1 (en) 1998-03-03 2002-01-01 International Business Machines Corporation DRAM access method and a DRAM controller using the same

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