JPS6459692A - Dram control device with page mode function - Google Patents
Dram control device with page mode functionInfo
- Publication number
- JPS6459692A JPS6459692A JP62215104A JP21510487A JPS6459692A JP S6459692 A JPS6459692 A JP S6459692A JP 62215104 A JP62215104 A JP 62215104A JP 21510487 A JP21510487 A JP 21510487A JP S6459692 A JPS6459692 A JP S6459692A
- Authority
- JP
- Japan
- Prior art keywords
- information
- cell
- generator
- address information
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dram (AREA)
Abstract
PURPOSE:To shorten an access time by selecting a generator based on the compared result of the row address information of a cell during the access at present and the row address of the cell accessed last time. CONSTITUTION:When a microprocessor 1 receives a cycle completion signal S3 or S4 from a timing generator 3 for a page mode or a timing generator 4 for normal access, the microprocessor 1 reads a piece of row address information RA and a piece of column address information CA. Next, when the information RA during an output at present corresponds to that of the pre-cycle, the RA enables the generator 3. Thus, a selector first selects the information RA, and next selects the information CA, and supplies them to a DRAM 1 as an address information ADD. Thus, a word line and a bit line are selected, and then, the cell is selected. When the information during the output at present does not correspond to that of the pre-cycle, the generator 4 is enabled, and the cell of the DRAM 1 is selected in the same way.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62215104A JPS6459692A (en) | 1987-08-31 | 1987-08-31 | Dram control device with page mode function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62215104A JPS6459692A (en) | 1987-08-31 | 1987-08-31 | Dram control device with page mode function |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6459692A true JPS6459692A (en) | 1989-03-07 |
Family
ID=16666820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62215104A Pending JPS6459692A (en) | 1987-08-31 | 1987-08-31 | Dram control device with page mode function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6459692A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5715421A (en) * | 1992-10-16 | 1998-02-03 | Seiko Epson Corporation | Apparatus and method of addressing paged mode memory including adjacent page precharging |
US6336162B1 (en) | 1998-03-03 | 2002-01-01 | International Business Machines Corporation | DRAM access method and a DRAM controller using the same |
-
1987
- 1987-08-31 JP JP62215104A patent/JPS6459692A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5715421A (en) * | 1992-10-16 | 1998-02-03 | Seiko Epson Corporation | Apparatus and method of addressing paged mode memory including adjacent page precharging |
US6336162B1 (en) | 1998-03-03 | 2002-01-01 | International Business Machines Corporation | DRAM access method and a DRAM controller using the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO1992011638A3 (en) | Hidden refresh of a dynamic random access memory | |
JPS5764383A (en) | Address converting method and its device | |
KR920008594A (en) | Data processing system that dynamically sets the timing of the dynamic memory system | |
WO1990004576A3 (en) | Automatically variable memory interleaving system | |
JPS563499A (en) | Semiconductor memory device | |
JPS57150190A (en) | Monolithic storage device | |
US4779232A (en) | Partial write control apparatus | |
GB1468783A (en) | Memory systems | |
EP0153469B1 (en) | Refresh generator system for a dynamic memory | |
JPS6459692A (en) | Dram control device with page mode function | |
KR920005283B1 (en) | Dram controller | |
US5771369A (en) | Memory row redrive | |
JPS54130841A (en) | Address generator | |
JPS6421790A (en) | Dram controller with page mode function | |
KR950009745A (en) | Semiconductor memory | |
JPS57157365A (en) | Busy control system of memory controller | |
JPS6459438A (en) | Read-out method for memory device | |
JPS6419580A (en) | Dual port memory circuit | |
JPS5447445A (en) | Memory unit | |
JPH0782751B2 (en) | Semiconductor memory device | |
JPS5544263A (en) | Frame synchronous circuit | |
JPS5658196A (en) | Memory device having memory part for test | |
JPS55147788A (en) | Information output unit | |
JPS5611686A (en) | Storage unit | |
JPS5637900A (en) | Memory unit compensating defective cell |