JPH03182954A - Data processor - Google Patents

Abstract

PURPOSE:To improve processing capacity as a whole data processor by controlling a gate circuit if CPU in a processor is in an internal processing state, setting an internal bus and an external bus to be a non-condition state and outputting the use permission signal of the external bus to a peripheral equipment. CONSTITUTION:When a timing control circuit 11a detects that the processing of CPU 11 is an internal processing which does not use the external bus 20, it shifts a system between the internal bus 11e and the external bus 20 to be the non-connection state by dropping a strobe signal STB supplied to the gate circuit 13 to be low. When it receives a holding request signal HLDR from a DMA controller 23, it continues the internal processing state and returns the use permission signal of the external bus in the form of HLDA, which shows a shift to a holding state. Thus, the internal processing of the processor and data transfer by the peripheral equipment through the external bus can be executed in parallel and processing capacity as the whole data processor can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) (Field of Industrial Application) The present invention relates to a data processing device used in various control systems, communication systems, and the like.

Data processing devices used in various control systems and communication systems include a microprocessor with a built-in local memory connected to the internal bus of the CPU, and an external bus connected to the internal bus of the CPU in this microprocessor. There are some that consist of peripheral devices connected via.

(Problem to be Solved by the Invention) Conventionally, in the data processing device described above, the internal bus and external bus remain connected even while the CPU of the microprocessor uses only the internal bus. . Therefore, internal processing by the CPU and data transfer by the peripheral device via the external bus cannot be performed simultaneously, resulting in a problem that the processing capacity of the data processing device as a whole is reduced.

(Means for Solving the Problems) The data processing device of the present invention includes a gate circuit that can selectively connect an internal bus (2) of a CPU to an external bus, and an internal bus (2) in which a CPU in a processor does not use an external bus. It detects whether or not it is in the processing state, and if it is in the internal processing state, it controls the gate I circuit to disconnect the internal bus from the external bus and outputs an external bus use permission signal to the peripheral device. The controller is configured to enable internal processing of the processor and data transfer by peripheral devices via an external bus to be performed in parallel, thereby improving the processing capacity of the data processing device as a whole.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a data processing device according to an embodiment of the present invention, in which 10 is a microprocessor, 20 is an external bus, 21 is a human output (Ilo) interface circuit, and 22 is buffer memory (BM), 23 is D
It is an MA controller.

The microprocessor IO has a CPUI 1 and a local memory (LM) connected to the internal bus of this (3) CPU.
) 12 and a gate circuit 13. C.P.
The UII includes a timing/control circuit 11a, an instruction decoder llb, an arithmetic circuit 11c, a register group lid, and an internal bus lie interconnecting these circuits.

Instructions read from the local memory 12, which is composed of a ROM for storing programs and a RAM for storing data, are transferred to the instruction decoder llb via the internal bus lie and decoded. Various control signals are generated in the timing/control circuit 11a based on this decoding result and a predetermined timing signal, and the operation of the arithmetic circuit 11c is performed based on these control signals, and the arithmetic results are stored in various registers in the register group lid. or written to the local memory 12.

This timing/control circuit 11a includes an instruction decoder ll
Based on the decoding result of C and the contents of the address register and program counter in register group 11d
It is detected whether the PUII process is an internal process that does not use the external bus (4) 20 or an external process that uses the external bus 2°. When the timing/control circuit 11a detects that the CPU II processing is internal processing, the timing/control circuit 11a lowers the strobe signal STB supplied to the gate circuit 13 to a disconnected state between the internal bus lie and the external bus 2o. to be transferred to

The DMA controller 23 connected to the external bus 20 is
When it becomes necessary to use the external bus 20 for DMA transfer between the input/output interface circuit 21 and the buffer memory 22, a signal requesting the use of the external bus 2o is output to the timing/control circuit 11a in the CPU II.

As illustrated in the timing chart of FIG. 2, this external bus use request signal is generated by c
It is issued in the form of a hold request signal (HLDR) to puz. When the timing/control circuit 11a receives the hold request signal (5) (HLDR) from the DMA controller 23 in the internal processing state described above, it actually continues the internal processing state without shifting to the hold state. So, D
An external bus use permission signal in the form of HLDA indicating transition to the hold state is returned to the MA controller 23.

The DMA controller 23 that has received permission to use this external bus
starts DMA transfer using the external bus 20 between the turnout interface circuit 21 and the buffer memory 22. This transfer data on the external bus 20 and the internal bus l
Transfer data on le does not interfere with each other because both buses are separated by gate circuit 18. This DMA
When the transfer is completed, the DMA controller 23 transfers the
11, the hold request signal HLDR is pulled low, and in response, the hold signal HALDA
is also lowered to low.

The timing/control circuit 11a in the CPUI I controls the CPUI while the DMA transfer via the external bus 20 continues.
When it is detected that l is in an external processing state involving access to the buffer memory 22, it shifts to the (6) DMA transfer completion waiting state. The timing/control circuit 11a raises the external bus use permission signal (HLDA) to low level when the external bus use request signal (HLDR) falls to low level upon completion of the DMA transfer. In addition, the strobe signal STB supplied to the gate circuit 13 is raised to high level, and the internal bus Ice and the external bus 20 are connected. 1 starts accessing the CPU memory 22. This CPU 1 starts accessing the external bus 2.
In the use state of 0, even if an external bus use request (HLDR goes high) occurs from the DMA controller 23, HLDA remains low and permission to use the external bus is not issued.

When the external processing of the CPU II is completed, the timing/control circuit 11a lowers the strobe signal STB to low to return the internal bus lie and external bus 2o to a disconnected state, and also sets HLDA to high. By raising the flag, permission to use the external bus is issued to the DMA controller 23. Along with this, internal processing of C(7) P tJ + 1 and I) MA transfer by the DMA controller 1-1 caller 23 are started in parallel.

(Effects of the Invention) As described above in detail, the data processing device of the present invention controls the gate circuit to disconnect the internal bus and external bus when the CPU in the processor is in the internal processing state. Since the configuration also outputs an external bus use permission signal to peripheral devices, it is possible to perform internal processing of the processor and use of the external bus by peripheral devices in parallel, improving the processing capacity of the data processing device as a whole. This effect is produced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the data processing apparatus shown in FIG. 10...Microprocessor, 1]...CPU, 1
10... CPU II internal bus, 11a... timing/control circuit, I2... low (8) memory, I3... gate circuit, 20... external bus,
21... Human output interface circuit, 22... Hasofa memory, 23... DMA controller.

Claims (1)

[Claims] Consisting of a CPU, a processor equipped with a local memory connected to the internal bus of this CPU, and a peripheral device connected to the internal bus of the CPU in this microprocessor via an external bus. In a data processing device, a gate circuit capable of selectively connecting an internal bus of the CPU and an external bus; and a gate circuit that detects whether or not a CPU in the processor is in an internal processing state that does not use the external bus, and performs internal processing. control means for controlling the gate circuit to disconnect the internal bus and the external bus and outputting an external bus use permission signal to the peripheral device if the external bus is in the state. Data processing equipment.