JPH08185370A - Microprocessor controller - Google Patents

Abstract

PURPOSE: To provide a microprocessor controller capable of executing data transfer by a single bus cycle. CONSTITUTION: The microprocessor controller for mutually connecting a microprocessor 10, a memory 12 and a peripheral device 14 through an address bus 19 and a data bus 18 and controlling data transfer by the microprocessor 10 is provided with a buffer circuit 20 inserted into the data bus 18 among the microprocessor 10, the memory 12 and the device 14 and capable of setting up the microprocessor 10, the memory 12 and the device 14 to an interrupted state or a connected state in accordance with the control of the microprocessor 10. When the buffer means is set up to the interrupted state, the microprocessor 10 sets up either one of the memory 12 and the device 14 to a reading state and sets up the other to a writing state to directly execute data transmission/ reception between the memory 12 and the device 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor control device, and more particularly to a microprocessor control device capable of executing a data transfer operation at high speed.

[0002]

2. Prior Art and Problems to be Solved by the Invention FIG.
It is a block diagram which shows an example of a structure of the conventional microprocessor control device. In a device controlled by the microprocessor (hereinafter referred to as CPU) 10, when data is transferred between the memory 12 and a peripheral device (hereinafter referred to as I / O) 14, the CPU 10 first uses the first bus. In a cycle, data is read from one of the memory 12 and the I / O 14, and the data is written to the other in the next bus cycle. As an example, the case of transferring data from the memory 12 to the I / O 14 will be specifically described. In the first bus cycle, the CPU 10
Outputs a predetermined one address line 16 and an address strobe output (\ AS: "\" indicates a logical inversion, which is indicated by a horizontal line above a character in the drawing), and outputs it via the logic circuit 17. 12 is enabled, the I / O 14 is disabled, and a read control signal and an address signal are supplied to the memory 12 to read data at a predetermined address via the data bus 18. The address at this time is designated by the address bus 19. In the next second bus cycle, the CPU 10 disables the memory 12, sets the I / O 14 in the enabled state, and sets the I / O 14 in the written state to read in the previous bus cycle. I / O1
Write to the designated address of 4. Therefore, the memory 12
To transfer data from the I / O 14 to the
Cycle time is needed.

A DMA (direct memory access) technique for transferring data in a single bus cycle is also known, but it is a technique for executing data transfer without going through the CPU and is controlled by the CPU. When transferring data with
As mentioned above, two bus cycle periods were absolutely necessary. Further, in the DMA technology, data existing in a predetermined amount of continuous addresses is collectively transferred from the start address, and data of an arbitrary address cannot be transferred like data transfer by a CPU. It was

It is an object of the present invention to provide a microprocessor controlled device capable of performing the transfer of data at any address in a single bus cycle.

[0005]

According to the present invention, a microprocessor, a memory, and a peripheral device are interconnected by an address bus and a data bus, and the microprocessor controls data transfer. A microprocessor controller for inserting into the data bus between the microprocessor and the memory and peripheral device, and controlling the microprocessor and the memory and peripheral device under the control of the microprocessor. And a buffer circuit for setting either the connection state to the cutoff state or the connection state, and the microprocessor sets one of the memory and the peripheral device to the read state and the other when the buffer means is set to the cutoff state. Is set to the write state, and data is directly exchanged between the above memory and peripheral devices. Characterized in that to.

Therefore, it is possible to complete the data transfer between the memory and the peripheral device under the control of the microprocessor in a single bus cycle.

[0007]

1 is a block diagram showing the configuration of an embodiment according to the present invention. Components corresponding to those of the conventional example shown in FIG. 2 are designated by the same reference numerals. In this embodiment, the CPU 1
A buffer circuit 20 is inserted in the portion of the data bus 18 between 0 and the memory 12 and the I / O 14. The buffer circuit 20 has an operation mode of either a data passing state or a blocking state. In the data passing state, there are cases where data is passed from the left side to the right side and cases where data is passed from the right side to the left side. is there. That is, when the DIR terminal of the buffer circuit 20 is at a high level, data can pass from the right side to the left side, and in the opposite case, data can pass from the left side to the right side. Therefore, the CPU 10 causes the buffer circuit 20 and the data bus 18 to pass. Through the memory 12 and I
Data can be exchanged with / O14. When such an operation is performed, there is no difference from the conventional case.

However, when it is desired to transfer data at high speed between the memory 12 and the I / O 14, the CPU 10
Of the buffer circuit 20 via the first address line 22.
The CE terminal is set to the high level, and the buffer circuit 20 is set to the cutoff state. With this setting, the CPU 10
Since the data bus 18 between the memory 12 and the I / O 14 is cut off, the CPU 10, the memory 12 and the I / O 14 are disconnected.
Data is not exchanged with the device 14. At the same time as this state, the logical state of the address strobe signal (\ AS) and the read / write control signal (READ / \ WRITE) is appropriately set to set one of the memory 12 and the I / O 14 to the read state. Then, the other is set to the write state and the address signal is supplied to execute the data transfer.
Then, since the data is directly sent from one of the read states in the memory 12 and the I / O 14 to the other of the write states, it becomes possible to complete the data transfer in a single bus cycle, which is a comparison with the conventional one. As a result, the data transfer time is significantly reduced.

The logic control circuit 26 is necessary to execute the above-mentioned operation. The logic control circuit 26 sets one of the memory 12 and the I / O 14 in a read state in accordance with the first and second address lines 22 and 24, the read / write control signal, and the address strobe signal. And a circuit for setting the other to the written state. It is obvious to those skilled in the art that the specific circuit configuration is not limited to the circuit shown in FIG.

First, when data is transferred from the memory 12 to the I / O 14, the memory 12 is set to the read state,
Set the I / O 14 to the write state. In this case, CPU1
0 sets the read / write control signal (READ / \ WRITE) to high level, sets the first address line 22 to high level, and sets the address strobe signal (\ AS) to low level, respectively. As a result, the buffer circuit 20 is in the cutoff state, and the chip enable terminals (\ C) of the memory 12 and the I / O 14 are irrespective of the logical state of the second address line 24.
E) is at a low level and is in an operable state. Further, the memory 12 is in a read state (high level), and the other I /
O14 is in a written state (low level). Therefore, data is transferred from the memory 12 to the I / O 14 according to the address signal supplied via the address bus 19.

Next, when data is directly transferred from the I / O 14 to the memory 12, the I / O 14 is set to the read state and the memory 12 is set to the write state. In this case, CP
U10 sets the read / write control signal to the low level, the first address line to the high level, and sets the address strobe signal (\
AS) to low level. Then, the buffer circuit 20
Is a cut-off state, and the terminal \ CE of the memory 12 and the I / O 14 is at a low level regardless of the logic state of the second address line 24, and the operation is possible. In addition, the memory 12
Becomes a write state (low level) and the I / O 14 becomes a read state (high level).
The data designated by the address signal is directly transferred to.

According to the apparatus of the present invention described above, the memory 12
And I / O 14 can complete the transfer of data during a single bus cycle. At this time, since the data to be transferred can be arbitrarily designated by the CPU 10 via the address bus 19, arbitrary data can be transferred. This is something that conventional DMA technology cannot do.

The second address line 24 is not relevant to the operation of the invention described above. When the buffer circuit 20 is set to the data passable state, the chip enable terminal (\ CE) of either the memory 12 or the I / O 14 is set to the low level according to the logical state of the second address line 24,
The other is set to a high level and only one is set to be operable. This is the same operation as the conventional case, and the CPU 10 and the memory 12 or the I or
Data can be exchanged with / O14. Although the configuration and operation of the logic circuit 26 can be easily understood by those skilled in the art, the operation of this conventional case will be described below.
The first address line 22 is at the low level and the buffer circuit 20
Can pass data. When the second address line 24 is at a high level and the address strobe (\ AS) is at a low level, the memory 12 is enabled and the I / O 14 is disabled. At this time, read the memory 12
When it is set to (high level), the buffer circuit 20 can pass data from the right side to the left side, and the data from the memory 12 is C
It is transferred to the PU 20. On the contrary, when the read / write control signal is set to the low level, the memory 12 is in the write state, and the buffer circuit 20 can pass the data from left to right.
Data is written from 20 to the memory 12. Next, the second address line 24 is set to the low level, \ AS is set to the low level, and the memory 12 is disabled and the I / O 14 is enabled. At this time, if the read / write control signal is set to the high level, the I / O 14 becomes the read state, and the I / O 1
4 sends data to the CPU 10 via the buffer circuit 20, and when the read / write control signal is set to low level, I / O
14 is in the write state, and data is sent from the CPU 10 to the I / O 14.

The preferred embodiment of the present invention has been described above.
It will be apparent to those skilled in the art that the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the gist of the present invention.

[0015]

By providing a buffer circuit, data transfer between a memory and a peripheral device can be completed in a single bus cycle under the control of the microprocessor, and the data to be transferred can be any data. It can be one that exists at the address. Therefore, it is possible to significantly reduce the transfer time of data at an arbitrary address.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional circuit.

[Explanation of symbols]

 10 Micro Processor (CPU) 12 Memory 14 Peripheral Device (I / O) 20 Buffer Circuit 22 First Address Line 24 Second Address Line 26 Logic Control Circuit

Claims (2)

[Claims] 1. A microprocessor controller for interconnecting a microprocessor, a memory, and a peripheral device with an address bus and a data bus, and controlling data transfer by the microprocessor. Inserted into the data bus between the processor and the memory and peripheral device, and in a cutoff state or a connection state between the microprocessor and the memory and peripheral device under the control of the microprocessor. The microprocessor is provided with a buffer circuit which is set to either of the above, and when the buffer means is set to the cutoff state, one of the memory and the peripheral device is set to the read state and the other is set to the write state, and the memory is set. And direct exchange of data between peripheral devices Microprocessor control unit for. 2. When the microprocessor sets the buffer circuit to the cutoff state, one of the memory and the peripheral device is set to the read state and the other is written according to a control signal from the microprocessor. 2. A microprocessor controller according to claim 1, including a logic control circuit for setting the state.