JPS6488853A - Memory mechanism for high speed arithmetic unit - Google Patents

Memory mechanism for high speed arithmetic unit

Info

Publication number
JPS6488853A
JPS6488853A JP24713487A JP24713487A JPS6488853A JP S6488853 A JPS6488853 A JP S6488853A JP 24713487 A JP24713487 A JP 24713487A JP 24713487 A JP24713487 A JP 24713487A JP S6488853 A JPS6488853 A JP S6488853A
Authority
JP
Japan
Prior art keywords
memories
high speed
cpu
data
fpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24713487A
Other languages
Japanese (ja)
Inventor
Yuusuke Satsuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GE Healthcare Japan Corp
Original Assignee
Yokogawa Medical Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Medical Systems Ltd filed Critical Yokogawa Medical Systems Ltd
Priority to JP24713487A priority Critical patent/JPS6488853A/en
Publication of JPS6488853A publication Critical patent/JPS6488853A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To read data from respective memories to a high speed computing element and to perform arithmetic operation even when a CPU executes a writing and a reading by providing a switch means, etc., between the plural memories and the CPU and between the memories and the high speed computing element. CONSTITUTION:A memory (A)5 and a memory (B)6 respectively store the data from a CPU 1 and supply the data to a high speed computing element FPU 4 to execute arithmetic operation at a high speed. Switches 7 and 8 are inserted between a CPU bus 2 and the memories 5 and 6 and execute the turning-on and off of data input and output between the bus 2 and the memories 5 and 6. Then, switches 9 and 10 execute the turning-on and off of the reading and writing of the data between the memories 5 and 6 and the FPU 4. The memories 5 and 6 are connected through a control register 11 to the CPU 1 or connected to the FPU 4 by changing-over the respective switches. Thus, the respective memories and the FPU 4 can be operated without a rest. Namely, even while the CPU 1 executes the writing and reading, the data can be read from the respective memories and can perform arithmetic operation in the FPU 4.
JP24713487A 1987-09-30 1987-09-30 Memory mechanism for high speed arithmetic unit Pending JPS6488853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24713487A JPS6488853A (en) 1987-09-30 1987-09-30 Memory mechanism for high speed arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24713487A JPS6488853A (en) 1987-09-30 1987-09-30 Memory mechanism for high speed arithmetic unit

Publications (1)

Publication Number Publication Date
JPS6488853A true JPS6488853A (en) 1989-04-03

Family

ID=17158939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24713487A Pending JPS6488853A (en) 1987-09-30 1987-09-30 Memory mechanism for high speed arithmetic unit

Country Status (1)

Country Link
JP (1) JPS6488853A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013136857A1 (en) * 2012-03-13 2015-08-03 日本電気株式会社 Data processing system, semiconductor integrated circuit and control method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374336A (en) * 1976-12-15 1978-07-01 Hitachi Ltd Switching unit
JPS5957358A (en) * 1982-09-27 1984-04-02 Matsushita Electric Ind Co Ltd Shared memory access controlling circuit
JPS61251943A (en) * 1985-04-30 1986-11-08 Yokogawa Medical Syst Ltd Data processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5374336A (en) * 1976-12-15 1978-07-01 Hitachi Ltd Switching unit
JPS5957358A (en) * 1982-09-27 1984-04-02 Matsushita Electric Ind Co Ltd Shared memory access controlling circuit
JPS61251943A (en) * 1985-04-30 1986-11-08 Yokogawa Medical Syst Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013136857A1 (en) * 2012-03-13 2015-08-03 日本電気株式会社 Data processing system, semiconductor integrated circuit and control method thereof

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