JPS57212541A - Operational processor - Google Patents

Operational processor

Info

Publication number
JPS57212541A
JPS57212541A JP9801581A JP9801581A JPS57212541A JP S57212541 A JPS57212541 A JP S57212541A JP 9801581 A JP9801581 A JP 9801581A JP 9801581 A JP9801581 A JP 9801581A JP S57212541 A JPS57212541 A JP S57212541A
Authority
JP
Japan
Prior art keywords
register
cpu
output
operating device
program status
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9801581A
Other languages
Japanese (ja)
Other versions
JPS6119065B2 (en
Inventor
Yasushi Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9801581A priority Critical patent/JPS57212541A/en
Publication of JPS57212541A publication Critical patent/JPS57212541A/en
Publication of JPS6119065B2 publication Critical patent/JPS6119065B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To efficiently move a data between a CPU and an additional operating device, and to elevate a throughput of a device, by providing a register which is capable of independently writing in both the CPU and the additional operating device. CONSTITUTION:When multiplication of a floating point ends, a microprogram writes contents of a program status register 205 in accordance with its operation result, and also sets a selecting and indicating flip-flop 155 (FF155) provided in an execution unit 15 of a CPU 1. An output of the program status register 205 of a floating point operating device 20 is supplied to an input of a selecting circuit 156 through a line 2000. In case when the FF155 is set, the selecting circuit 156 selects an output of the register 205 side, and this output is directly supplied to a logical circuit in the execution unit 15 which requires a value of the program status.
JP9801581A 1981-06-24 1981-06-24 Operational processor Granted JPS57212541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9801581A JPS57212541A (en) 1981-06-24 1981-06-24 Operational processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9801581A JPS57212541A (en) 1981-06-24 1981-06-24 Operational processor

Publications (2)

Publication Number Publication Date
JPS57212541A true JPS57212541A (en) 1982-12-27
JPS6119065B2 JPS6119065B2 (en) 1986-05-15

Family

ID=14207989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9801581A Granted JPS57212541A (en) 1981-06-24 1981-06-24 Operational processor

Country Status (1)

Country Link
JP (1) JPS57212541A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027030A (en) * 1983-07-25 1985-02-12 Hitachi Ltd Microprocessor
JPS60214069A (en) * 1984-04-02 1985-10-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Processing system
US5426742A (en) * 1983-07-25 1995-06-20 Hitachi, Ltd. Microprocessor for supplying branch condition indicating signal in response to execution of conditional branch instruction

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027030A (en) * 1983-07-25 1985-02-12 Hitachi Ltd Microprocessor
US5426742A (en) * 1983-07-25 1995-06-20 Hitachi, Ltd. Microprocessor for supplying branch condition indicating signal in response to execution of conditional branch instruction
JPS60214069A (en) * 1984-04-02 1985-10-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Processing system

Also Published As

Publication number Publication date
JPS6119065B2 (en) 1986-05-15

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