JPS5512570A - Control system for memory element - Google Patents

Control system for memory element

Info

Publication number
JPS5512570A
JPS5512570A JP8544378A JP8544378A JPS5512570A JP S5512570 A JPS5512570 A JP S5512570A JP 8544378 A JP8544378 A JP 8544378A JP 8544378 A JP8544378 A JP 8544378A JP S5512570 A JPS5512570 A JP S5512570A
Authority
JP
Japan
Prior art keywords
signal
memory element
unit
counter
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8544378A
Other languages
Japanese (ja)
Inventor
Tsuguhito Serizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8544378A priority Critical patent/JPS5512570A/en
Publication of JPS5512570A publication Critical patent/JPS5512570A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To enable to use the memory element in which the bit width is determined to the signal having greater bit width, by controlling the memory element according to the output state of counter, in the data processing unit. CONSTITUTION:The unit consists of the latch unit 2 having a plurality of input terminals and holding the input signal, multiplexer 3 receiving the output signal of the unit 2, memory element 1 storing the output signal of the circuit 3, shift register 6 sequentially storing the output signal of the element 1, latch unit 7 selecting and delivering the output depending on the signal from the inverter 11, and counters 4 and 5. Further, the signal stored in the latch unit 2 is stored to the memory element 1 with the signal delivered from the counter 4. Further, the counter 4 performs different count operation according to the state of the control signal.
JP8544378A 1978-07-13 1978-07-13 Control system for memory element Pending JPS5512570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8544378A JPS5512570A (en) 1978-07-13 1978-07-13 Control system for memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8544378A JPS5512570A (en) 1978-07-13 1978-07-13 Control system for memory element

Publications (1)

Publication Number Publication Date
JPS5512570A true JPS5512570A (en) 1980-01-29

Family

ID=13859005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8544378A Pending JPS5512570A (en) 1978-07-13 1978-07-13 Control system for memory element

Country Status (1)

Country Link
JP (1) JPS5512570A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63746A (en) * 1986-06-20 1988-01-05 Fujitsu Ltd Memory access system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63746A (en) * 1986-06-20 1988-01-05 Fujitsu Ltd Memory access system

Similar Documents

Publication Publication Date Title
EP0267612A3 (en) Timer/counter using a register block
JPS5549729A (en) Data transfer system
EP0234038A3 (en) Apparatus for identifying the lru storage unit in a memory
ES458222A1 (en) Common polling logic for input/output interrupt or cycle steal data transfer requests
JPS56166614A (en) Mixing console
JPS5512570A (en) Control system for memory element
JPS56123069A (en) Data processing device
JPS5286746A (en) Pulse count readout control circuit
JPS54818A (en) Signal input device
JPS5577069A (en) Data memory system
JPS5393743A (en) Collective arithmetic unit
JPS57169809A (en) Programmable logic controller
JPS54107629A (en) Key input unit
JPS53135682A (en) Operation state display system
JPS56114026A (en) Data processor
JPS576967A (en) Data transfer system
JPS57178426A (en) Counting device
JPS51144137A (en) Input/output data control unit
JPS5530746A (en) Specification set system for electronic cash register
JPS5793473A (en) Multiplexing convolution product sum calculating device
JPS5671105A (en) Shift register type programmable controller with memory
JPS578845A (en) Indeterminate processing control system
JPS5740800A (en) High-speed readout circuit of sequential storage device
JPS56135252A (en) Computer system for process control
JPS6488853A (en) Memory mechanism for high speed arithmetic unit