JPS5740800A - High-speed readout circuit of sequential storage device - Google Patents

High-speed readout circuit of sequential storage device

Info

Publication number
JPS5740800A
JPS5740800A JP55116602A JP11660280A JPS5740800A JP S5740800 A JPS5740800 A JP S5740800A JP 55116602 A JP55116602 A JP 55116602A JP 11660280 A JP11660280 A JP 11660280A JP S5740800 A JPS5740800 A JP S5740800A
Authority
JP
Japan
Prior art keywords
inputted
storage device
speed readout
readout circuit
sequential storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55116602A
Other languages
Japanese (ja)
Other versions
JPS6143792B2 (en
Inventor
Hisashi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55116602A priority Critical patent/JPS5740800A/en
Publication of JPS5740800A publication Critical patent/JPS5740800A/en
Publication of JPS6143792B2 publication Critical patent/JPS6143792B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To enable high-speed readout operation by freely reading low-operation- speed storage element in parallel. CONSTITUTION:To respective storage elements 21-24, addresses are inputted from corresponding address counters 25-28 at any time, and pieces of information stored in those addresses are inputted to a selecting circuit 31 all the time. The parallel outputs of a counter 29 are inputted as a control signal to a selecting circuit 31 and as the count value of the counter 29 varies, the outputs of the storage elements 21-24 are selected being circulated successively and then outputted as an information signal 33.
JP55116602A 1980-08-22 1980-08-22 High-speed readout circuit of sequential storage device Granted JPS5740800A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55116602A JPS5740800A (en) 1980-08-22 1980-08-22 High-speed readout circuit of sequential storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55116602A JPS5740800A (en) 1980-08-22 1980-08-22 High-speed readout circuit of sequential storage device

Publications (2)

Publication Number Publication Date
JPS5740800A true JPS5740800A (en) 1982-03-06
JPS6143792B2 JPS6143792B2 (en) 1986-09-30

Family

ID=14691214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55116602A Granted JPS5740800A (en) 1980-08-22 1980-08-22 High-speed readout circuit of sequential storage device

Country Status (1)

Country Link
JP (1) JPS5740800A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0546507A2 (en) * 1991-12-09 1993-06-16 Mita Industrial Co., Ltd. FIFO memory control device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0241666A (en) * 1988-07-29 1990-02-09 Matsushita Refrig Co Ltd Transistor inverter device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100941A (en) * 1975-12-31 1977-08-24 Olivetti & Co Spa Device for addressing memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52100941A (en) * 1975-12-31 1977-08-24 Olivetti & Co Spa Device for addressing memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0546507A2 (en) * 1991-12-09 1993-06-16 Mita Industrial Co., Ltd. FIFO memory control device
US5331598A (en) * 1991-12-09 1994-07-19 Tsukasa Matsushita Memory control device

Also Published As

Publication number Publication date
JPS6143792B2 (en) 1986-09-30

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