JPS6116113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction control device in a vector arithmetic processing device that operates on corresponding operands, for example, a plurality of first operands and a plurality of second operands, and particularly relates to an instruction control device in a vector arithmetic processing device that operates on corresponding operands of a plurality of first operands and a plurality of second operands. This relates to an instruction control device that efficiently performs data processing by having multiple stages of arithmetic control management sections that manage processing units and storage control sections, and transferring instruction information to subsequent arithmetic processing management sections in a timely manner. It is.

In a general-purpose computer, one element of data is loaded from memory to a register in the central processing unit, and a second input operand consisting of one element on the register and a third input operand consisting of one element are loaded.
An operation is performed on the input operand to obtain a result operand consisting of one element. An instruction that performs such control is an instruction called a scalar instruction that processes a single element with one instruction.

However, vector arithmetic devices are controlled by vector instructions that process a plurality of elements with one instruction. For example, in a load instruction, as shown in FIG. 1, _a plurality of data a ₁ , a ₂ , _{a 3 ,} .
b ₃ , ......, b _o are loaded into the vector register 5 via the storage control device 3 and main storage control device 2 based on the command of the instruction control device 4, and are calculated by, for example, the following addition instruction. These data are added in the processing unit 6 and A+B=C, that is, a ₁ +b ₁ =
Perform the additions c ₁ , a ₂ + b ₂ = c ₂ , a _o + b _o = c _o , and the resulting multiple addition results c ₁ ,
After setting c ₂ , _{c 3} . In this case, with one addition instruction, the above a ₁ +b ₁ =c ₁ , a ₂ +b ₂ =c ₂ ......a _o + b _o =
A plurality of operations c _o are sequentially performed.

When performing such operations, instructions are generally processed in a pipeline in the field of high-speed computers such as vector arithmetic units. For example, as shown in FIG. 2, one instruction process includes fetching an instruction word (Fetch), decoding it (Decode),
It can be divided into three stages: instruction execution (Execute). Instead of processing these instructions one by one, when the preceding instruction is executing the instruction, the next instruction is decoding the instruction, and the subsequent instruction is decoding the instruction. Let's do it. That is, as shown in Figure 3, when the preceding instruction V ₁ is executing instruction (E), the next instruction V ₂ is decoding the instruction.
Execute (D), and the next instruction V ₃ is command word fetch (F)
Processing is performed using a pipeline processing method in which each stage is processed simultaneously. At this time, multiple cycles are required to execute an instruction, but generally the arithmetic processing unit uses adders and shifters multiple times to execute one scalar instruction, that is, one element at a time, instead of using a pipeline structure. It is now possible to perform the following processing. Therefore, the next instruction cannot be executed until the instruction execution (E) of one preceding instruction is completed.

However, if high-speed calculations are not required, the method described above will not cause much of a problem, but if vector instructions are to be processed at extremely high speeds, the calculation processing section should be constructed in a pipeline structure, and the processing of the preceding element is Before the arithmetic process is completed, it is necessary to input the subsequent element and start the arithmetic process.

For example, when performing addition, the instruction execution in the arithmetic processing unit involves reading data (Read), comparing the exponents of both operands (Compare), shifting to match the exponents (Aligment), and adding (Add).
Shift for normalization after operation (Post Shift),
Data writing is divided into six stages. Here and above you need to use a shifter. General-purpose computers use the same shifter, but this slows down the calculation speed, so in order to process vector instructions at ultra-high speed, the calculation processing unit naturally has a pipeline structure, and for this purpose, the above and Separate shifters will be provided for each. Therefore, when a vector instruction that processes multiple elements in one instruction is processed by a pipeline arithmetic unit, the final stage of write processing is performed for the most preceding element _e1 , as shown in Figure 4A. When the next element e ₂ is postshifted, element e ₃ is added, element e ₄ is aligned, element e ₅ is compared exponentially, and element A read process is performed for e ₆ , and each of these processes is sequentially performed for element e _o . As a result, when addition is performed using a vector instruction, a process represented by a parallelogram as shown in FIG. 4B is performed for each instruction.

Furthermore, when a load instruction is used to load data from the main storage device 1 into the vector register 5 shown in FIG. 1, pipeline processing similar to that for the addition instruction is performed in the storage control device 3.

However, when an arithmetic processing unit with such a pipeline structure continuously processes vector instructions V ₁ and V ₂ (for example, both are addition instructions), the instructions in the instruction control device and the control pipeline structure , processing for these vector instructions V ₁ and V ₂ is performed in the state shown in FIG.

Now, in the instruction control device, reading of the instruction word F ₁ is performed in accordance with the instruction V ₁ , and when it is decoded D ₁ , reading of the instruction word F ₂ is performed in response to the instruction V ₂ . When the arithmetic processing unit executes the instruction _E1 of the instruction _V1 , the instruction control device decodes the instruction word _D2 of the instruction _V2 . However, as shown in FIG. 5, this instruction execution E ₁ ends when the write process for the last element e ₈ is performed at time t ₂ , and then instruction execution E ₂ for the instruction V ₂ is performed. Therefore, from time t ₁ when the data read process for the last element e ₈ is completed in the instruction V ₁ in the arithmetic processing unit to time t ₂ when the data read process for the first element e ₁ ' starts in the instruction V ₂ . The period of ₂ -t ₁ =t ₀ is a so-called idle period in which the data read processing circuit is not given any job from the instruction control device even though it is possible to execute a job. Similarly, each circuit for index comparison processing, alignment processing, addition processing, postshift processing, and write processing each has an idle period of period t ₀ ,
As a result, there is an idle period as shown by the shaded area L in FIG. As described above, due to the limitations of the pipeline structure of the instruction control device, the arithmetic processing unit is unable to perform read processing for instruction V ₂ even though it is possible to do so once the read stage for instruction V ₁ has been completed. As a result, there is a drawback that the above-mentioned idle period occurs, which poses a problem in terms of high-speed processing.

Therefore, as shown in FIG. 6, it is conceivable to manage the instruction execution stage of the instruction pipeline by dividing it into two, for example, into a data read stage and a subsequent stage. In this case, the instruction control device is provided with a first instruction execution register and a second instruction execution register,
The instruction V ₁ is initially controlled by the instruction set in the first instruction execution register, and then the instruction V ₁
An instruction is set in the second instruction execution register at time _T1 when read processing for all elements is completed, and write processing up to time _T2 is managed based on the instruction set in the second instruction execution register. It will be done. However, in this case, during the period from time T ₀ when the write process for the first element is started to the above-mentioned time T ₁ , the first instruction execution register must manage the control for the read process and the control for the write process. Another problem is that this makes the control complex.

Therefore, in order to solve the above-mentioned problem, the present invention improves the pipeline structure of an instruction control device by:
The instruction execution stage is divided into multiple stages to enable high-speed processing of the arithmetic control execution, and the instruction information necessary for the arithmetic control execution is calculated based on the control signal transmitted from the arithmetic processing means or storage data processing means. It is an object of the present invention to provide an instruction control device in which a control execution instruction is held in a control execution instruction holding means. In a data processing device for processing vector instructions, the data processing device includes a stored data processing means such as a means or a storage control device, and an instruction control device for controlling data processing in the arithmetic processing means or the stored data processing means, and the instruction control device performs calculations. A plurality of arithmetic control execution instruction holding means for holding arithmetic control execution instruction information are provided in the arithmetic control execution stage which is equipped with a stage register for holding instruction information, a stage setting circuit, an instruction decoder, etc. The method is characterized in that the arithmetic control execution command is held in the arithmetic control execution command holding means based on a control signal transmitted from the arithmetic processing means or the storage data processing means.

An embodiment of the present invention will be described below with reference to FIGS. 7 and 8.

FIG. 7 is a configuration of one embodiment of the present invention, and FIG. 8 is an explanatory diagram of its operation.

In the figure, 7 is an ER stage setting circuit, 8 is an ER stage register, 9 is an EW stage setting circuit, 10
1 is an EW stage register, 11 and 12 are decoders, 13 is a vector register, and 14 is an arithmetic processing unit.

The ER stage register 8 and the EW stage register 10 are stage registers each holding an operation execution instruction, and provide operation execution instruction holding means.

The ER stage setting circuit 7 determines whether the read process can be executed when the instruction is transmitted from the decoder 11 to the arithmetic processing unit 14, and when the read process is possible, receives the instruction from the decoder D and executes the ER stage setting circuit 7. It is transmitted to the stage register 8 and further decoded by the decoder 11, or when it is no longer necessary to hold the instruction set in the ER stage register 8, it is erased or the next new instruction is accepted. It is for controlling.

The EW stage setting circuit 9 sets the command from the ER stage register 8 to the EW stage register 10, and also sets the command from the ER stage register 8 to the EW stage register 10.
When it is no longer necessary to hold an instruction that has been set, it is deleted or the next new instruction is accepted.

The decoder 11 decodes the instructions set in the EW stage register 8, and in particular decodes parts other than write processing instructions.

The decoder 12 decodes the instructions set in the EW stage register 10, and in particular decodes the write processing instruction portion.

The vector register 13 is a vector register that temporarily sets a plurality of elements necessary for a vector operation, or is temporarily set by a write instruction decoded by the decoder 12 for the result processed by the arithmetic processing unit 14. be.

The arithmetic processing unit 14 uses the elements set in the vector register 13 to process the decoder 1.
It has a function of executing the arithmetic processing decoded by No. 1 and transmitting the result to the EW stage setting circuit 9 when the state of writing the arithmetic result is reached.

Now, as shown in FIG. 8, when instructions V ₁ and V ₂ are to be executed, instruction V ₁ is first transmitted to the instruction control device. This causes the instruction controller to perform an instruction fetch _F1 and then decode it _D1 . Then, at time _t0 ', when the ER stage setting circuit 7 determines that the instruction based on the decode _D1 can be executed in the arithmetic processing section 14, it sets the instruction transmitted from the decoder in the ER stage register 8.

The instruction set in the ER stage register 8 is further decoded by the decoder 11.
Based on this, the decoder 11 transmits an element read request instruction and an element processing request instruction (for example, an addition processing instruction) to the vector register 13 and the arithmetic processing section 14. As a result, the elements e ₁ set in the vector register 13,
e ₂ , e ₃ , ...... are read out sequentially (element e ₁ consists of operands a ₁ and b ₁ , element e ₂ consists of a ₂ and b ₂ , element e ₃ consists of operands a ₃ and b ₃ ...... ),
A comparison of the exponents of both operands, a shift for adjusting the exponents, an addition, and a shift for normalization after the addition are performed. and the first element e ₁
When the above-mentioned processes have been performed on the EW stage setting circuit 9 and the calculation result is set in the vector register 13, the calculation processing section 14 sets the EW stage setting circuit 9.
transmits an instruction signal to the When the EW stage setting circuit 9 receives this instruction signal, it sets the command set in the ER stage register 8 into the EW stage register 10. As a result, the decoder 12 decodes the write processing command portion and transmits the write request command to the vector register 13. As a result, at time t ₁ ′, the above element
The calculation results for e ₁ , e ₂ ...... are sent to the calculation processing unit 14.
From there, the write stage processing is performed, which is set in the vector register 13.

On the other hand, the above elements e ₁ , e ₂ , e ₃ ... by instruction V ₁
When the readout stage of ... ends at time _t2 ', the vector register 13 transfers it to the ER stage setting circuit 7.
Report to. As a result, the ER stage setting circuit 7
This time, the instruction _V2 transmitted via the decoder D is set in the ER stage register 8, and the read stage processing based on this is started.

Further, the write stage processing started from time t ₁ ' ends at time t ₃ ', but at this time the arithmetic processing unit 14 reaches the stage where the arithmetic result should be set in the vector register 13, so a signal instructing this is sent. of
It is transmitted to the EW stage setting circuit 9. As a result, the EW stage setting circuit 9 now outputs the instruction related to instruction V ₂ set in the ER stage register 8.
The EW stage register 10 is set, and the write stage processing for instruction _V2 is started.
The same control processing as that for instruction V ₁ is performed for instruction V ₂ , and at time t ₄ ', the read stage processing of instruction V ₂ is completed, and at time t ₅ ', the write stage processing of instruction V ₂ is completed. will end.

The same instruction is set in the ER stage register ₈ and the EW stage register 10 from time _t1 ' to _t2 ' for the processing of the instruction V1, and from time _t3 ' to _t4 for the processing of the instruction _V2 . ’, the above ER stage register 8 and
The same instruction is set in the EW stage register 10. As a result, when decoding the instruction set in the ER stage register 8, it is only necessary to decode only the part of the EW stage register 10 other than the part decoded by the decoder 12, and the EW stage register 10 only needs to decode the part of the write instruction. Since it is only necessary to decode these decodes, these decodes can be managed separately, making the decoding and control very simple, and the idle period shown in FIG. 5 can be used for arithmetic processing. Moreover, since the control of the write stage can be started based on instructions from the arithmetic processing section,
For example, if there is no 0 at the beginning of the operation result and no shift is required for normalization after addition, the above instructions can be used in the previous stage without going through the shift stage for normalization. Therefore, the calculation process can be made faster compared to control that necessarily requires going through a shift stage for normalization.

Another embodiment of the present invention will be described based on FIG.

In a data processing system in which the main storage device 1 is commonly used by the central processing unit 20, the channel processor 21, etc., the central processing unit 20 currently reads data necessary for data processing from the main storage device 1 and stores it in the vector register 5. If there is a prior access from the channel processor 21, the main memory controller 2
The access request from 0 is temporarily put on standby. When the preceding access is completed, an access request is made to the central processing unit 20. At this time, the load instruction processing unit 3-1 in the storage control device 3 decodes the instruction transmitted from the instruction control processing 4, performs address calculation, issues an access request signal to the main memory control device 2, and sends the main memory When an access permission signal is received from the control device 2, access to the main storage device 1 is started. The read data is then transmitted from the main storage device 1 to the storage control device 3 via the main storage control device 2.
When setting the data in the vector register 5, the load instruction processing section 3-1 transmits a timing instruction signal instructing the instruction control device 4 to write data. This timing instruction signal is applied to the EW stage setting circuit in the instruction control device 4, the instruction is set in the EW stage register, and the write stage processing for the vector register 5 is started. According to this, even if the timing of the write stage to the vector register after an access request is uncertain depending on the type of conditions, such as when reading data from the main memory in a multiprocessor system, instructions from the processing unit can be used. Since the write process is performed based on

As described above, according to the present invention, the management means for the instruction execution stage in the instruction control device is configured in a pipeline structure so that instruction information can be held in an overlapping manner, and the instruction execution stage from the control processing section is Since the instruction information is transmitted using the instruction timing signal, it is possible to perform optimal data processing according to the actual control processing state.

Although the above explanation deals with an addition instruction and reading data from the main memory, the present invention is of course not limited to these.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a vector calculation device, Figures 2 to 4 are illustrations of its operation, Figure 5 is an illustration of the problems of the conventional vector calculation device, and Figure 6 is a diagram that has improved the above problems. FIG. 7 is an explanatory diagram of an embodiment of the present invention, FIG. 8 is an explanatory diagram of the operation, and FIG. 9 is another embodiment of the present invention. In the figure, 1 is a main storage device, 2 is a main storage control device,
3 is a storage control device, 4 is an instruction control device, 5 is a vector register, 6 is an arithmetic processing unit, 7 is an ER stage setting circuit, 8 is an ER stage register, 9 is a
EW stage setting circuit, 10 is an EW stage register, 11 and 12 are decoders, 13 is a vector register, 14 is an arithmetic processing unit, 20 is a central processing unit, and 21 is a channel processor.

Claims (1)

[Scope of Claims] 1. A data processing device that processes vector instructions and includes an arithmetic processing means or stored data processing means having a pipeline structure and an instruction control device that controls data processing in the arithmetic processing means or stored data processing means. A plurality of arithmetic control execution instruction holding means for holding arithmetic control execution instruction information is provided in an arithmetic control execution stage that includes a stage register, a stage setting circuit, an instruction decoder, etc. for holding arithmetic execution instruction information of the instruction control device. and dividing the arithmetic control execution stage into a plurality of stages, and causing the arithmetic control execution command holding means to hold the arithmetic control execution command based on a control signal transmitted from the arithmetic processing means or the storage data processing means. A command control device characterized by: