JPS6022247A - Micro instruction control system - Google Patents

Abstract

PURPOSE:To maximize the arithmetic performance of a processing section by giving an instruction stored in an instruction storage and reproducing section to an instruction register, reading a constant data from a control storage section and processing it sequentially to decrease the processing cycle of execution of instruction. CONSTITUTION:An FIFO20 is provided as the instruction storage and reproducing section to a control system, a micro instruction of an instruction register 6 is stored and the instruction stored corresponding to the output of an instruction decoder 7 is outputed. Further, a selector 30 is provided between a control storage section 2 and the register 6 to select the output of the FIFO20 and the register 6. Further, a stack 40 is connected to a micro program 1 and an output of a constant address register 5 is fed to the storage section 2 via a selector 4. Then the instruction stored in the FIFO20 is given to the register 6 and also the constant data is read sequentially from the storage section 2 and added to an arithmetic section 10 to decrease the processing cycle of execution of instruction by an arithmetic and logic unit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement of an optimal micro-instruction control system when operations of the same type are repeatedly executed.

[Technical background of the invention and its problems]

In recent years, with the development of microfabrication technology (LSI technology), various types of microprocessors have been developed1.The cholera microprocessor has an external program storage system for versatility and flexibility for software changes. Mesori is often provided.

In this case, from the point of view of effective use of memory and the limitation on the number of pins of an LSI, a method is widely adopted in which a microinstruction and constant data referred to when executing the microinstruction are sequentially read in a time-sharing manner.

FIG. 1 is a block diagram of a trap microinstruction control device employing the above method. In the figure, 1 indicates a micro program counter (hereinafter referred to as MPC), and this MPCl
An address for reading a microinstruction in the control memory unit (hereinafter referred to as CM) 2 is stored in . This address is sent to 0M2 via the selector 4 when the output signal “SEL” of the control circuit (hereinafter referred to as C0NT) 3 is “1”.
given to. Further, the constant data address register (hereinafter referred to as CAR) 5 stores an address corresponding to the constant data in 0M2, and when the output signal SEL of C0NT3 is "0", the address in CAR5 is
Synchronized with the rise of the output signal "CLK" of C0NT3, which is given to 0M2 via selector 4,
MPCI is counted up and at the same time, the microinstruction read from 0M2 is set in the instruction register (hereinafter referred to as IR) 6. Also, when the output signal "SEL" of C0NT3 is rOJ, The constant data obtained is given from 0M2 to an arithmetic unit (hereinafter referred to as PROC) 1o.

In this embodiment, PIOCIO is a multiplier (hereinafter MPY).
) 11, an arithmetic logic unit (hereinafter referred to as ALU) 12, an accumulator (hereinafter referred to as ACC) 13,
A RAM address register (hereinafter referred to as RAR) 14,
It consists of a data RAM (hereinafter simply referred to as RAM) 15. Reference numerals 16 and 17 indicate buffer registers (hereinafter referred to as XR and YR, respectively) that store data to be provided to MPYII.

The constant data read from 0M2 is PR, 0CIO
The data in RAM 15 read out by the address output from RAR 14 is set in Y R17, and these data are stored in M
Multiplied by P Y 11. The resulting data is
The output of ACC13 is set to the other input of ALU12, and the output of ACC13 is set to the other input of ALU12.
In step 2, addition or subtraction of these data is performed.

This result is set in ACC13 again.

The PROC 10 configured in this way is, for example, aL
f, coefficient data, xLt variables as %, X, aLX
It is suitable for executing the product-sum operation represented by XL. This equation is a general form of a fixed coefficient digital transversal filter and is often used in the field of digital signal processing.

Further, numeral 7 indicates an instruction decoder (hereinafter referred to as DEC), and this DEC7 decodes the output of XR6 and supplies it to the output 2CONT3 and other parts to control operations.

Further, CLOCK is a master clock given to C0NT3.

The operation of the microinstruction control device configured as above will be explained.

First, when executing an instruction that does not refer to constant data, as shown in FIG.
" is the output of CLOCK as it is. This "CLK" is given to MPCl and XR6. Also, C0NT3 keeps the output signal "8EL" at "1".

As a result, the outputs of MP and C1 are applied to 0M2, and the output of 0M2 is successively set to XR6. Also,"
CLK" rises), MPCl counts up 7 by 1, so microinstructions with consecutive addresses are set one after another in IfL6, such as I11■2, and so on, and are output to DEC7. and this microinstruction is executed.

FIG. 3 is a diagram showing the above operation divided into machine cycles. In the first cycle, an instruction fetch is performed for microinstruction (1), and in the second cycle, its execution is performed. Indicates that the That is, the second
In the th cycle, PROC10 is operated (OP),
MPcl is counted up by "1". At the same time, the next microinstruction I2 is output from 0M2.

On the other hand, when executing an instruction that refers to constant data,
As shown in Figure 4, in the X*th cycle, the microinstruction I
! is fetched and set to XR6. As a result, in the second cycle, microinstruction (1) is decoded in DFiC7, and its output is given to C0NT3. C0NT3 detects that the microinstruction Is is an instruction that refers to constant data, and outputs the output signal 5.
F3L'i is changed from "1" to "0". So, constant day! Fetching is started, and constant data is set in the XR16 at the rear end of this second cycle. Now that the data necessary for the operation has been prepared, microinstruction 15 is executed in the third cycle. In this third cycle, as can be seen from FIG. 4, the contents of MPC'l and IR6 are held by the output signal of C0NT3.

FIG. 5 is a diagram illustrating the above operation divided into machine cycles. Here again, although the microinstruction is fetched in the first cycle, its execution requires two cycles, the second and third. That is, in the second cycle, since constant data C is being fetched, PROCIO is inactive (NOP), and it is not until the third cycle that PROCIO becomes operational (OPIO). ).

In a microinstruction control device operating in this way, 1.
When Σ0LxL is executed, its operation changes as shown in FIG. 6 for each machine cycle (cy-mi, 2, . . . in the figure).

Here, microinstruction 11.12 is as follows.

In this way, microinstructions ■1, ■! , . . . are instructions having similar contents. However, its execution always requires two cycles. That is, as is clear from FIG. 5, the microinstruction 11 is executed in the second and third cycles, and the microinstruction I2 is executed in the fourth and fifth cycles (・・・・・・・・・
(Omitted)...The microinstruction IL is executed in the 1+2nd and λ+3rd cycles.

In this way, in the conventional microinstruction control method, it always takes two cycles to execute an instruction that refers to constant data.
There was a drawback that the performance of PROCIO (operation unit) could not be fully utilized.

On the other hand, for the calculation of Σ9XL, it is connected to a loop counter (hereinafter referred to as LPG) 8'1CONT3 as shown by the broken line in FIG. r, jJTh is set in this LP01, and this is counted down by "1" every time execution of one microinstruction is completed.

CON T 3 O output signal “8 BL” and “cLK”
'' is held at "0" until LP01 becomes "0".

In this way, as shown in FIG. 7, the microinstruction Is is fetched in the first cycle, the 7-etch of constant data O1 is carried out in the second cycle, and P is fetched in the third cycle. Calculations are performed in the ROC 10. Further, in the third cycle, since the output signals SEL and CLK of C0NT3 are kept at [OJK, constant data Ol is fetched. Below, in each cycle,
1 constant data 0, C4, . Therefore, as is clear from the comparison with FIG.
. . . can be omitted, so that unnecessary processing time can be eliminated.

However, in this case, although it is effective for repeating loops of a single instruction, it is not compatible with repeating loops of multiple instructions, such as a cascade connection of second-order recursive filters, and processing performance is reduced. Not enough.

[Purpose of the invention]

The present invention was developed in view of the drawbacks of the conventional method, and its purpose is to eliminate constant data reference instructions that require two cycles to execute, even in the case of a repeat loop of multiple instructions. , can be practically processed in one cycle,
An object of the present invention is to provide a microinstruction control method that can maximize the arithmetic performance of an arithmetic processing unit.

[Summary of the invention]

Therefore, the present invention provides an instruction storage/reproduction unit that can store and read a predetermined amount of microinstructions, and selectively outputs either the output of the control storage unit or the output of the instruction storage/reproduction unit to the instruction register. In the first process, microinstructions and constant data are read out from the control storage section to the instruction register and executed, and only the microinstructions read out in this operation are sent to the instruction storage reproducing section. Write sequentially to the second
In the subsequent processing, the microinstruction stored in this instruction storage/reproduction unit is given to the instruction register, and
The above object is achieved by reading constant data from the control storage section and sequentially executing processing.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 8 is a block diagram of a microinstruction control device to which the present invention is applied, and members having the same reference numerals as those in FIG. 1 are the same components. In this device, an F I F O (First In First
Out ) 20 is provided so that the microinstruction set in In2 can be stored, and the stored microinstruction is output in response to the output of the DBC 7. In addition, a selector (9) is provided between 0M2 and In2, and II? , 6 has 0M2 output, FiFO
20 outputs 1. One of the outputs of In2 is selected and output. Since CLOCK is input to In2 and the contents of In2 are updated at its startup, the output of IFL6 is introduced to the selector 30. Therefore, in the same way as in FIG.
If you adopt a method that limits the content update of In2, there is no need to introduce it to all output selectors 30 of In2 (0 or 1M).
A stack (hereinafter referred to as 5TACK) 40 is connected to the CI, and the address of the next microinstruction is stored in advance in the 5TACK 40.

Furthermore, the DEC7 inputs the MPCI control signal (see “C” in Figure 1).
LK") and directly to In2, CLOCK-
ft, so the element corresponding to C0NT3 in FIG. 1 is unnecessary.

FIG. 9 is a block diagram of an embodiment of the FIFO 20.

In the figure, reference numeral 21 indicates a RAM having a predetermined capacity for storing microinstructions. A microinstruction is applied to this RAM 21 from In2 to its D terminal. At this time, the DIimC7 RAM write enable signal TLW
E is given as "1", and the microinstruction is stored at the address indicated by the write counter 22. At other times, the microinstruction at the address indicated by the read counter 23 is output from the Q terminal of the RAM 21 and reaches the selector 30.

Here, the write counter 22 and the read counter are constructed of presettable down counters, and are controlled by load enable signals siw, 51R, and count enable signals 52W, 52R.

The load enable signal 51W and count enable signal 52W are output from the DBC7. The load enable signal 51R is an output generated by an OR gate between the load enable signal 51W and the output of the first zero detection circuit arm that detects that the output of the read counter is zero. The count enable signal 52R is the write counter 2
This is the output of the second zero detection circuit that detects that the second output is zero. Further, the number of writes is set to the write counter 22 and read counter path from the DBC 7 via the buffer 27. The buffer 127 is given an N load enable signal 51W, and this signal is set to "1".
When , the buffer 27 passes the contents and the above signal is "
0'', the buffer 12'7 latches the input.

Therefore, the buffer 127 receives latched data once, when the read counter is set to zero and the output of the first zero detection circuit is set to "1" (a microinstruction is executed in one loop). In particular, it has the role of loading the read counter.

The operation of the apparatus configured as described above when performing the same process as the first equation in the process untH(end) when second-order recursive filters are connected in cascade will be described.

If the above processing is converted into microinstructions, the result will be as follows, for example.

11: Set the number of loops in LPCg and store it in the address ft8 T ACK 40 of the next instruction.

(Inform DEC7 that the next command and subsequent instructions are loop processing → permission to write to FIFO20) I2: Multiply a by XL and set in AOO13.

After that, 0AR5 and RAR14 are each incremented by (+1).

Engineering! bz,! :)' Multiply by A, add with the contents of AOC113, and set the result back to A0013.

After that, 0AR5 and RA R14 are each increased by (+1).

I4: Store the contents of AOO13 to Z (RAM).

Check the value of LPCg and if it is "0", end the process, "0"
If not, set LPCg to (-1) and set the contents of 8TAOK40 set in M and POI with l.

Of these, 3 instructions of process
Set (=3-=1).

This command is necessary.

That is, if this is shown in a flowchart, as shown in FIG. 10, in step 101, the loop count is set in LPCg and stored in the address QSTACK40 of the next instruction.

This step 101 corresponds to the above microinstruction. Next, the process proceeds to step 102, where processing ("""b xb
+bL'ri, s/-=L + 1) Do 1.

This corresponds to microinstruction b, Is. Next, the process proceeds to step 103, and it is checked whether the content of LPCg is "0" or not. If it is "0", the process is terminated, and if it is not "0", LPC8ftr-IJ is performed and further 8'l 'ACK4
By jumping to the address indicated by 0, the process returns to step 102 again. Here, step 10 within the dashed line
3 and step 104 correspond to microinstruction I4. In this way, loop processing is executed.

When this is executed with the apparatus shown in FIG. 8, each part changes as shown in FIG. 11 every machine cycle.

First, microinstruction Io is executed. This microinstruction is a process similar to initialization, for example,
Initially, the microinstruction Io at the address indicated by MPCI is 0M.
2 and set to IR,6. In the first cycle, by executing the microinstruction Io, the DEC 7 outputs the write count (-2) and the load enable signal 51W (-rl J ''). The number of writes is set in the n1 read counter 23, the load enable signal 51W is set to "0", and the buffer I
The number of writes is also latched. For this, DBC
Inside 7, necessary data is set in PIF020, and it is stored that it is ready for loop processing. At the same time, the microinstruction Is is fetched, output from 0M2, and set into IR6 via selector 30.

Next, in the second cycle, MPCI is counted up [U] and microinstruction 11 is executed and microinstruction I
! is fetched. In other words, LPCg has “3
” is set, and 5TACK40 contains the microinstruction I.
The address of FIFO 20 is stored, and the DEC 8 is informed that the next microinstruction and subsequent steps are loop processing.
, the count enable signal 52W is given as "1", and Rwn also becomes active.

Next, in the third cycle, the microinstruction is executed, the constant data is fetched, and the microinstruction l! is sent to the FIFO 20. is written. That is, the DEC7 microinstruction I! is decoded and found to be an instruction that refers to constant data.

In PROCIQ, the constant data is set to XR16, and the intuition is set from R, A M 15 to YR17, but no actual calculation is performed.1 Also, the selector 30 selects the output of In2, and the micro Instruction 12 is set. On the other hand, in FIFO20, '
Since BJWE is active, the microinstruction I-, which is the output of In2, is written to the address output by the write counter 22 (W in FIG. 11 is the write e,
(R means read, respectively). When the kneeling is finished and the count enable signal 52W becomes rOJ, the write counter 22 counts down and changes from "2" to "1".
”. In the 44th cycle, microinstruction 12
The second half of the execution is performed. That is, an arithmetic operation is performed on PxO to obtain the multiplication result aoXO, and CAR, 5, and RAR14 are each counted up by 1, and addresses corresponding to bo and yo are created.

Also, microinstruction I3 is fetched.

In the fifth cycle, the first half of the execution of the microinstruction Is is performed. The selector (9) selects the output of In2, and microinstruction 11 is set in In2. On the other hand, in the fourth cycle, the count enable signal 52W is set to "1" and RWE is activated, so the microinstruction 11 controls the R and AM of F'IFO20.
2i. The write counter 22 outputs the storage address at this time.

When writing of the microinstruction 11 is completed, the count enable signal 52W is set to "0", and the write counter 2
2 is counted down and becomes "0" from rlJ. Then, the second zero detection circuit 26 detects "0" and outputs the count enable signal 52Ri "xJ. As a result, the read counter command is enabled to perform counting operation)," and , the count enable signal 52R is DE
C7, indicating that the next instruction is the final instruction of loop processing.

In the sixth cycle, the second half of the execution of the microinstruction In is performed. So, in j5, PROCIO, a multiplication bo yo is performed, this result is added to the data at) Xo in AC013, and this result is set in person CCl3. After this, CAR5, R, and AR14 are counted up by n'', and addresses corresponding to al and xt are created. Additionally, the microinstruction 14 is fetched.

In the seventh cycle, microinstruction I4 is executed. ACC13 contents aL1XD+ bo yo RA
Store in M15. At the same time, the count enable signal 52W is set to "1" in the sixth cycle, so the microinstruction (4) is stored at the address zero output by the write counter 22 in the RAM 2i.

Further, in the sixth cycle, the DEC 7 receives the count enable signal 5zRiroj and is informed that this is the final instruction of the loop processing, so it controls the selector 30, selects the output of the FIFO 20, and inputs the IR
Set to 6. At this time, the read counter n is “2”.
”, correspondingly, 12 microinstructions are read out from the RAM 21. Thereafter, the DEC 7 supplies the read clock to the read counter cram school and counts down the read counter 23 by "1".

That is, in this cycle, the microinstruction I4 is written into the FIFO 20 and the microinstruction I3 is read out in parallel.

After this, the content of LP01 becomes "0" υ, and the output of PIFO 20 is set to IR6 via selector 3o until the execution of microinstruction I4 is completed. In the example of Fig. 9, the loop number is more than -, so the 8th
Processing after the th cycle is also performed. In the processing after the 8th cycle, even if the contents of f9TAcK40 are set in MPCl and the count is increased, the DEC7 controls the selector 4 so that it selects the output of CAR5. ing. Therefore, although the operation of the λ4PCI described above may not be necessary, this operation is performed so that the MPCI has the correct contents when the loop processing is completed. Then, in the eighth cycle, al Xl is set to ACC13 by the execution of microinstruction I2, and constant data b1 is
is fetched. Next, in the ninth cycle, by executing the microinstruction Ig, bsys is created, a+X+ + bx 7x is created, and -IA
Set to CC13. Furthermore, in the 10th cycle, microinstruction number 1 is executed and the above operation result is R.
It is set to AM15 and proceeds to the next cycle. In this way, while the microinstruction is being output to the F-engine FO20, the processes corresponding to the third and fourth cycles are executed in the eighth cycle, and the processes corresponding to the third and fourth cycles are executed in the ninth cycle. , the processing corresponding to the 5th and 6th cycles is executed, and the processing corresponding to the 7th cycle is executed in the 10th cycle, so that the microinstruction fetch cycle is unnecessary. only, processing can be made more efficient. Note that in the 11th and 12th cycles, processes corresponding to the 8th and 9th cycles are performed.

In this way, when the loop count +1 is executed, RA
"-a!xL+bL'jJt" is stored in M15.

〔Effect of the invention〕

As described above, according to the present invention, even an instruction that needs to refer to constant data can be processed in one cycle. Furthermore, the present invention is capable of not only repeating loop processing of a single instruction but also repeating loop processing of multiple instructions.

That is, in the conventional example, microinstructions 11 to I4 require two cycles for microinstructions h and In, and one cycle for microinstruction I4, so 5n cycles are required for n loop processing. However, in the present invention,
In the second and subsequent loops, the microinstructions Is and Ig can also be executed in one cycle, so the total number is (3n+2)
It's a cycle. It can be seen that if nf is large, it can be processed using the conventional cycle.

In addition, in the embodiment, the processing speed was improved by 40% because two of the microinstructions 12 to N4 needed to refer to constant data, but all microinstructions need to refer to constant data. In some cases, processing speed is improved by 50%.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a microinstruction control device that employs a conventional microinstruction control method, Fig. 2 is a timing chart of an operation using microinstructions that do not refer to constant data of the device in Fig. Figure 4 is a timing chart of the operation of the device shown in Figure 1 by a microinstruction that refers to constant data. Figure 1 is a diagram showing the operation by a microinstruction that refers to constant data of the device in each machine cycle, and Figure 6 is a diagram showing the operation in each machine cycle when b = 1 when processing ΣOL XL with the device in Figure 1. Figure 7 shows the operation for each machine cycle when processing similar to Figure 6 is performed using another conventional microinstruction control device, and Figure 8 shows a microcontroller using the method of the present invention. A block diagram of the instruction control device, FIG. 9 is a block diagram of the main part of FIG. 8, FIG. 10 is a flowchart of row 5 processing in the device of FIG. 8, and FIG. FIG. 3 is a diagram showing the operation performed by the apparatus for each machine cycle. 1... Micro program counter 2... Control storage unit 3... Control circuit 4.30...
Selector 5...constant data address register 6...instruction register 7..., instruction decoder 8...
Loop counter 10...Arithmetic unit 20...F'IFO
(Instruction storage/reproduction unit) 21-RAM 22...Write counter 23...Read counter 24...First zero detection circuit 25...OR gate 26...Second zero detection circuit agent Patent attorney Book 1) Takashi

Claims (1)

[Claims] Microinstructions and constant data used when executing microinstructions are placed in the control memory so that the addresses where each data is stored do not overlap, and this data is read out continuously in a time-sharing operation and processed. In a micro-instruction control method for executing a micro-instruction, an instruction storage and reproducing section capable of storing and reading a predetermined amount of micro-instructions, and an instruction register having an output of the control storage section and an output of the instruction storage and reproducing section. and a selector for selectively outputting one of them, and in the first process, the microinstruction and constant data are read from the control storage section to the instruction register and executed, and only the microinstruction read in the operation is executed. are sequentially written into the instruction storage and reproduction section,
In the second and subsequent processes, the microinstruction stored in the instruction storage reproducing unit is given to the instruction register, constant data is read from the control storage unit, and the processes are sequentially executed. Microinstruction control method.