JPH04167027A - Parallel arithmetic processing unit - Google Patents

Abstract

PURPOSE:To enable more efficient processing to execute by providing an execution control part which controls the execution of an arithmetic result corresponding to a branch state to a branch control part for instruction words. CONSTITUTION:The branch control part 32 for instruction words is equipped with the execution control part 6 which controls the execution of the arithmetic result of an arithmetic unit, which performs the arithmetic of a part other than the branch control part, corresponding to the branch state. Consequently, not only instructions which are executed when branching requirements are not met, but also instructions which are executed when the branching requirements are met can be arranged in instruction words OP1 - OP3 by the specification of the execution control part 6. Therefore, the ratio of the numbers of the instructions which are executed when a branching process is performed and the instructions which are executed when not can be set corresponding to the probability of the branching and the frequency of the setting of NOP(No Operation) codes decreases. Consequently, the performance of the parallel arithmetic processor is improved without increasing the hardware quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel arithmetic processing device that simultaneously executes a plurality of instructions.

[Prior Art] A conventional parallel processing device is configured as shown in FIG. 3, for example.

In the instruction fetch stage, instruction words corresponding to the number of subsequent arithmetic units are fetched from an instruction cache memory (not shown). In this example, since there are four arithmetic units, four instruction words OPO to OP3 are fetched. This instruction word OPO to O
Of P4, instruction word OPO is a branch control instruction,
For example, as shown in FIG. 4, it consists of a branch condition and a displacement.

As a branch condition, a condition for specifying whether or not to branch is written in correspondence with the status of the calculation unit, a flag, etc.

The displacement field contains data that can be added to the program counter value to generate a branch address. On the other hand, normal instructions such as addition and 'g calculation are written in instruction words OPI to OP3.

Four operations NALUo to ALU3 are arranged in the execution stage, and each one has instruction words OPO to OP.
3 is supplied, and each arithmetic unit executes the input instruction word. The calculation results of each of the calculation units ALUO to ALU3 are stored in each register of the store stage.

In this way, in this example, four instructions can be processed in parallel.

When the processing of the first instruction word has been transferred from the instruction fetch stage to the execution stage, the next instruction word is input to the instruction fetch stage. Also in the execution stage, when the process is transferred to the store stage, the next execution process is input. At the final store stage,
It is determined whether the branch condition is satisfied, and if the branch condition is not satisfied, the processing of each stage is continued as is.

However, if the branch condition is met, the instruction at the branch destination will be processed, so the processing of the instruction fetch stage and execution stage at that time, and the operation results of instruction words ○P1 to OP3 in the store stage, will be invalidated. . Then, the instruction word of the branch destination is fetched into the instruction fetch stage, and new processing is started.

In this way, when a branch is taken, the processing in the instruction fetish stage and execution stage immediately before the branch, as well as the calculation results in the store stage, are invalidated.

Conventionally, a code indicating the probability of a branch occurring is written in each instruction word, and a branch prediction mechanism determines this probability. If the probability of branching is high, the instruction word of the branch destination is fetched. was.

[Problem to be solved by the invention] However, when using the branch prediction mechanism in this way,
For example, when it is predicted that the probability of branching is high, as in a loop, it is possible to execute efficient processing to some extent, but as in the case of processing in an O8 program, for example, it is not possible to branch or not. When it is difficult to predict
A valid instruction cannot be set in instruction words OPI to OP3, and a harmless NOP code (No 0 peration) cannot be set.
Code) had to be set. Furthermore, when a branch is established, it is necessary to sufficiently suppress the invalidation of already stored calculation results.

As a result, it was not possible to sufficiently improve processing efficiency.

The present invention has been made in view of this situation, and is intended to enable more efficient processing regardless of whether a branch is established.

[Means for Solving the Problems] A parallel processing device of the present invention includes an arithmetic unit that performs arithmetic operations on a branch control unit of an instruction word, and a plurality of arithmetic units that perform arithmetic operations on other parts; In a parallel arithmetic processing device that includes an instruction fetcher that supplies instruction words corresponding to the number of arithmetic units to the arithmetic units, and a storage unit that stores the results of calculations by the arithmetic units, the branch control unit is configured to The execution of the calculation result of the calculation unit that performs the calculation,
The present invention is characterized in that it includes an execution control unit that performs control in response to a branch state.

[Operations] In the parallel arithmetic processing device configured as described above, the instruction word branch control section is provided with an execution control section that controls execution of the operation result in accordance with the branch state. Therefore, more efficient processing becomes possible.

Embodiment Next, an embodiment of the parallel arithmetic processing device of the present invention will be described.

FIG. 1 shows an embodiment of the format of an instruction word used in the parallel processing device of the present invention.

Also in the present invention, the instruction word is configured corresponding to the number of arithmetic units. In this embodiment, OPO to OF
2 four instruction words can be fetched at once. Each instruction word consists of 32 bits. Of these, the branch condition (8 bits), execution control section (6 bits), and displacement (18 pits) are written in the instruction word OPO of the branch control section.

The branch condition specifies whether or not to branch based on the status of the calculation unit, flags, etc.

Displacement is data that is added to the value of the program counter to generate a branch address. As this displacement, specify the number of the register,
The contents of the register can also be used as a branch address.

The execution control unit controls whether or not to execute the operation results of the instruction words OPI to OP3, and two pits are allocated to each instruction word. The data of these two pits and the execution contents correspond, for example, as follows.

OO... Execute unconditionally 01... Undefined 10... Execute only when branch is taken 11... Execute only when branch is not taken, that is, when the execution control section is (00), the result of the operation is Executed regardless of the established state (considered valid)
. In the case of (10), it is executed when the branch is taken, but it is not executed when the branch is not taken (it is invalidated). Conversely, in case (11), it is executed when the branch is not taken, but not when the branch is taken.

An embodiment of an apparatus for processing instruction words having the format described above is shown in FIG.

Instructions read from the main memory 1 are input to the memory interface 2 via the system bus, and are roughly transferred to the instruction cache memory 3 and stored therein. Further, the operand data read from the main memory device 1 is supplied to the memory interface 2 via the system bus,
Furthermore, it is input to the operand cache memory 8 and stored. The operand data stored in the operand cache memory 8 is loaded into the register file 9 and can be stored. The register file 9 also receives and stores the calculation result from the calculation unit 6 via the store controller 7 as a destination operand.

Fully stored in the instruction cache memory 3 t: Predetermined instructions are fetched into the instruction fetcher 4 as an instruction stream, and some of them are roughly stored in the arithmetic unit 60 of the arithmetic unit 6.
Instruction words corresponding to the numbers ((n+1)) from 6n to 6n ((n+1)) or VLIW (Very Long I n5tructi)
on Word) (long instruction word) to the instruction decoder 5. In other words, when there are four arithmetic units in the arithmetic unit 6 (n=3), IVLIW is 128 (=
4x32) bits.

When n=3, the instruction decoder 5 decodes the input instruction words OPO to OP3 and decodes the corresponding arithmetic unit 60.
Specifies calculation operations such as addition and subtraction of 63 to 63. Further, necessary source operands are supplied from the register file 9 to the computing units 60 to 63.

Arithmetic units 60 to 63 perform arithmetic operations on source operands input from register file 9 in accordance with control signals from instruction decoder 5, and output the arithmetic results to store controller 7. The store controller 7 supplies the input operation result to the register file 9 as a destination operand and stores it.

The data stored in the register file 9 can be read out as needed, passed through the arithmetic units 60 to 63 and the store controller 7, and stored in the operand cache memory 8. Then, this stored data is input to the main storage device 1 via the memory interface 2' and is stored.

As in the case in FIG. 3, instruction words OPO to OP3 output from the instruction fetcher 4 are sent to the instruction decoder 5
The signals are inputted to the corresponding arithmetic units 6Q to 63 via. Arithmetic units 6o to 63 perform predetermined arithmetic operations on the source operands and output the arithmetic results to the store controller 7.

As shown in FIG. 1, the instruction word OPo processed by the arithmetic unit 60 includes a branch condition, an execution control section, and a displacement. When the branch condition is not satisfied, processing is sequentially transferred from a higher stage to a lower stage in each stage of the instruction fetcher 4, instruction decoder 5, arithmetic unit 6, and store controller 7.

When the branch condition is met, a displacement is added to the output of the program counter built into the store controller 7, and the displacement is supplied to the instruction fetcher 4 as a branch address.

As a result, the instruction word of the branch destination can be read out from the instruction fetcher 4, and the process will be executed thereafter.

At this time, it is possible to control the above-mentioned branch prediction mechanism (not shown) so that the processing at each stage of the instruction fetcher 4, instruction decoder 5, and arithmetic unit 6 is less likely to be invalidated. Same as in case.

In the present invention, the calculation results in the store controller 7, which together with the register file 9 constitute a storage section, can be used more effectively.

That is, the branch control unit of the present invention is provided with an execution control unit as shown in FIG. , instructions to be executed when the condition holds can also be placed in OPI to OF2. Therefore, the ratio of the number of instructions executed when a branch is taken and the number of instructions executed when a branch is not taken can be set according to the probability of branching, and the frequency of setting NOP codes is reduced. Thereby, the performance of the parallel processing device can be improved without significantly increasing the amount of hardware.

[Effects of the Invention] As described above, according to the parallel arithmetic processing device of the present invention, the instruction word branch control unit is provided with an execution control unit that controls execution of the operation result in accordance with the branch state. So,
More efficient processing becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the format of an instruction word used in the embodiment of FIG. 2, FIG. 2 is a block diagram showing the configuration of an embodiment of the parallel processing device of the present invention, and FIG. FIG. 4 is a diagram explaining the operation of the parallel arithmetic processing device, and FIG. 4 is a diagram explaining the format of a conventional instruction word. 3...-Instruction cache memory, 4 instruction fetcher, 5
...Instruction decoder, 6--Arithmetic unit, 7--Store controller, 8--Operand cache memory,
9...Register file, 6o to 6n...Arithmetic units. 20゛ 4 parts 7 pieces Figure 3 Figure 4

Claims (1)

[Scope of Claims] An arithmetic unit comprising an arithmetic unit that performs arithmetic operations on a branch control unit and a plurality of arithmetic units that perform operations on other parts of an instruction word; and the instructions corresponding to the number of the arithmetic units. In a parallel arithmetic processing device comprising an instruction fetcher that supplies words to the arithmetic unit, and a storage unit that stores a result of the arithmetic operation by the arithmetic unit, the branch control unit is configured to operate the branch control unit other than the branch control unit. A parallel arithmetic processing device characterized by comprising an execution control unit that controls execution of arithmetic results of arithmetic units in accordance with a branch state.