JPH02742B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides efficient processing by guaranteeing the validity of vector data when a chain of vector registers occurs in a vector processing device using a pipeline system. The present invention relates to a pipeline control method for executing parallel processing of two successive vector instructions.

[Technology background]

Figure 1 shows the schematic configuration of a general vector processing device. In the figure, 1 is a storage device, 2 is an access pipeline, 3 is a vector register (VR), 4 is an arithmetic pipeline, and 5 is a This is an instruction processing section.

As shown in the figure, in the vector processing device, a vector register ( VR) 3 is provided. The calculation is executed between the calculation pipeline 4 and the vector register 3, and only the source data necessary for the calculation or the result data after the calculation is completed is transferred between the vector register 3 and the storage device 1. The access pipeline 2 plays the role of data transfer between the vector register 3 and the storage device 1.

For example, in the case of vector addition of 〓+〓→〓, if each operand of 〓, 〓, 〓 indicates a certain area of the storage device 1, first 〓,
The operand 〓 is loaded into the vector register 3 (for example, vector registers A and B) by the access pipeline 2. Next, after performing the addition of vector registers A and B, the result is stored in a vector register 3 (for example, vector register C), and then stored in an area of the storage device by the access pipeline 2. Figure 2 shows this situation using a time chart.

In Figure 2, VRA, VRB, and VRC represent vector registers A, B, and C, respectively, and
Write writes to a vector register, and
Read represents reading from the vector register.

By the way, if the addition instruction is executed after all vector data has been written to the vector registers VRA and VRB using the vector load instruction, the arithmetic pipeline will have to wait during that time, making it difficult to improve processing performance. Can not. Therefore, as shown in FIG. 2, it is common practice to operate the access pipeline and the calculation pipeline in parallel. In other words, when it is recognized that writing to the vector register has started in vector load, the operation pipeline is immediately activated.
In this case, vector load〓, vector load〓
Write registers VRA, VRB in VR
This shows that there is a register chain from 1 to the operation read registers VRA and VRB. Note that there is register chaining when the same register is used between two consecutive vector instructions.

On the other hand, it goes without saying that if register chaining is not performed from writing to a vector register in the access pipeline to reading to the arithmetic pipeline, the arithmetic pipeline can operate without being aware of the access pipeline. .

When there is a register chain, continuous data transfer to the vector register by the access pipeline may be temporarily interrupted due to bank conflict with other accesses to the storage device, bus conflict, bank busy, etc. There is.

Therefore, when data is no longer being transferred from such a storage device, the entire calculation pipeline is stopped to prevent processing errors from occurring in order to prevent the writing of the vector register from being delayed by the reading of the calculation. things are being done.

In this case, as shown in Figure 2, when an arithmetic pipeline with a register chain is activated successively from a vector load, there is no problem using the above method, but as shown in Figure 3, there is no problem in using the above method. In this case, if another operation The processing performance of the arithmetic pipeline will be degraded since the processing will be stopped until the end of the process.

[Object and structure of the invention]

An object of the present invention is to solve the problem when data transfer from a storage device to a vector register is interrupted.
The operation of an arithmetic pipeline with register chains is
The purpose is to provide a means that can reliably control the required amount at any time, and the configuration for this purpose includes a vector register that can access one or more elements at the same time, and an operation that performs an operation between the vector registers. In a vector processing device equipped with a pipeline and one or more access pipelines that transfer data between a storage device and a vector register, an operation or access that performs a vector register used in the access pipeline and a vector register read operation. Register chain detection means detects the presence or absence of register chain between vector registers used in a pipeline, and when transferring data from a storage device to a vector register, the transfer amount of vector register writing from the start of data transfer and the register Comparing means for detecting the amount of operation or access pipeline operation for performing a vector register read operation after the chain detecting means detects the register chain, and determining the difference between them, and detecting the amount of operation of the vector register read operation or the operation amount of the access pipeline after the chain detecting means detects the register chain; If the data transfer is interrupted, the read operation from the vector register to the pipeline is performed until the difference amount outputted from the comparison means becomes 0, and when the difference amount becomes 0, the pipeline operation is started. Then, when the data transfer from the storage device to the vector register is restarted and the difference amount becomes 1 or more, the operation of the pipeline is restarted, and the data transfer from the storage device to the pipeline is completed. In this case, the read operation from the vector register to the pipeline is performed until the difference amount becomes 0, and the operation of the pipeline is not stopped.

[Embodiments of the invention]

The details of the present invention will be explained below with reference to Examples.

FIG. 4 is a configuration diagram of an arithmetic pipeline control circuit according to an embodiment of the present invention, and FIG. 5 is a timing diagram of an example of the operation of the embodiment circuit of FIG.

In FIG. 4, 6 is a write count circuit, 7
is an arithmetic pipeline operation control circuit, 8 is a subtracter,
9 is a selection gate, 10 is an adder, and 11 is a write count register.

Also, as shown in FIG. 5, the VR write start signal occurs at time a, the register chain detection signal occurs at time b, and the VR write end signal occurs at time c. The VR write signal is a signal that is turned on every time the access pipeline transfers data to the vector register between time points a and c, and by counting the number of signals, the amount of data transferred to the vector register can be determined. The arithmetic pipeline operating signal is a signal that is supplied every cycle when operating the arithmetic pipeline, and instructs to operate the arithmetic pipeline when it is on and to stop it when it is off. The arithmetic pipeline operating signal when register chaining 'is a signal equivalent to the arithmetic pipeline operating signal, and while the arithmetic pipeline operating signal is a signal that instructs the operation/stop of the arithmetic pipeline, the arithmetic pipeline operating signal when register chaining is the same as the arithmetic pipeline operating signal. ' is treated as the same signal as the arithmetic pipeline operation signal after the register chain detection signal is turned on. That is, in the interval T from time a to time b in FIG. 3, the register chain detection signal is not turned on, so the arithmetic pipeline operation signal is turned on, and the register chain operation pipeline operation signal ' is turned off. In the interval from time point b to time point c, the register chain detection signal is generated at time point b, so that the register chain operation pipeline operation signal' is specified in synchronization with the operation pipeline operation signal. Therefore, by counting the number of on-states of the arithmetic pipeline operation signal ′ during register chaining, it is possible to know the amount of operation of the arithmetic pipeline when there is register chaining, that is, the amount of data read from the vector register. . Note that the signals are supplied from an instruction processing unit (not shown), and the signals , . . . are created and supplied within an access pipeline (not shown).

By calculating the difference between these two amounts, the write count circuit 6 knows the amount of data that can be processed and that has been previously written into the vector register, and is independent of the interruption of data transfer to the vector register. This allows the operation of the calculation pipeline to proceed by the amount of data that can be processed.

First, when a VR write start signal is input at time a, the write count register 11 is initialized by the selection gate 9, and thereafter starts counting. In the interval T from time a to time b, the arithmetic pipeline operation control circuit 7 is disabled by the register chain detection signal, and the register chain arithmetic pipeline operation signal' remains off every cycle, so that writing is not possible. Count register 11
counts only n VR write signals. This causes the calculation pipeline to start at point b
Then, the value of the write count register 11 is “n”
It's getting old.

When the register chain detection signal is input at time point b, the arithmetic pipeline operation control circuit 7 is enabled. As a result, the arithmetic pipeline operating signal and register chain arithmetic pipeline operating signal' are turned on every cycle, and the arithmetic pipeline performs an arithmetic operation. On the other hand, if data transfer from the storage device to the vector register (VR) continues normally, the VR write signal also turns on every cycle. Therefore, in the subtracter 8, VR
Since both the write signal and register chain operation pipeline operation signal' are canceled, the output of the subtracter 8 is "0", and the write count register 11 does not count, but starts counting in the first section T. The value n is held as is.

However, as shown between time points b′ and b″ in Figure 3,
If the data transfer to the vector register is interrupted, the VR write signal is not generated during that time, so only the register chain operation pipeline operation signal ' is applied to the (-) input of the subtracter 8, and the write count register is It works to subtract the count value "n" of 11 by "1". As a result, the operation progresses in such a way that the amount of data read to the calculation pipeline catches up with the amount of data written to the vector register, and if we assume that n = "0" at time point b'', then the first calculation is performed. The pipeline operation signal and register chain operation pipeline operation signal' are turned off in the next cycle, instructing to stop the operation of the operation pipeline.

After that, when the data transfer to the vector register is resumed at time point b, the VR write signal also turns on, the write count register 11 counts "1", and the operation pipeline operation signal and register chain operation pipeline operation signal ' is also restored. In the above case, if data transfer to the vector register is resumed before n = "0", the arithmetic pipeline operation signal and the arithmetic pipeline operation signal during register chaining will not turn off, and the arithmetic pipeline operation signal will not turn off. The line never stops working.

Next, at time C, when the VR write end signal turns on, the data transfer to the vector register ends, and the arithmetic pipeline operation control circuit 7 operates in the same way as in section T, so the arithmetic pipeline operation signal turns on. When register chaining occurs, the arithmetic pipeline operating signal 'is turned off, and there is no need to stop the arithmetic pipeline.

In this way, the calculations by the calculation pipeline are
From the time when the arithmetic pipeline is activated, even if data transfer is not performed during or at the end, the arithmetic pipeline is operated by the amount of processable data held by the write count circuit 6 at that time. I try to forgive. In addition, each time the calculation pipeline operates, the write count circuit is decremented (for example, by -1), and the calculation pipeline is stopped only when the amount of data that can be processed becomes 0. There is no need to stop the calculation pipeline, improving performance.

It goes without saying that once the writing to the vector register is completed (time point C), there is no need to stop the arithmetic pipeline.

FIG. 6 shows another embodiment of the arithmetic pipeline control circuit. In the figure, 6 is a write count circuit, 7
is an arithmetic pipeline operation control circuit, 12 is a write count register, 13 is a read count register, 14 and 15 are selection gates, 16 and 1
7 is an adder, and 18 is a write/read difference amount detector.

In this embodiment, the amount of write data and the amount of read data are counted separately and held in a write count register 12 and a read count register 13, respectively. It determines the amount of data that can be processed in the register and controls the arithmetic pipeline operation control circuit 7. Compared to the embodiment shown in FIG. 4, the only difference is the configuration of the write count circuit 6, and the basic function is are the same.

〔Effect of the invention〕

As described above, according to the present invention, the validity of the vector data is always guaranteed even if the data transfer to the vector register is interrupted, regardless of the start point of parallel processing of two vector instructions with a register chain. However, it can be executed with maximum efficiency.

[Brief explanation of drawings]

Figure 1 is a schematic configuration diagram of a general vector processing device, Figure 2 is a time chart showing one example of vector operation processing, and Figure 3 is another example of vector operation processing.
A time chart showing an example; FIG. 4 is a configuration diagram of an arithmetic pipeline control circuit according to an embodiment of the present invention;
5 is a time chart of the embodiment circuit shown in FIG. 4 based on FIG. 3, and FIG. 6 is a block diagram of an arithmetic pipeline control circuit according to another embodiment of the present invention. In the figure, 6 is a write count circuit, 7 is an arithmetic pipeline operation control circuit, 8 is a subtracter, 9 is a selection gate, 10 is an adder, 11 is a write count register, is a VR write start signal, is a register chain detection signal , is VR write end signal, is VR
The write signal is the calculation pipeline operation signal,
' indicates an arithmetic pipeline operation signal during register chaining.

Claims (1)

[Claims] 1. A vector register that can access one or more elements simultaneously; an arithmetic pipeline that performs operations between the vector registers;
In a vector processing device equipped with one or more access pipelines that transfer data between a storage device and a vector register, a vector register used in the access pipeline and an operation that performs a vector register read operation or used in the access pipeline. a register chain detection means for detecting the presence or absence of a register chain between vector registers to be transferred; Comparison means is provided for detecting the operation amount of the vector register read operation or the operation amount of the access pipeline after detecting the register chain, and calculating the difference between them, and the data transfer from the storage device to the vector register is performed. In the case of interruption, the read operation from the vector register to the pipeline is performed until the amount of difference outputted from the comparison means becomes 0, and when the amount of difference becomes 0, the operation of the pipeline is stopped, and then When the data transfer from the storage device to the vector register is resumed and the difference amount becomes 1 or more, the operation of the pipeline is restarted, and when the data transfer from the storage device to the pipeline is completed,
A pipeline control method characterized in that a read operation from a vector register to a pipeline is performed until the difference amount becomes 0, and the operation of the pipeline is not stopped.