JPS63298463A - System bus system - Google Patents

Abstract

PURPOSE:To ensure use of the conventional software as it is even though the packing density of hardware is increased by packing the function elements contained in plural boards into a single sheet of board and adding a register to store a logical slot number for each function element of the board. CONSTITUTION:In a system bus system where plural boards are connected to a back plane bus, the function elements contained in both boards 10 and 20 are packed into a single board 50. Then registers 11, 21, 31 and 32 are provided to store the logical slot numbers for each function element and the logical slot number set when plural boards are used are given to the component elements of each function. Thus the software applied when both boards 10 and 20 are provided can be used as it is. As a result, the conventional software can be used as it is even in case the packing density of boards is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a system bus system in which a plurality of boards used in a processor control system such as a robot control device are connected to a backboom bus, and particularly relates to a system bus system in which a plurality of boards used in a processor control system such as a robot control device are connected to a backboom bus. This relates to a system bus system that is configured so that conventional software can be used as is even when the density is increased.

[Conventional technology]

Typically, a large number of boards are used, such as in a robot control device, and the system configuration changes. This is because the robots to be controlled are used in a variety of ways, and it is desired to control many types of robots with as few types of control devices as possible. This makes it possible to shorten the development time of hardware and software and ensure economic efficiency.

As a processor control system in which the system configuration changes due to such changes in the controlled object, the applicant has
The company filed a patent application on April 18, 2017 for a ``Method of Allocating Board Slot Numbers''. Here, in order to maintain software compatibility, we introduced the concept of "logical slot number" in place of the physical slot number, so that even if the hardware system configuration changes, each board has a logical slot number. The software is assigned a "logical slot number" and controlled under this "logical slot number" to maintain software compatibility. That is, first, a physical slot number is given, the module ID of each board is checked, and a corresponding "logical slot number" is given. This allows existing software to continue to be used even if the number of boards on the hardware changes.

[Problem that the invention seeks to solve]

On the other hand, the packaging density of hardware, especially semiconductors such as LSIs, is improving day by day, and the packaging density of boards is also improving day by day. Therefore, hardware functions that were conventionally mounted on two boards can now be mounted on one board.

An example of this is shown in FIGS. 3(a) and (b). In the figure,
Figure 3(a) shows the conventional system configuration, and Figure 3(b) shows the conventional system configuration.
) is a new, more densely packed system. In the figure, IO is a main processor board, 20 is a sub-processor board, 30 is a memory board, and 40 is an axis control board. In FIG. 3(b), the packaging density has increased, and the memory processor board 10 and sub-processor board 20 can now be mounted on one new board 50.

In this case, as in the case where the system configuration changes, if the conventional software cannot be used, it will be necessary to develop new software, convert the software, etc.

The purpose of the present invention is to respond to such advances in hardware by ``developing a system bus system that uses the concept of logical slot number j so that conventional software can be used as is even when board mounting density increases.'' It is about providing.

[Means for solving problems]

In the present invention, in order to solve the above problems, as shown in FIG. 1, in a system bus system in which multiple boards are connected to a backplane bus, the functions that were composed of multiple boards (10, 20) are improved. It has a board (50) in which elements are mounted on one board, and registers (11, 21, 31, 41) are provided to store logical slot numbers for each functional element, and it is composed of multiple boards. A system bus method is provided, which is characterized in that a logical slot number is given to each functional component to enable software to be used as is when the board is configured with a plurality of boards.

[Effect]

As the packaging density increases, functions mounted on a single board can be implemented by providing a register for storing the logical slot number for each function, and by assigning the logical slot number to this register, the processor can register each functional element or function using the logical slot number. Since the board can be accessed, software compatibility can be maintained.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, 10 is the main processor functional element;
20 is a sub-processor functional element, which in the old system was mounted on an independent board, but in the new system, it is mounted on a single board 50. 30
is a memory board, and 40 is an axis control board. 11.2
1.31 and 41 are registers that store physical slot numbers and logical slot numbers. 15 is a main processor functional element 10 and a sub-processor functional element 2
It is a switching means for switching 0, and is used to access one functional element when accessed from the bus, and is actually processed by the printed board hardware pattern and gate logic.

In FIG. 1, a physical slot number is initially assigned to each register. Add this to register 11.21.31
and the number to the left of 41. At this time, since the main processor functional element 10 and the sub-processor functional element 20 are on the same board, the same physical slot number is set. On the other hand, next register 11.21.
The logical slot numbers listed on the right side of 31 and 41 are assigned. This logical slot number is the logical slot number when the main processor functional element 10 and the sub-processor functional element 20 are mounted on separate boards.

This operation will be explained based on a time chart.

FIG. 2 shows a time chart for setting the logical slot number after the physical slot number has been set. Address buses A4 to A23 are in address cycle 0003 for the first setting of logical slot numbers.
It becomes 0XH. In this cycle, a logical slot number is set from the module ID of each functional element and board. Regarding the board 50, the switching circuit 15 is set to address 0O.
At the time of 030XH, the main processor 10 is accessed, and the register 11 of the main processor 10 is accessed.
The logical slot number 0 is set by referring to the module ID. This is done in cycle TO.

Next, in cycle T1, module I of the memory board 30
D is read and the corresponding logical slot number 2 is written in the register 31. Furthermore, in cycle T2, the ID module of the axis control board 40 is read and the corresponding logical slot number 3 is written into the register 32. Write the logical slot number of each board in this way.

Next, address buses A4 to A23 are at address 0OOBOX.
It becomes H. At this address, the switching circuit 15 of the board 50
selects subprocessor functional element 20 for access from the bus. Therefore, in cycle T3, the module ID of the subprocessor functional element is read and the corresponding logical slot number l is written in the register 21. In this way, conventional software can be used as is by writing the logical slot number of each functional element and board into each register and accessing each board using this logical slot number.

In the above embodiment, a case has been described in which two boards become one, but the same process can be performed even when two or more boards become one.

[Effects of the Invention] As explained above, in the present invention, even when a plurality of boards are mounted on one board, a register is provided for storing a logical slot number for each functional element, and the logical slot number of this register is Since each board is configured to be accessed by slot number, the software used on the old hardware can be used as-is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart diagram of an embodiment of the present invention, and FIGS. 3(a) and (
b) is a diagram showing changes in board mounting;

Claims (2)

[Claims] (1) In a system bus system in which multiple boards are connected to a backplane bus, there is a board in which functional elements configured on multiple boards are mounted on a single board, and a logical slot is provided for each functional element of the board. A register was provided to store the number, and a logical slot number was assigned to each functional element when the board was configured with multiple boards, so that the software could be used as is when the board was configured with multiple boards. A system bus method characterized by: (2) The system bus system according to claim 1, wherein the functional element is configured to switch addresses by switching means of the one board.